Abstract: A design application interacts with an end-user to generate design problem geometry that reflects a design problem to be solved. Various design objectives, design constraints, boundary conditions, and other design criteria may be associated with the design problem geometry via the design application. When the design problem is sufficiently well defined, a client-side solver generates a solution approximation using a coarse multi-objective solver. The client-side solver favors speed over accuracy, and so the solution approximation provides only a rough representation of various attributes of potentially feasible design solutions. Based on the solution approximation, the end-user may correct any omissions, mistakes, and so forth, before executing pay-per-service cloud-based parallel solver.

Abstract: A system for creating an energy performance and predictive model. The system includes a non-transitory computer-readable storage medium which performs the steps obtaining parametric information objects that represent actual physical objects and modifying the parametric information objects by embedding data related to energy performance characteristics unique to the device represented. The system further performs the steps grouping the modified parametric information objects that define actual real world interrelationships to create a complete virtualized project and parsing the virtualized model data set to create a first parsed data set and a second parsed data set. The first parsed data set creates the project system control application, which acts upon and coordinates the actions of the real device through the virtual field bus.

Abstract: Techniques that facilitate overlaying and integrating computer aided design drawings with fluid models are presented. For example, a system includes a modeling component, a machine learning component, and a graphical user interface component. The modeling component generates a three-dimensional model of a mechanical device based on a library of stored data elements. The machine learning component predicts one or more characteristics of the mechanical device based on a machine learning process associated with the three-dimensional model. The machine learning component also generates physics modeling data of the mechanical device based on the one or more characteristics of the mechanical device. The graphical user interface component generates, for a display device, a graphical user interface that presents the three-dimensional model and renders the physics modeling data on the three-dimensional model.

Abstract: A streakline visualization apparatus sets a partial region including a discrete point at a first position on a first streakline in an analysis space as an analysis target region of the discrete point. Based on a velocity of fluid in the analysis target region indicated by fluid information, the apparatus calculates a second position indicating a destination of a particle on the discrete point at a second analysis time point. Next, based on information about a structure in the analysis target region indicated by structure information, the apparatus determines a region occupied by the structure in the analysis target region at the second analysis time point. Next, based on the first and second positions, the apparatus determines whether a second streakline has entered the occupied region. If the second streakline has not entered the occupied region, the apparatus displays the second streakline passing through the second position.

Abstract: Systems and methods for performing power analytics on a microgrid. In an embodiment, predicted data is generated for the microgrid utilizing a virtual system model of the microgrid, which comprises a virtual representation of a topology of the microgrid. Real-time data is received via a portal from at least one external data source. If the difference between the real-time data and the predicted data exceeds a threshold, a calibration and synchronization operation is initiated to update the virtual system model in real-time. Power analytics may be performed on the virtual system model to generate analytical data, which can be returned via the portal.

Abstract: A method comprising: simulating, in a lattice velocity set, movement of particles in a volume of fluid, with the movement causing collision among the particles; based on the simulated movement, determining relative particle velocity of a particle at a particular location within the volume, with the relative particle velocity being a difference between (i) an absolute velocity of the particle at the particular location within the volume and measured under zero flow of the volume, and (ii) a mean velocity of one or more of the particles at the particular location within the volume; and determining, based on the relative particle velocity, a non-equilibrium post-collide distribution function of a specified order that is representative of the collision.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.

Abstract: A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.

Abstract: Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

Abstract: Adjustable integrated circuits and methods for designing the same are provided. In one embodiment, a method of designing an integrated circuit includes determining a plurality of design criteria of the integrated circuit; designing a plurality of circuit blocks of the integrated circuit in accordance with the plurality of design criteria, where one or more circuit blocks in the plurality of circuit blocks include one or more feedback paths; designing a circuit performance monitor, where the circuit performance monitor includes one or more replica feedback paths corresponding to the one or more feedback paths in the one or more circuit blocks, and where the circuit performance monitor is configured to monitor feedback path information of the one or more replica feedback paths; verifying the plurality of circuit blocks and the circuit performance monitor to meet the plurality of design criteria; and producing a verified description of the integrated circuit for manufacturing.

Abstract: An integrated circuit may include a reconfigurable functional circuit block coupled to a microcontroller. The microcontroller may monitor a trigger register that receives trigger signals at a reconfiguration portion. The trigger signals may initiate corresponding reconfiguration operations by triggering the execution of instructions in a reconfiguration sequence program to load appropriate configuration data to configuration registers. The configuration registers may determine the operating mode of the functional circuit block by activating a subcomponent module in the functional circuit block. By providing a reconfiguration port that has full control of the reconfiguration of the functional circuit block, sensitive information regarding the implementation of the functional circuit block, the microcontroller, and connections therebetween may be protected while simplifying the design process for a custom logic circuit generated based on the reconfigurable functional circuit block.

Abstract: An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.

Abstract: We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.

Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.

Abstract: In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.

Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.

Abstract: A method of forming an integrated circuit is provided. The method includes several operations. A semiconductor substrate is received, and a conductive grid is disposed over the semiconductor substrate, wherein the conductive grid includes a plurality of non-continuous conductive lines. A plurality of first conductive lines and a plurality of second conductive lines are selected from the plurality of non-continuous conductive lines. The plurality of second conductive lines is replaced by a plurality of third conductive lines respectively, wherein a space between adjacent third conductive lines is greater than a space between adjacent second conductive lines. A system configured to perform the method is also provided.

Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.

Abstract: Techniques and systems for determining a route from a start point to a target point in an integrated circuit (IC) design using topology-driven line probing are described. Some embodiments can create a data structure to store a set of nodes, wherein each node is located on a horizontal probe or a vertical probe, and wherein each node has a cost. The embodiments can then perform a set of operations in an iterative loop, the set of operations comprising: selecting a lowest cost node from the set of nodes; terminating the iterative loop if the lowest cost node is located at the target point; extending a probe from the lowest cost node if the lowest cost node is not located at the target point; creating at least one new node on the probe or on an ancestor of the probe; and adding the new node to the set of nodes.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.

Abstract: A method of fabricating a semiconductor device includes designing a layout, forming a photomask based on the layout, correcting an optical transmittance of the photomask, and performing a photolithography process using the photomask having the corrected optical transmittance to form a pattern on a substrate. The correcting the optical transmittance of the photomask includes creating an intensity map by capturing light that passes through the photomask, simulating the layout to create a virtual intensity map, and correcting an optical transmittance of a mask substrate of the photomask based on the intensity map and the virtual intensity map.

Abstract: Methods of fabricating semiconductor devices are provided. A method of fabricating a semiconductor device includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via that is electrically connected to the target net; and a crossing net that is electrically connected to the target via on a different level from the target net. The method includes analyzing a peripheral pattern that is adjacent the target net. Moreover, the method includes generating a redundant net, and a redundant via that electrically connects the redundant net and the crossing net. Related layout design systems are also provided.

Abstract: A method of making a mask includes computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the transmission cross coefficient matrix into an ideal transmission cross coefficient (TCC) kernel set for a corresponding ideal optical system and at least one perturbation kernel set with coefficients corresponding to optical defects in the optical system, calibrating a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns, and providing the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the mask using the synthesized mask layout.

Abstract: A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

Abstract: An integrated circuit (IC) structure includes a first active region, a second active region, a first multi-gate structure, a first rail and a second rail. The first active region and the second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, supplies a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and supplies a second supply voltage.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Abstract: Portions of document contents are separated into individually controlled sections on a user interface of a smaller size client device display. A document viewed on a mobile device may include different content portions such as textual content, tables, slides and graphics. Due to a smaller user interface of the mobile device, some portions of the content may extend outside of the user interface and may not all be visible at the same time. The user may use gestures to scroll through and resize the document to view all of the contents. The system may separate each of the different content portions into individual sections and enable the user to control each section separately, such that the user may navigate, resize, and reposition each individual section without affecting the size and position of the remaining sections of the document for optimally viewing the document on the user interface.

Abstract: Disclosed is an approach for implementing an editing tool that can effectively leverage the “contentEditable” feature, while reliably being able to work with structured objects within a document. The approach is particularly useful to implement tools that allow for collaboration with respect to the structured objects.

Abstract: Technology for generating thumbnail images is provided. In one example, a thumbnail image generation method may include receiving a request to generate a thumbnail image of an electronic page. The electronic page may be analyzed to identify content features of the electronic page. A determination of changes to make to a copy of the electronic page may be made based on the content features to form a modified electronic page. The thumbnail image for the electronic page may be generated using at least a portion of the modified electronic page.

Abstract: Systems and methods are disclosed for manually and programmatically remediating websites to thereby facilitate website navigation by people with diverse abilities. For example, an administrator portal is provided for simplified, form-based creation and deployment of remediation code, and a machine learning system is utilized to create and suggest remediations based on past remediation history. Voice command systems and portable document format (PDF) remediation techniques are also provided for improving the accessibility of such websites.

Abstract: From the content of a document, a factual entity that relates to the content of the document is determined. Content for a knowledge panel is requested. A knowledge panel is a user interface element that provides a collection of content related to the factual entity. The contents of the knowledge panel is received for contemporaneous display on the user device with the content of the document.

Abstract: A method described herein includes acts of extracting at least one entity from an arbitrary web page being viewed by an individual on a computing device and comparing the at least one entity with social network data of the individual, wherein the social network data comprises a plurality of messages generated by members of a social network of the individual. The method further includes the acts of identifying at least one message in the plurality of messages based at least in part upon the comparing of the at least one entity with the social network data of the individual and causing the at least one message to be displayed on the web page in conjunction with the at least one entity.

Abstract: Embodiments are disclosed in which a process receives annotation inputs for annotations of a document. The annotation inputs may be grouped together into clusters based at least in part on a functional relationship between the timing of annotation inputs and the paths of the annotation inputs across an electronic display. The annotation inputs may be associated with portions of the document based at least in part on the shape of the paths of the annotation inputs, the sequence of annotation inputs, or the locations of the annotation inputs. Additionally, the paths of the annotation inputs to portions of the document may be modified in response to modifications of the portion of the document data.

Abstract: Systems and methods disclosed herein provide a mechanism for synchronizing comments to an electronic document. An example method may include, receiving, by a processing device of a server, a request of a first user device to access an electronic document that is stored on a remote storage system in a native document format; providing for presentation, via a remote document access user interface at the first user device, data of the electronic document; receiving comment data comprising a plurality of comments of one or more user devices; sending, by the processing device of the server, a message comprising the comment data to a second user device for incorporation into a local copy of the electronic document; and providing, by the processing device of the server, the plurality of comments to the first user device for presentation with the data of the electronic document.

Abstract: A method and system for providing an electronic form are described. The method and system include identifying a visible portion of the electronic form. The electronic form can include a control component at a component location of the electronic form that is operable to receive an input from a user. The method and system can then determine an accessibility state of the control component based on the component location and at least one of a display property of the display and the visible portion. The accessibility state can be a convenient state when the component location is suitable for the display but is in an inconvenient state when the component location is not suitable for the display. When it is determined that the accessibility state is the inconvenient state, the method and system involves displaying a transient control component, or a version of the control component, on the display.

Abstract: Systems and methods are provided for generating tables from print-ready digital source documents. A document is received and one or more text fragments are identified on a rendered page of the document. A wrapping region collection is generated, comprising one or more wrapping regions. A tabular, narrative and label score is generated for each wrapping region. A block type is assigned to each wrapping region based on the scores. A wrapping region group and a block set are generated. One or more tables are generated based on text fragments corresponding to one of the one or more blocks. The text fragments are organized into corresponding fields of the one or more tables.

Abstract: Techniques are described herein that are capable of intelligently updating a collaboration site or a template that may be used to create a new collaboration site. The collaboration site or the template may be updated to include new features based on (e.g., based at least in part on) a likelihood that the new features will be valuable to users. The likelihood that new features will be valuable to the users may be determined (e.g., derived) using heuristics, machine learning, intelligent user experiences, and/or an understanding of user behavior gathered by a service that provides the collaboration site or the template. The likelihood may be compared to a likelihood threshold to determine whether the collaboration site or the template is to be updated. In accordance with this example, the update may be made if the likelihood is greater than or equal to the likelihood threshold.

Abstract: In one embodiment, a domain-name based framework implemented in a digital assistant ecosystem uses domain names as unique identifiers for request types, requesting entities, responders, and target entities embedded in a natural language request. Further, the framework enables interpreting natural language requests according to domain ontologies associated with different responders. A domain ontology operates as a keyword dictionary for a given responder and defines the keywords and corresponding allowable values to be used for request types and request parameters. The domain-name based framework thus enables the digital assistant to interact with any responder that supports a domain ontology to generate precise and complete responses to natural language based requests.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for using a language classification system for generating response messages. A messaging system receives a message transmitted from a first user to a second user, and determines, based on a set of language counter values determined for the second user, a probability value that the second user will respond to the message in a first language and a probability value that the second user will respond to the message in a second language. The language counter values are determined using a text classification model and indicate a number of times that the second user has used the languages in previous messages. Based on the probability values, the messaging system determines that the second user will respond to the message in the first language and causes a set of recommended responses in the first language be presented on the second client device.

Abstract: An input method editor (IME) provides a distributed platform architecture that enables associating multiple applications with the IME to provide extended functionalities. The presentations of the applications, such as skins, may be different from each other and that of the IME. The applications may be represented in a manifest file that is human-readable and editable. The IME collects multiple parameters relating to a user input into a host application including a query input by the user and a scenario of the host application, and selects one or more applications to provide candidates based on a score or ranking of the applications under the collected multiple parameters. Machine-learning may be used to improve the score or ranking. The candidates may include text candidates, rich candidates, and informative candidates.

Abstract: A server computing device, including memory storing a knowledge graph including a plurality of ontology entities. The server computing device may further include a processor configured to receive a tokenized utterance including a plurality of words and one or more metadata tokens. The processor may extract a respective word embedding vector from each word included in the tokenized utterance. Based on a glossary file, the processor may determine a respective ontology entity type of each word included in the tokenized utterance. The processor may extract a character embedding vector from each character included in the tokenized utterance. Based on the plurality of word embedding vectors, the plurality of respective ontology entity types of the words, and the plurality of character embedding vectors, the processor may determine a predefined intention of the tokenized utterance using at least one recurrent neural network. The predefined intention may indicate a target ontology entity type.

Abstract: There is disclosed a system and method for using a knowledge representation to provide relevant information based on environmental inputs. In an embodiment, the system and method considers environmental information from members in a crowd to generate a pool of interests based on the semantic relevance concepts associated with those interests. The most prominent concepts of interest may then be the basis for presenting content to the crowd as a whole. In another embodiment, environmental inputs and other surrounding inputs are considered as a user context. The concepts may be identified as relevant from the environmental context and used to present information relevant to the user given his or her surroundings.