Abstract: A temporary protective film comprising a support film and an adhesive layer provided on one surface or both surfaces of the support film is disclosed. The coefficient of linear expansion at 30° C. to 200° C. of the temporary protective film may be greater than or equal to 16 ppm/° C. and less than or equal to 20 ppm/° C. in at least one in-plane direction of the temporary protective film.

Abstract: A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.

Abstract: A heat dissipation substrate includes a substrate, a heat conducting element, an insulating filling material, a first circuit layer, and a second circuit layer. The substrate has a first surface, a second surface opposite the first surface, and a through groove communicating the first surface with the second surface. The heat conducting element is disposed in the through groove. The heat conducting element includes an insulating material layer and at least one metal layer. The insulating filling material is filled in the through groove for fixing the heat conducting element into the through groove. The first circuit layer is disposed on the first surface of the substrate and exposes a portion of the heat conducting element. The second circuit layer is disposed on the second surface of the substrate. The first circuit layer and the metal layer are respectively disposed on two opposite sides of the insulating material layer.

Abstract: A semiconductor apparatus, including an insulated substrate having a first surface and a second surface that are opposite to each other, a semiconductor element that is mounted on the first surface of the insulated substrate, and a cooler for cooling the semiconductor element. The cooler includes a heat dissipation board having a bonding surface and a heat dissipation surface that are opposite to each other, the bonding surface being bonded to the second surface of the insulated substrate, a plurality of fins provided on the heat dissipation surface of the heat dissipation board, and a cooling case having a recess accommodating the plurality of fins, an inner wall surface of the cooling case being in the recess. The heat dissipation surface is provided with a plurality of engagement pieces that position the cooling case by engaging portions of the inner wall surface of the cooling case.

Abstract: To provide a method of manufacturing power module substrate board at high productivity and a ceramic-copper bonded body in which warps are reduced. In a bonded body-forming step, a circuit layer-forming copper layer consisting of a plurality of first copper layers is formed by arranging and bonding a plurality of first copper boards on a first surface of a ceramic board, and a metal layer-forming copper layer consisting of a second copper layer with a smaller arrangement number than that of the first copper layers is formed by bonding a second copper board having a larger planar area than that of the first copper board and a smaller thickness than that of the first copper board so as to cover at least two of adjacent substrate board-forming areas on a second surface of the ceramic board among the substrate board-forming areas partitioned by the dividing groove.

Abstract: The present subject matter relates to composite films for heat dissipation. In an example implementation of the present subject matter, a composite film for heat dissipation comprises a conductive material layer for thermal conduction of heat; and a polymer layer disposed over the conductive material layer to provide insulation from the heat.

Abstract: A highly reliable electronic device that efficiently dissipates generated heat and a method for manufacturing the electronic device are provided. The electronic device includes mount board, heat generating component mounted on mount board, pressing component provided above heat generating component, and film provided between heat generating component and pressing component. Further, liquid heat conductive material is provided between heat generating component and film and between pressing component and graphite-based carbonaceous film. Film contains graphite-based carbon and is compressed to predetermined compressibility by pressing component.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

Abstract: A power control module includes a power device having a first side and a second side opposite from the first. The power control module includes a printed wiring board (PWB) spaced apart from the first side of the power device. The PWB is electrically connected to the power device. A heat sink plate is soldered to a second side of the transistor for heat dissipation from the transistor. The PWB and/or the heat sink plate includes an access hole defined therein to allow for access to the transistor during assembly. A method of assembling a power control module includes soldering at least one lead of a power device to a printed wiring board (PWB), pushing the power device toward a heat sink plate, and soldering the power device to the heat sink plate.

Abstract: A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.

Abstract: A semiconductor device includes: a semiconductor element; an element conductor having an element mounting surface on which the semiconductor element is mounted; a connection conductor that is arranged apart from the element conductor and has a connection surface on an upper part thereof; a connecting line connecting the semiconductor element and the connection surface of the connection conductor; and an encapsulation resin that encapsulates the semiconductor element, the element conductor, the connection conductor, and the connecting line, wherein: a parasitic capacitance reducing structure is provided in at least one of facing side surfaces of the element conductor and of the connection conductor, the facing side surfaces being arranged to face each other.

Abstract: A lead frame wiring structure including first and second bonding parts positioned apart from each other, and a coupling part extending in a first direction to couple the first and second bonding parts. The coupling part includes a coupling face section, and first and second leg sections extending respectively from two opposite end portions of the coupling face section toward the first and second bonding parts. The first bonding part includes a wide section having a side edge portion and a peripheral section adjacent to the side edge portion in a second direction, and a narrow section protruding in the first direction from the side edge portion. In the coupling part, the coupling face section is spaced apart from the two bonding parts in a third direction, and the first leg section is connected to the peripheral section of the first bonding part. The first to third directions are perpendicular to one another.

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

Abstract: A circuit carrier includes a substrate, a laminar circuit structure, a metal heat slug, a first fixing piece, and a second fixing piece. The laminar circuit structure is disposed over the substrate and includes a plurality of dielectric layers and circuits in the dielectric layers. The metal heat slug is disposed in the laminar circuit structure. The first fixing piece is disposed on the first side of the upper surface of the metal heat slug. The second fixing piece is disposed on the second side of the upper surface of the metal heat slug, wherein the first side is perpendicular to the second side. A method of manufacturing a circuit carrier is also provided herein.

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

Abstract: A semiconductor assembly includes a carrier element with a first carrier element conductor path, a semiconductor, an electrically insulating element having a first insulating element conductor path, and a first spacer element. The semiconductor is connected electrically and mechanically on a first semiconductor side via a first connecting material to the first carrier element conductor path, The semiconductor is connected on a second semiconductor side, which faces away from the first semiconductor side of the semiconductor, via a second connecting material to the first insulating element conductor path, which is arranged on a first insulating element side of the electrically insulating element, The first spacer element is arranged for maintaining a distance between the carrier element and an assembly element facing toward the second semiconductor side of the semiconductor and is connected mechanically to both the carrier element and the assembly element.

Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Abstract: An electronic module includes a power supply wiring line disposed on a substrate along a first side and connected to a power supply terminal, a ground wiring line disposed on the substrate along a second side and connected to a ground terminal, and first to third half bridges each having a high-side switch and a low-side switch connected in series between the power supply wiring line and the ground wiring line. Connection points of the high-side switches and the low-side switches are connected to first to third motor terminals and also connected in parallel to one another. The first motor terminal, the second motor terminal, and the third motor terminal are disposed between the power supply terminal and the ground terminal.

Abstract: A fan-out chip package assembly with fine pitch silicon through via uses one or more silicon interposers in the bottom package as interconnections between the top package and the substrate. The one or more partially distributed silicon interposers may be disposed in the same layer of the bottom semiconductor die according to the design requirement of the fan-out contact pads of the top package, allowing more design freedom of the top high level chips.

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Abstract: A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A semiconductor package is provided including a package substrate. The package substrate includes a substrate pattern and a substrate insulation layer at least partially surrounding the substrate pattern. The package substrate has a groove. An external connection terminal is disposed below the package substrate. An embedded semiconductor device is disposed within the groove of the package substrate. The embedded semiconductor device includes a first substrate. A first active layer is disposed on the first substrate. A first chip pad is disposed on the first active layer. A buried insulation layer is disposed within the groove of the package substrate and at least partially surrounds at least a portion of a lateral surface of the embedded semiconductor device. A mounted semiconductor device is disposed on the package substrate and is connected to the package substrate and the embedded semiconductor device.

Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.

Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s

Abstract: An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.

Abstract: A semiconductor device and method for forming same are provided. The method for forming a semiconductor device includes: providing a base; forming an interlayer dielectric layer over the base; forming contact holes by etching the interlayer dielectric layer; forming a barrier layer over the base in the contact holes; and forming a metal layer over the barrier layer. The contact holes exposed a portion of a surface of the base. The metal layer fully filled the contact hole.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: A semiconductor structure of a work unit module includes an encircling noise-resistance structure and a P-type substrate being defined with a chip region and a surrounding region surrounding the chip region. The surrounding area includes two first strip regions and two second strip regions. Each of the first strip regions is located between the second strip regions, and each of the second strip regions is located between the first strip regions. The encircling noise-resistance structure is located on the surrounding area, and includes first arrangement units and second arrangement units. The first arrangement unit is arranged in one of the first strip regions in a single row. The second arrangement unit is arranged in one of the second strip regions in a single row, and the long axis direction of the second arrangement unit is different from the long axis direction of the first arrangement unit.

Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.

Abstract: A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.

Abstract: An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S>?·R2.

Abstract: A package is disclosed. In one example the package comprises a carrier having a plurality of leads and an electronic component mounted on the carrier and comprising at least one pad. An impedance structure electrically couples the at least one pad with the carrier so that, at different ones of the leads, different impedance values of the impedance structure can be tapped.

Abstract: Disclosed is an antenna apparatus including a substrate having a cavity in a first outer surface thereof. The substrate has a sidewall defining a portion of the cavity, and a first edge contact is formed at the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact. An antenna element, disposed at a second outer surface of the substrate opposite the first outer surface, is electrically connected to RF circuitry within the IC chip through a conductive via extending within the substrate.

Abstract: A cryptographic device (100) arranged to compute a target block cipher (Bt) on an input message (110), the device comprising a first and second block cipher unit (121, 122) arranged to compute the target block cipher (Bt) on the input message, and a first control unit (130) arranged to take the first block cipher result and the second block cipher result as input, and to produces the first block cipher result only if the block cipher results are equal.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.

Abstract: A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Abstract: Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.

Abstract: An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.

Abstract: A metal particle aggregate includes metal particles and an organic substance. The metal particles include first particles that contain one or both of silver and copper in an amount of 70% by mass or more relative to 100% by mass of all metals and have a particle diameter of 100 nm or more and less than 500 nm at a ratio of 20 to 30% by number, and include second particles that have a particle diameter of 50 nm or more and less than 100 nm, and third particles that have a particle diameter of less than 50 nm at a ratio of 80 to 70% by number in total. Surfaces of the first to third particles are covered with the same protective film.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, at least one conductive clip, and a heat dissipation baseplate. The heat dissipation insulating substrate has a first surface and a second surface opposite thereto, and the power devices form a bridge circuit topology and are disposed on the first surface, wherein active regions of at least one of the power devices are flip-chip bonded to the first surface. The conductive clip is configured to electrically connect at least one of the power devices to the first surface, and the heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate.

Abstract: A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Abstract: The present disclosure relates to an electrode connection element, a light emitting apparatus including the same, and a method for manufacturing the light emitting apparatus, and more particularly, to an electrode connection element, a light emitting apparatus including the same, and a method for manufacturing the light emitting apparatus, which are for electrically connecting an electrode terminal and an external drive circuit. An electrode connection element according to an exemplary embodiment includes: an upper connection member coming into contact with an upper surface of an electrode terminal formed on a substrate; a lower connection member configured to support a lower surface of the substrate; a connection member configured to connect the upper connection member and the lower connection member to each other.