Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.

Abstract: The present application relates to an array substrate, a display panel and a method of manufacturing the same, the array substrate comprising a substrate, a plurality of active switches, a color filter layer, a spacer unit layer, and an electrode layer formed on the color filter layer and the spacer unit layer.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a liquid crystal display panel, and a liquid crystal display apparatus, which can solve a problem that an independent backlight of the related liquid crystal display device is easy to cause light leakage, resulting in a thicker product. Both a light emitting structure and an array structure are disposed on the array substrate of the present disclosure, wherein a control device of the light emitting structure can control the light emitting source to emit light. That is, in the present disclosure, the light emitting structure is directly formed in the array substrate, which is equivalent to a built-in light emitting source, so that it is no longer necessary to adhere an external backlight, and no adhesive gap is generated to cause light leakage, and the thickness of the product can be reduced.

Abstract: A display device, and method for manufacture, having a substrate; a first thin film transistor (TFT) on the substrate, the first TFT having a first active layer, a first gate insulator, and a first gate electrode; a second TFT on the substrate, the second TFT having a second active layer, a second gate insulator and a second gate electrode. The first gate insulator is disposed between the first gate electrode and the first active layer, and the first gate insulator is in contact with the first active layer. The second gate insulator is disposed between the second gate electrode and the second active layer, and the second gate insulator is in contact with the second active layer. The first active layer is a different material than said second active layer, and a hydrogen concentration of the second gate insulator is less than a hydrogen concentration of the first gate insulator.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The method of manufacturing a display substrate includes manufacturing a plurality of gate insulation layers having different thicknesses on a base substrate in one patterning process.

Abstract: The disclosure discloses a display panel, a method for driving the same, and a display device, where a control electrode is arranged on the side of an active layer of a thin film transistor away from a gate electrode, and the thickness of a buffer layer between the control electrode and the active layer is controlled so that the buffer layer is thicker than a gate insulation layer between the gate electrode and the active layer, to adjust the distance between the control electrode and the active layer to be larger than the distance between the gate electrode and the active layer; and at least when a gate off voltage is applied to the gate electrode so that the thin film transistor is switched off, a first control voltage is applied to the control electrode to vary a voltage Vg of the thin film transistor.

Abstract: The present disclosure provides a display device including an array substrate. At least one wiring on array is arranged on a surface of the array substrate, the wiring on array including a plurality of signal wires, and all the signal wires of the wiring on array being the same in impedance and different in length and in cross-sectional area. At least one first driving component is arranged at one side of the array substrate, adjacent first driving components being electrically connected via one wiring on array. At least one second driving component is arranged at the same side or different sides of the array substrate as the first driving member, adjacent second driving components being electrically connected via one wiring on array or adjacent first and second driving components being electrically connected via one wiring on array.

Abstract: The invention provides an array substrate and manufacturing method thereof.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes: a plurality of pixel zones in an array on a base substrate, where each pixel zone includes a pixel electrode, a common electrode, a compensation electrode, and a control circuit. The compensation electrode is insulated from the common electrode, the orthographic projection of the compensation electrode on the base substrate has an overlap area with the orthographic projection of the pixel electrode on the base substrate, and the orthographic projection of the common electrode on the base substrate has an overlap area with the orthographic projection of the pixel electrode on the base substrate; and the control circuit is configured to connect the pixel electrode with the compensation electrode while the pixel electrode is being charged.

Abstract: A liquid crystal display device comprises a display panel, a signal generator, a plurality of wires, and a controller. The display panel includes a plurality of pixel columns, the pixel columns each extending along source lines of the display panel and each having an input end and a plurality of pixels connected to the input end, with the pixels receiving data signal from the input end. The signal generator has a plurality of output ends arranged in a first direction of the signal generator with respect to each other. The wires connect the output ends of the signal generator to the input ends of the pixel columns, respectively. The controller varies voltage waveform of the data signal at the output ends of the signal generator according to location of the output ends of the signal generator.

Abstract: The present disclosure provides a conductive wire structure, a manufacturing method thereof, an array substrate and a display device. The conductive wire structure includes a first conductive wire and a second conductive wire on a first plane, wherein a connection end of the first conductive wire is spaced apart from a connection end of the second conductive wire by a gap so as to discharge charges accumulated on the first conductive wire and the second conductive wire through the gap; an electrical connector connected to the connection end of the first conductive wire and the connection end of the second conductive wire, respectively, wherein a part of the electrical connector is located on a second plane different from the first plane.

Abstract: The present application discloses a method of fabricating an array substrate. The method includes forming a first conductive material layer on a base substrate; forming an insulating layer on a side of the first conductive material layer distal to the base substrate, the insulating layer formed to cover a first part of the first conductive material layer, exposing a second part of the first conductive material layer; over-etching the first conductive material layer to remove the second part of the first conductive material layer, and remove a portion of a periphery of the first part of the first conductive material layer to form a recess between the insulating layer and the base substrate, thereby forming a first electrode; and subsequent to forming the first electrode and the recess, annealing the insulating layer to mobilize a portion of the insulating layer above the recess and fill the recess with a mobilized insulating material.

Abstract: A method for transferring light emitting elements precisely during manufacture of display panels includes providing light emitting elements; providing a first electromagnetic plate defining magnetic adsorption positions; providing a receiving substrate defining receiving areas; energizing the first electromagnetic plate to magnetically adsorb one light emitting element at one adsorption position; facing the first electromagnetic plate to the receiving substrate; and transferring the light emitting elements to one receiving area of the receiving substrate.

Abstract: The present disclosure relates to a manufacturing method of LTPS TFT substrate and the LTPS TFT substrate. With respect to the manufacturing method, after the gate insulation layer is formed, the gate insulation layer is doped with nitrogen by a plasma containing nitrogen so as to increase the positive charges within the gate insulation layer. As such, the P-type TFT threshold voltage can be negatively shifted so as to enhance the splash screen issue.

Abstract: An array substrate and a method of manufacturing the same are provided. The method of manufacturing an array substrate includes: forming a black matrix and an organic insulating pattern on a base substrate with a thin film transistor formed thereon, wherein the black matrix and the organic material pattern are formed by using an identical mask.

Abstract: An image sensor includes a polarizer array and a depth pixel array. The polarizer array may include first to fourth unit pixels, which are arranged in a first direction and a second direction crossing each other, and may include polarization gratings respectively provided in the first to fourth unit pixels. The polarization gratings of the first to fourth unit pixels may have polarization directions different from each other. The depth pixel array may include depth pixels corresponding to the first to fourth unit pixels, respectively. Each of the depth pixels may include a photoelectric conversion device and first and second readout circuits, which are connected in common to the photoelectric conversion device.

Abstract: A high degree of phase difference detection accuracy can be obtained using a phase difference pixel with a simpler configuration. A solid-state image-capturing device includes a pixel array unit in which a plurality of pixels including a phase difference pixel which is a pixel for focal point detection and an image-capturing pixel which is a pixel for image generation are arranged in a two-dimensional array. In this case, a predetermined layer between a light shielding layer and a micro lens formed in the image-capturing pixel has a higher refraction index than a refraction index of the predetermined layer formed in the phase difference pixel. The technique of the present disclosure can be applied to, for example, a back-illuminated-type solid-state image-capturing device and the like.

Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure includes a first insulating layer and an etch stop layer, the first insulating layer extends from the front surface into the substrate, the etch stop layer is between the first insulating layer and the substrate, and the etch stop layer, the first insulating layer, and the substrate are made of different materials. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure is in direct contact with the etch stop layer, the second isolation structure surrounds the light-sensing region, and the second isolation structure includes a light-blocking structure.

Abstract: A semiconductor device is operated for sensing incident light and includes a carrier, a device layer, and a semiconductor layer. The device layer is disposed on the carrier. The semiconductor layer is disposed on the device layer. The semiconductor layer includes light-sensing regions. The semiconductor layer has a first surface and a second surface opposite to the first surface that is adjacent to the device layer. The second surface has a lattice plane which is tilted with respect to a basal plane, and the semiconductor layer has various pit portions arranged on the second surface.

Abstract: An optical semiconductor device includes a semiconductor substrate having a plurality of photoelectric conversion parts and having a trench formed to separate the plurality of photoelectric conversion parts from each other, an insulating layer formed on at least an inner surface of the trench, a boron layer formed on the insulating layer, and a metal layer formed on the boron layer.

Abstract: A photoelectric conversion device has an isolation structure. First and second isolation portions are provided between first and second photoelectric conversion elements. The first isolation portion extends from a first plane of a semiconductor layer to a position corresponding to at least a quarter of a length from the first plane to a second plane of the semiconductor layer. The second isolation portion extends from the second plane of the semiconductor layer to a position corresponding to at least a quarter of the length from the first plane to the second plane.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.

Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.

Abstract: To solve at least one of various problems in an image sensor in a 2PD scheme. A solid-state image pickup element includes a plurality of pixels each including a photoelectric conversion element formed on a silicon substrate, in which some pixels in the plurality of pixels each have the photoelectric conversion element partitioned by a first-type separating region extending in a plate shape in a direction along a thickness direction of the silicon substrate, and other pixels in the plurality of pixels each have the photoelectric conversion element partitioned by a second-type separating region formed with a material different from a material of the first-type separating region, the second-type separating region extending in a plate shape in the direction along the thickness direction of the silicon substrate.

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

Abstract: A light-emitting device includes: a substrate; a unit light-emitting area disposed on the substrate; first and second electrodes disposed in the unit light-emitting area to be separated from each other; a plurality of rod-shaped LEDs disposed between the first and second electrodes; a reflective contact electrode disposed on opposite ends of the rod-shaped LEDs to electrically connect the rod-shaped LEDs to the first and second electrodes; and a light-transmitting structure disposed between the first and second electrodes and extending to cross the rod-shaped LEDs.

Abstract: Provided is a display device including a pixel circuit, a first insulation layer covering the pixel circuit, a first barrier disposed on the first insulation layer and extending in a first direction, a second barrier separated from the first barrier and extending in the first direction and spaced apart from the first barrier layer in a second direction substantially perpendicular to the first direction, a first electrode disposed on the first barrier and electrically connected to the pixel circuit, a second electrode disposed on the second barrier and separated from the first electrode, a second insulation layer disposed on the first electrode and the second electrode with a rubbing groove provided therein in the second direction, and a light emitting element aligned along the rubbing groove on the second insulation layer and electrically connected to the first electrode and the second electrode.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: The invention comprises a novel composite seed layer with lattice-matched crystalline structure so that an excellent epitaxial growth of magnetic pinning layer along its FCC (111) orientation can be achieved, resulting in a significant enhancement of PMA for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a dielectric structure over a substrate. The integrated chip further includes a memory device having a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the plurality of lower interconnect layers. A sidewall spacer continuously extends from an outermost sidewall of the data storage structure to below an outermost sidewall of the bottom electrode.

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.

Abstract: A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: The present technology relates to a solid-state image sensor, a photoelectric conversion film, an electron blocking layer, an imaging apparatus, and an electronic device that can appropriately photoelectrically convert light of specific wavelengths with high spectral characteristics and high photoelectric conversion efficiency. A photoelectric conversion layer or an electron blocking layer is configured with a photoelectric conversion film made of only a compound represented by Chemical Formula (1). The present technology can be applied to a solid-state image sensor.

Abstract: A display device comprises a substrate provided with a first subpixel area and a second subpixel area, a first electrode provided on the substrate, including a first sub electrode provided in the first subpixel area and a second sub electrode provided in the second subpixel area, an organic light emitting layer including a first organic light emitting layer arranged on the first sub electrode and a second organic light emitting layer arranged on the second sub electrode, and a second electrode arranged on the organic light emitting layer, wherein the first organic light emitting layer includes a first pattern layer, a second pattern layer provided on the first pattern layer and a third pattern layer provided on the second pattern layer, the second organic light emitting layer includes a first pattern layer, a second pattern layer provided on the first pattern layer and a third pattern layer provided on the second pattern layer, the first pattern layer of the first organic light emitting layer is spaced apart

Abstract: A pixel structure of an organic light emitting diode display comprises a substrate and a plurality of pixels arranged on the substrate. The plurality of pixels is closely arranged. Each of the pixels is a light-emitting region. Each of the pixels comprises a plurality of sub-regions arranged in at least one column. Each sub-region of each of the column of the pixels comprises a color sub-pixel, a transparent sub-pixel or a sensing component. At least one of the pluralities of sub-regions of each pixel is the sensing component and the sensing component is arranged in the light-emitting region. The pixel structure of the organic light emitting diode display of the disclosure has a sensing function in addition to the display function, and at the same time the such arrangement enables the display to have a resolution of more than 500 ppi.

Abstract: A display device includes a first pixel, a second pixel, and a third pixel. The common electrodes of the first and second pixels have an integrated shape. The hole control layers of the first and second pixels have an integrated shape. The electron control layers of the first and second pixels have an integrated shape. The common electrode, the hole control layer or the electron control layer of the third pixel may be separated from the first pixel and the second pixel.

Abstract: A display substrate includes a substrate, a pixel-defining layer configured to define a plurality of sub-pixel regions, and a plurality of sub-pixels having at least two colors, each arranged within each of the plurality of sub-pixel regions. The pixel-defining layer and the plurality of sub-pixels are disposed over the substrate. The pixel-defining layer includes a plurality of first pixel-defining portions and a plurality of second pixel-defining portions. Each of the plurality of first pixel-defining portions is configured to separate neighboring sub-pixels of different colors. Each of the plurality of second pixel-defining portions is configured to separate neighboring sub-pixels of the same color. At least one of the plurality of second pixel-defining portions has a smaller width than any one of the plurality of first pixel-defining portions.

Abstract: The disclosure relates to an OLED display substrate, a manufacturing method and a display apparatus. The OLED display substrate comprises a base substrate, and a plurality of light-emitting elements and a plurality of pixel defining layers formed on the base substrate, wherein a pixel defining layer is located between any two adjacent light-emitting elements of the plurality of light-emitting elements; and a surface of the pixel defining layer facing away from the base substrate comprises an accommodating portion, a bottom surface of the accommodating portion and the surface of the pixel defining layer facing away from the base substrate are located at different planes, and an orthographic projection of the accommodating portion on the base substrate does not overlap with an orthographic projection of the plurality of light-emitting elements on the base substrate. The method for manufacturing the OLED display substrate is configured to manufacture the above OLED display substrate.

Abstract: A display substrate is provided. The display substrate includes a first chromogenic layer; a plurality of first columns of light emitting elements on the first chromogenic layer; a second chromogenic layer on a side of the plurality of first columns of light emitting elements away from the first chromogenic layer; and a plurality of second columns of light emitting elements on a side of the second chromogenic layer away from the first chromogenic layer. The plurality of first columns of light emitting elements are arranged along substantially a same direction as the plurality of second columns of light emitting elements. The plurality of second columns of light emitting elements are spaced apart by a plurality of inter-column gap regions respectively. A respective one of the plurality of first columns of light emitting elements is at least partially in a respective one of the plurality of inter-column gap regions.

Abstract: A display device achieves a high resolution and a low power consumption through provision of subpixels each including a single light emitting layer and subpixels each including a plurality of overlapping light emitting layers. In the display device, it is also unnecessary to increase the number of expensive fine metal masks even for rendering of various grayscales. In addition, in the display device, different light emitting layers overlap with each other, and a charge generation layer is disposed between the overlapping light emitting layers, and, as such, emission of a secondary color can be achieved without necessity of a material for an additional light emitting layer of the secondary color.

Abstract: An organic light-emitting display apparatus in which a plurality of pixels are arranged in a first direction and a second direction crossing the first direction includes: an organic light-emitting device disposed on a substrate, wherein the organic light-emitting device is included in each of the plurality of pixels; a pixel-defining film covering edges of a pixel electrode of the organic light-emitting device and having an opening exposing a portion of the pixel electrode to define an emission region; and a conductive layer between the substrate and the organic light-emitting device. The conductive layer includes first extension portions extending in the first direction and second extension portions extending in the second direction. The emission region of each of the plurality of pixels overlaps one of cross portions where the first extension portions and the second extension portions cross each other.

Abstract: A color control member includes a substrate including a first pixel area and a second pixel area; a first color conversion layer converting incident light on the first color conversion layer to light of a first color, the light of the first color being emitted from the first color conversion layer and through the first pixel area; a second color conversion layer converting incident light on the second color conversion layer to light of a second color, the light of the second color being emitted through the second color conversion layer and through the second pixel area; and a partition wall disposed between the first color conversion layer and the second color conversion layer to correspond to a light-blocking area of the substrate in which the light emitted from the first color conversion layer or the second color conversion layer is blocked from being emitted to the other thereof.

Abstract: An OLED module can include a panel, a middle frame coupled to a rear surface of the panel, a PCB assembly provided at the outside of the panel, connected to the panel and folded to be arranged on a rear surface of the middle frame, and a back cover coupled to an outer surface of the middle frame provided with the PCB assembly arranged thereon.