Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Alx1Ga1-x1N. The first nitride region includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second nitride region includes Alx2Ga1-x2N. The second nitride region includes sixth and seventh partial regions. The first insulating film includes a first insulating region and is between the third partial region and the third electrode. The third partial region has a first surface opposing the first insulating region. The fourth partial region has a second surface opposing the sixth partial region.

Abstract: A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region.

Abstract: A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.

Abstract: A plurality of trench gate electrodes are formed from an upper surface to reach an intermediate depth of an n-type SiC epitaxial substrate including an n-type drain region on a lower surface and an n-type source region on an upper surface in contact with the source region to be arranged in a direction along the upper surface. Here, at least three side surfaces among four side surfaces of each of the trench gate electrodes having a rectangular planar shape are in contact with a p-type body layer below the source region. In addition, a JFET region in the SiC epitaxial substrate and a source electrode connected to the source region immediately above the JFET region extend along a direction in which the plurality of trench gate electrodes are arranged.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.

Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.

Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Abstract: A TFT substrate includes a plurality of antenna element regions each including a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate further includes a source metal layer including a source electrode of the TFT, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT, a semiconductor layer of the TFT, a gate insulating layer formed between the semiconductor layer and the gate metal layer, wherein the source metal layer further includes the patch electrode. The TFT substrate further includes a source terminal portion arranged in a non-transmitting/receiving region, and the gate metal layer further includes a source terminal upper connection portion of the source terminal portion.

Abstract: The present application provides a thin film transistor, a method of fabricating a thin film transistor and an array substrate. The thin film transistor includes: a gate electrode on a substrate and having first and second side surfaces facing each other; and an active layer between the first side surface and the second side surface of the gate electrode and having a third side surface and a fourth side surface. The third side surface of the active layer and the first side surface of the gate electrode face and are spaced apart from each other, the fourth side surface of the active layer and the second side surface of the gate electrode face and are spaced apart from each other, and at least one portion of the gate electrode is in the same range as at least one portion of the active layer in a height direction.

Abstract: A display apparatus includes: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between a first area and a second area and bent along a bending axis are defined; a first thin-film transistor (“TFT”) and a second TFT; and a first conductive layer and a second conductive layer. The first TFT includes: a first active layer including polycrystalline silicon; a first gate electrode; and a first electrode disposed at a level which is the same as a level of the first conductive layer, and the second TFT includes: a second active layer including an oxide semiconductor; a second gate electrode; and a second electrode disposed at a level which is the same as a level of the second conductive layer.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A semiconductor device with excellent electric characteristics is provided. The semiconductor device includes an oxide in a channel formation region. The semiconductor device includes the oxide over a substrate, a first insulator over the oxide, a second insulator over the first insulator, a third insulator, and a conductor over the third insulator. The oxide and the first insulator are in contact with each other in a region. An opening exposing the oxide is provided in the first insulator and the second insulator. The third insulator is placed to cover an inner wall and a bottom surface of the opening. The conductor is placed to fill the opening. The conductor has a region overlapping with the oxide with the third insulator between the conductor and the oxide. The first insulator contains an element other than a main component of the oxide.

Abstract: A TFT and a method for manufacturing the TFT, an array substrate, and a display device are provided. An active layer of the TFT includes a channel region, a first conductive region and a second conductive region, and the channel region is arranged between the first conductive region and the second conductive region. The channel region includes a first side and a second side, the first side is opposite to the second side, the first side is in contact with a third side of the first conductive region, the second side is in contact with a fourth side of the second conductive region, and a length of the first side is greater than a length of the third side.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

Abstract: Provided is a semiconductor apparatus in which the buried region includes an end portion buried region continuously disposed from a region below the contact opening up to a region below the interlayer dielectric film while passing below an end portion of the contact opening in a cross section perpendicular to the upper surface of the semiconductor substrate, and the end portion buried region disposed below the interlayer dielectric film is shorter than the end portion buried region disposed below the contact opening in a first direction in parallel with the upper surface of the semiconductor substrate.

Abstract: An anti-reflection coating has an average total reflectance of less than 10%, for example less than 5.9% such as from 4.9% to 5.9%, over a spectrum of wavelengths of 400-1100 nm and a range of angles of incidence of 0-90 degrees with respect to a surface normal of the anti-reflection coating. An anti-reflection coating has a total reflectance of less than 10%, for example less than 6% such as less than 4%, over an entire spectrum of wavelengths of 400-1600 nm and an entire range of angles of incidence of 0-70 degrees with respect to a surface normal of the anti-reflection coating.

Abstract: The present disclosure describes methods of forming a colored conductive ribbon for a solar module which includes combining a conductive ribbon with a channeled ribbon holder, applying a color coating to at least the conductive ribbon within the channel, curing the color coating on the conductive ribbon, and separating the conductive ribbon from the channeled holder.

Abstract: Methods and apparatus form a photon absorber layer of a photodiode with characteristics conducive to applications such as, but not limited to, image sensors and the like. The absorber layer uses a copper-indium-gallium-selenium (CIGS) material with a gallium mole fraction of approximately 35% to approximately 70% to control the absorbed wavelengths while reducing dark current. Deposition temperatures of the absorber layer are controlled to less than approximately 400 degrees Celsius to produce sub-micron grain sizes. The absorber layer is doped with antimony at a temperature of less than approximately 400 degrees Celsius to increase the absorption.

Abstract: The disclosure discloses a photovoltaic cell assembly, a photovoltaic cell array, and a solar cell assembly.

Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include Ill nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.

Abstract: A light-emitting diode (LED) substrate and a manufacturing method thereof, and a display device are provided. The LED substrate includes a receiving substrate, the receiving substrate is provided thereon with a pixel definition layer and a plurality of LED units, the pixel definition layer defines a plurality of sub-pixel regions, each of the plurality of sub-pixel regions is configured to receive at least one of the plurality of LED units, and a solder point and an auxiliary metal member are both provided in the sub-pixel region, the auxiliary metal member is provided at a periphery of the solder point, an interval is provided between the solder point and the auxiliary metal member in a plan view of the receiving substrate, and a melting point of the auxiliary metal member is higher than a melting point of the solder point.

Abstract: A method for producing a component and a component are disclosed. In an embodiment a method includes providing a substrate, applying a composite of components to the substrate, forming an anchoring layer on the composite of components, attaching a carrier to the anchoring layer, wherein the anchoring layer is disposed between the substrate and the carrier and removing the substrate, wherein the composite of components is divided into a plurality of components by forming a plurality of separating trenches, wherein, after removing the substrate, the components continue to be held on the carrier by the anchoring layer, and wherein the anchoring layer comprises at least one predetermined breaking layer having at least one predetermined breaking position, the predetermined breaking position being laterally surrounded by the separating trenches and—in a plan view of the carrier—being covered by one of the components.

Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.

Abstract: A crystal of a group 13 nitride has an upper surface and lower surface and is composed of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. When the upper surface of the layer of the crystal of the group 13 nitride is observed by cathode luminescence, the upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. A half value width of reflection at the (0002) plane of a X-ray rocking curve on the upper surface is 3000 seconds or less and 20 seconds or more.

Abstract: An optoelectronic device including: a support; blocks of a semiconductor material, resting on the support and each including a first surface on the side opposite to the support and lateral walls; a nucleation layer on each first surface; a first insulating layer covering each nucleation layer and including an opening exposing a portion of the nucleation layer; a semiconductor element resting on each first insulating layer and in contact with the nucleation layer covered with the first insulating layer in the opening; a shell covering each semiconductor element and including an active layer capable of emitting or absorbing an electromagnetic radiation; and a first conductive layer, reflecting the radiation, extending between the semiconductor elements and extending over at least a portion of the lateral walls of the blocks.

Abstract: The present disclosure relates to a display device and, in particular, a display device using a semiconductor light-emitting device. The display device according to the present disclosure comprises: a substrate having a wiring electrode; a plurality of semiconductor light-emitting elements are electrically connected to the wiring electrode; a plurality of fluorescent substance layers for converting a wavelength of light; a wavelength conversion layer having a plurality of light-emitting elements formed from a plurality of fluorescent substance layers, and a color filter disposed so as to cover the wavelength conversion layer, where at least one of the plurality of fluorescent substance layers has a plurality of layers.

Abstract: A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein a first sub-pixel includes a first conversion element having a green phosphor, wherein a second sub-pixel includes a second conversion element having a red phosphor and wherein a third sub-pixel is free of a conversion element, the third sub-pixel configured to emit blue primary radiation, wherein each sub-pixel has an edge length of at most 100 ?m, and wherein the light-emitting device is configured to enhance a gamut coverage of an emitted radiation.

Abstract: A light emitting device includes a wiring substrate including an n-electrode and a p-electrode wired on a surface of the substrate, a light emitting element including an n-pad electrode joined directly to the n-electrode and a p-pad electrode joined directly to the p-electrode, a first gap between the n-electrode and the p-electrode, with the light emitting element being installed across that first gap, and an underfill, which fills a space between the wiring substrate and the light emitting element. At least one of the n-pad electrode and the p-pad electrode is divided into two islands with a linear shape second gap therebetween. The second gap is continuous with a linear shape third gap between the n-pad electrode and the p-pad electrode.

Abstract: Provided is a display device including a plurality of display modules each including a plurality of inorganic light emitting elements mounted on a mounting surface of a substrate, a light absorbing pattern formed between the plurality of display modules and an encapsulation layer formed on mounting surfaces of the plurality of display modules to cover the mounting surfaces of the plurality of display modules.

Abstract: A method for forming a light-transmissive member includes: a step (A) including locating a cured resin body having a principal surface and containing a silicone resin, and a die including a plurality of convex portions, such that the principal surface and the plurality of convex portions face each other, and pressing the die onto the principal surface of the resin body in a heated state to form a plurality of concave portions at the principal surface; and a step (B) including, after the step (A), irradiating the principal surface of the resin body with ultraviolet rays.

Abstract: A light-emitting device is provided. The light-emitting device includes a first substrate. The light-emitting device also includes a second substrate including a light-shielding structure. The light-emitting device further includes a first light-emitting module and a second light-emitting module being adjacent to each other. The first light-emitting module and the second light-emitting module are disposed between the first substrate and the second substrate. The first light-emitting module and the second light-emitting module are spaced apart by a gap, and the light-shielding structure at least partially covers the gap in a top view direction of the light-emitting device.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.

Abstract: A thermoelectric conversion element includes a thermoelectric member that is columnar and an insulator formed around the thermoelectric member. Particles are enclosed between the thermoelectric member and the insulator.

Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A layered body includes: a polymer film (A), the polymer film (A) including an organic piezoelectric material having a weight average molecular weight of from 50,000 to 1,000,000, having a standardized molecular orientation MORc at a reference thickness of 50 ?m of from 1.0 to 15.0 as measured by a microwave transmission molecular orientation analyzer, having a degree of crystallinity of from 20% to 80% as measured by a DSC method, and having an internal haze of 50% or less with respect to visible light; and a peelable protective film (B) that contacts one main face of the polymer film (A). The maximum indentation depth h max on a face of the protective film (B) that contacts the polymer film (A) is from 53 nm to 100 nm as measured by a nanoindentation method.

Abstract: The present disclosure provides an ultrasonic transducer and a method for manufacturing an ultrasonic transducer, a display substrate and a method for manufacturing a display substrate. The method for manufacturing the ultrasonic transducer includes: forming a via hole in a substrate; forming a structural layer on a side of the substrate, the structural layer cover the via hole; and etching the structural layer from a side of the substrate away from the structural layer by using the substrate formed with the via hole as a blocking layer, to form a cavity at a position of the structural layer corresponding to that of the via hole.

Abstract: A piezoelectric MEMS microphone comprising a multi-layer sensor that includes at least one piezoelectric layer between two electrode layers, with the sensor being dimensioned such that it provides a near maximized ratio of output energy to sensor area, as determined by an optimization parameter that accounts for input pressure, bandwidth, and characteristics of the piezoelectric and electrode materials. The sensor can be formed from single or stacked cantilevered beams separated from each other by a small gap, or can be a stress-relieved diaphragm that is formed by deposition onto a silicon substrate, with the diaphragm then being stress relieved by substantial detachment of the diaphragm from the substrate, and then followed by reattachment of the now stress relieved diaphragm.

Abstract: A helical dielectric elastomer actuator (HDEA) can include a first dielectric region comprising an elastomer defining a helix. In an example, a dielectric material can be deposited and a compliant conductive material can be deposited, such as using an additive manufacturing approach, to provide an HDEA. In an example where the HDEA has multiple mechanical degrees of freedom, at least two compliant conductive regions can be located on a first surface of the first dielectric region and at least one compliant conductive region can be located on an opposite second surface of the first dielectric region. For such an example, the at least two compliant conductive regions can be arranged to be energized with respect to the at least one compliant conductive region in a manner providing at least two mechanical degrees of freedom for operation of the HDEA.

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.