Abstract: A method and system of estimating human perception of audibility of audio alerts in the presence of background noise. In the audibility estimation system, a microphone generates an input signal corresponding to an audio alert. A processor receives the input signal and generates an audibility metric representing human perception of audibility of the audio alert based on a comparison between a background noise estimate and an audio alert estimate, and causes an action to be taken based on the audibility metric.

Abstract: A method of echo cancellation in hands-free communication is disclosed. The method includes: receiving, via a receive signal processor, a far-end audio signal; providing the far-end audio signal to: an acoustic echo canceller module as a reference signal, and at least one loudspeaker for playback; determining an external gain value associated with the far-end audio signal, the external gain applied to the far-end audio signal downstream of the receive signal processor and prior to playback from the at least one loudspeaker; adjusting at least one parameter of the acoustic echo canceller module based on the external gain value; receiving playback output of the far-end audio signal from the at least one loudspeaker as an input signal to a microphone; and processing the microphone input signal by the adjusted acoustic echo canceller module to produce an echo-cancelled signal.

Abstract: An apparatus or method to allow a user to control an audio processing operation of an internal and/or external microphone(s). The method includes providing a configurable user interface which defines an audio processing operation. The status of the audio processing operation can be defined through interaction with the user interface. Capture of sound with the microphone(s) may be controlled based on the status of the audio processing operation.

Abstract: A method and an apparatus for voice activity detection provided in embodiments of the present disclosure allow for dividing a to-be-detected audio file into frames to obtain a first sequence of audio frames, extracting an acoustic features of each audio frame in the first sequence of audio frames, and then inputting the acoustic feature of each audio frame to a noise-added VAD model in chronological order to obtain a probability value of each audio frame in the first sequence of audio frames; and then determining, by an electronic device, a start and an end of the voice signal according to the probability value of each audio frame. During the VAD detection, the start and the end of a voice signal in an audio are recognized with a noise-added VAD model to realize the purpose of accurately recognizing the start and the end of the voice signal.

Abstract: The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The magnetic recording head comprises a first write head, a second write head, at least one read head, and a thermal fly height control element. The first write head is a wide writing write head comprising a first main pole and a first trailing shield. The second write head a narrow writing write head comprising a second main pole, a trailing gap, a second trailing shield, and one or more side shields. The first main pole has a shorter height and a greater width than the second main pole. The second main pole has a curved or U-shaped surface disposed adjacent to the trailing gap. The thermal fly height control element and the at least one read head are aligned with a center axis of the second main pole of the second write head.

Abstract: A heat-assisted magnetic recording device includes a write pole positionable adjacent a magnetic recording medium and configured to write data to the medium. A near-field transducer is situated proximate the write pole and configured to produce a thermal spot on the medium. A channel circuit is configured to generate a sequence of symbols having a length of nT, where T is a channel clock rate and n is an integer over a predetermined range. A write driver is configured to apply bi-directional write currents to the write pole to record the sequence of symbols at a location of the thermal spot on the medium, wherein a duration of applying the write currents to the write pole by the write driver is dependent on a length of the sequence of symbols and the effective thermal spot size.

Abstract: An apparatus comprises a write pole for writing data to a magnetic recording medium and a near-field transducer (NFT) optically coupled to a laser source and configured to produce a thermal spot on the medium. A laser driver applies laser operation power (Iop) to the laser source. A channel circuit generates symbols having a length of nT, where T is a channel clock rate and n is an integer. The laser driver applies Iop to the laser source and a write driver applies bi-directional write currents to the write pole to record the symbols at a location of the thermal spot on the medium, wherein a duration of applying Iop to the laser source by the laser driver is dependent on a length of the symbols and the effective thermal spot size.

Abstract: Certain embodiments are directed to a spin torque oscillator (STO) device in a microwave assisted magnetic recording (MAMR) device. The magnetic recording head includes a seed layer, a spin polarization layer over the seed layer, a spacer layer over the spin polarization layer, and a field generation layer is over the spacer layer. In one embodiment, the seed layer comprises a tantalum alloy layer. In another embodiment, the seed layer comprises a template layer and a damping reduction layer over the template layer. In yet another embodiment, the seed layer comprises a texture reset layer, a template layer on the texture reset layer, and a damping reduction layer on the template layer.

Abstract: A heat-assisted magnetic recording (HAMR) write head has a write pole with a chemically-passivated end that substantially prevents oxidation and thus improves corrosion resistance of the write pole. The write pole and near-field transducer (NFT) are supported on a slider and have their ends in a window region of the slider's disk-facing surface. The outer surface region of the write pole is chemically-passivated, preferably by exposure to a nitrogen plasma. The nitrogen plasma has no effect on the NFT end or on the magnetoresistive read head, which is protected because it is located in a non-window region of the slider's disk-facing surface. An optically transparent protective film is formed in the window over the passivated write pole end and NFT end.

Abstract: Aspects of the present disclosure generally relate to magnetic recording heads of magnetic recording devices. A magnetic read head includes a first pinning layer magnetically oriented in a first direction, and a second pinning layer formed above the first pinning layer and magnetically oriented in a second direction that is opposite of the first direction. The magnetic read head includes a rear hard bias disposed outwardly of one or more of the first pinning layer relative or the second pinning layer. The rear hard bias is magnetically oriented to generate a magnetic field in a bias direction. The bias direction points in the same direction as the first direction or the second direction. The magnetic read head does not include an antiferromagnetic (AFM) layer between a lower shield and an upper shield.

Abstract: Devices that include a near field transducer (NFT), the NFT having at least one external surface; and at least one adhesion layer positioned on at least a portion of the at least one external surface, the adhesion layer including oxides of yttrium, oxides of scandium, oxides of lanthanoids, oxides of actionoids, oxides of zinc, or combinations thereof.

Abstract: A light source-unit includes a laser diode, a sub-mount which the laser diode is joined. The laser diode includes an optical generating layer including an active layer which emits laser-light and cladding layers being formed so as to sandwich the active layer. The active layer includes a quantum dot layer including a plurality of quantum dots, which respectively confine movements of carriers in the three-dimensional directions.

Abstract: According to one embodiment, a magnetic disk device includes a disk including a recording region including a servo sector, a head configured to write data to the disk and read data from the disk, and a controller configured to acquire a plurality of correction data for a repeatable runout of the recording region, the correction data respectively corresponding to a plurality of measurement positions set based on a first linearity error acquired by reading the servo sector, and to correct a position of the head based on the correction data.

Abstract: According to one embodiment, a servo write method includes a head and a disk having a plurality of spiral servo patterns which are written radially in a first direction from a first area to a second area other than the first area at velocity that varies between the first area and the second area, the method including moving the head in a second direction opposite to the first direction to read each of the spiral servo patterns, measuring a plurality of time intervals at which each of the spiral servo patterns is read in the first area, and writing a plurality of servo patterns to the first area based on the time intervals.

Abstract: The magnetic tape includes a non-magnetic support and a magnetic layer, in which an edge shape of the timing-based servo pattern, specified by magnetic force microscopy is a shape in which a difference between a value L99.9 of a cumulative distribution function of 99.9% and a value L0.1 of a cumulative distribution function of 0.1% in a position deviation width from an ideal shape of the magnetic tape in a longitudinal direction is 180 nm or less, and in which a difference between a spacing Safter measured on a surface of the magnetic layer by an optical interferometry after ethanol cleaning and a spacing Sbefore measured on the surface of the magnetic layer by an optical interferometry before ethanol cleaning is greater than 0 nm and 6.0 nm or less.

Abstract: A problem to be solved by the present invention is to provide a magnetic recording medium having a jet-black magnetic stripe which is not tinged with red. The present invention is directed to a magnetic recording medium including: a magnetic recording layer on a substrate; and a protective layer (a) on the magnetic recording layer, wherein the protective layer (a) contains an aniline coloring material. The magnetic recording medium is advantageous in that the magnetic stripe is jet-black and has excellent design properties, and therefore can be widely used for credit cards, bank cards and the like.

Abstract: A computer-implemented method includes identifying a lower calibration target of a column of an automated tape library and identifying an upper calibration target of the column. The method includes calculating at least one slot position between the upper calibration target and the lower calibration target. For at least some of the calculated slot positions, the method includes performing a check including identifying an actual slot position corresponding to the calculated slot position. The actual slot position is located by a robotic accessor. The method includes comparing the calculated slot position to the corresponding identified actual slot position and determining whether the calculated slot position is within a predefined range of the corresponding identified actual slot position. The method includes outputting a result of the determination.

Abstract: Various embodiments of the invention provide systems and methods for low bandwidth consumption online content editing, where user-created content comprising high definition/quality content is created or modified at an online content editing server according to instructions from an online content editor client, and where a proxy version of the resulting user-created content is provided to online content editor client to facilitate review or further editing of the user-created content from the online content editor client. In some embodiments, the online content editing server utilizes proxy content during creation and modification operations on the user-created content, and replaces such proxy content with corresponding higher definition/quality content, possibly when the user-created content is published for consumption, or when the user has paid for the higher quality content.

Abstract: A system for allowing a user to create a custom track on a user apparatus, the user apparatus having a display is described. A memory stores a plurality of video clips and an audio track having a timeline. An application is stored in the memory. The application is configured to provide, on the display of the user apparatus, a plurality of video source windows, each of the plurality of video source windows corresponding to a respective one of the plurality of video clips. The application is further configured to allow the user to create the custom track while the audio track is playing by correlating portions of the plurality of video clips with the audio track by selecting respective ones of the plurality of video source windows at desired times in the timeline of the audio track.

Abstract: A system and method for embedding versatile graphics in a digital media file. This is performed by a system that contains a processor and a memory coupled thereto where the memory contains spaces therein for data and instructions. Data areas include: an infographic repository; a tables repository; a templates repository; and, a projects and outcomes repository.

Abstract: Described herein are systems, devices and techniques for generating timecode for use in logging and identifying content in a recorded medium, and for use in synchronizing such content when captured and recorded to separate media via separate recording devices. Consistent with some embodiments of the invention, the timecode is generated based on a radio-based time signal that represents a universally accepted time standard (e.g., Coordinated Universal Time), thereby eliminating the need to configure and maintain a master clock distribution scheme as part of a timing synchronization system. Additionally, consistent with some embodiments, the timecode is generated to support any one of multiple framerates.

Abstract: A wearable camera includes an imaging unit; a storage unit configured to store video data imaged by the imaging unit; a sound collection unit disposed on an upper surface of a casing of the wearable camera and configured to collect a sound of a user; and a control unit configured to extract a sound of the user related to an imaging situation included in the video data, and add attribute information to the video data based on the extracted sound.

Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.

Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing startups of bandgap reference circuits in memory systems, e.g., non-volatile memory systems.

Abstract: The present disclosure generally relates to calibrating the communication with a memory device. To ensure proper calibration, interface training (IFT) needs to occur. IFT involves aligning the sampling point, which is an inflection point, of a clock signal with a data signal. The sampling point of the clock (i.e., the clock edge) needs to be located within the valid window of the data signal. The valid window of the data signal is the time in which the signal is guaranteed to be stable, i.e., after the signal has finished the signal transition time. If the sampling point is aligned with the inflection point of the data signal, then the data signal is not properly aligned. If the sampling point is aligned with the rising or falling edge of the data signal, the data may be obtained, but the data signal is misaligned and is dangerously close to being unreadable.

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

Abstract: An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: According to one embodiment, a magnetic device includes a magnetic tunnel junction element, the magnetic tunnel junction element comprising: a first structure having ferromagnetism; a second structure having ferromagnetism; and a first nonmagnet provided between the first structure and the second structure; wherein: the first structure and the second structure are antiferromagnetically coupled via the first nonmagnet; and the first structure includes a first ferromagnetic nitride.

Abstract: Embodiments of a Stochastic memristive array (SMA) device based on arrays of voltage-controlled magnetic tunnel junctions (MTJs) are disclosed. The SMA device is based on an array of stochastic (low energy barrier) magnetic tunnel junctions that are connected in parallel which simultaneously exhibits features that include (i) stochasticity and (ii) memristive behavior. The energy barrier of the MJTs may be tuned by an applied voltage (electric field). SMA devices may find applications in emerging computing concepts such as probabilistic computing and memcomputing, among others, providing a pathway towards intelligent hybrid CMOS-spintronic systems.

Abstract: The disclosure provides a voltage-controlled magnetic anisotropic magnetic random access memory. The memory comprises a virtual array, a memory array and a peripheral circuit, wherein the memory array comprises memory cells with X rows and Y columns; the virtual array comprises virtual cells with X rows and one column; the peripheral circuit comprises at least one data sampling-decision-output circuit, the data sampling-decision-output circuit comprises a sensitive amplifier circuit and a logic circuit in series, and are simultaneously connected to the data sampling-decision-output circuit in the peripheral circuit at the same time. By changing the width-length ratio of a differential circuit in the sensitive amplifier circuit and adding the virtual array, the problem that the storage state of the voltage-controlled magnetic anisotropy magnetic random access memory cannot be determined is effectively solved, and the risk of resistance deviation under different process conditions also can be avoided.

Abstract: According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

Abstract: A memory system includes a voltage generator disposed in a high temperature region, and suitable for generating a first voltage; a memory disposed in a low temperature region, and suitable for using a second voltage; and a voltage converter disposed between the high temperature region and the low temperature region, suitable for converting the first voltage into the second voltage, and including a core made from a material having lower heat conductivity than a metal.

Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.

Abstract: A semiconductor memory device includes a plurality of memory cells connected a pair of bit lines, a column selection circuit, and a sense amplifier. When the semiconductor memory device is in a data writing operation, the column selection circuit electrically connects a pair of data input and output lines to the pair of bit lines during a first time interval and a second time interval, consecutively arranged, and the sense amplifier electrically disconnects from the pair of bit lines during the first time interval, and senses and amplifies a voltage difference between the pair of bit lines during the second time interval.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: Provided herein are a nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of word lines having a first word line and a plurality of memory cells connected to the first word line. The plurality of memory cells includes a plurality of monitoring cells and a plurality of data cells each data cell configured to store N-bit data, N being a natural number. The nonvolatile memory device is configured to perform a first program on the plurality of data cells and a detection program different from the first program on the one or more monitoring cells after performing the first program.

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.

Abstract: Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

Abstract: In a channel-stacked memory device which includes a first channel stacked on a second channel, the first channel is programmed in a bottom-to-top direction and the second channel is programmed in a top-to-bottom direction. The electrons in the first channel may be drained by a bit line, while the electrons in the second channel may be drained by a well region.