Abstract: A scalable, distributed load control system for home automation based on a network of microphones may include control devices (e.g., load control devices) that may include microphones for monitoring the system and communicating audio data to a cloud server for processing. The control devices of the load control system may receive a single voice command and may be configured to choose one of the load control devices to transmit the voice command to the cloud server. The load control devices may be configured to receive a voice command, control a connected load according to the voice command if the voice command is a validated command, and transmit the voice command to a voice service in the cloud if the voice command is not a validated command. The voice service to which the load control devices transmit audio data to may be selectable.

Abstract: The present disclosure generally relates to a computer-implemented system for intelligently retaining and recalling memory data. An exemplary method comprises receiving, via a microphone of an electronic device, a speech input of the user; receiving a text input of the user; constructing a first instance of a memory data structure based on the speech input; constructing a second instance of the memory data structure based on the text input; adding the first instance and the second instance of the memory data structure to a memory stack of the user; displaying a user interface for retrieving memory data of the user; receiving, via the user interface, a beginning of a statement from the user; retrieving a particular instance of the memory data structure from the memory stack based on the beginning of the statement; and automatically displaying a completion of the statement.

Abstract: Methods and systems that automatically rank log/event messages and log/event-message transactions to facilitate analysis of log/event-messages generated within distributed-computer systems are disclosed. A base-window dataset and current-window dataset are selected for diagnosis of a particular error or failure and processed to generate a transaction sequence for each dataset corresponding to log/event-message traces identified in the datasets. Then, frequencies of occurrence of log/event-message types relative to transaction types are generated for each dataset. From these two sets of relative frequencies of occurrence, changes in the relative frequency of occurrence for each log/event-message-type/transaction-type pair are generated. Normalized scores for log/event-message-type/transaction-type pairs and scores for transaction types are then generated from the changes in the relative frequency of occurrence.

Abstract: Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation.

Abstract: This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values having multiple precisions, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

Abstract: A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.

Abstract: A method and circuit for performing multi-layer vector-matrix multiplication operations may include, at a first multiplier-accumulator (MAC) layer, converting a digital input vector using one-bit digital to analog converters (DACs); sequentially performing vector-matrix multiplication operations for the analog DAC signals; and sequentially performing an analog-to-digital (ADC) operation on outputs of the vector-matrix multiplication operations to generate binary partial output vectors. At a second MAC layer, the method and circuit may sequentially receive the binary partial output vectors from the first MAC layer at multi-bit DACs; and sequentially perform vector-matrix multiplication operations to generate a summed binary output for the second MAC layer.

Abstract: The disclosure provides a method for multiply-add operations for a neural network. The method includes: determining types of respective pieces of data to be calculated based on a multiply-add operation request; in a condition of the type of each piece of the data to be calculated is a type of single-precision floating point, compressing mantissa of each pieces of the data to be calculated to obtain each compressed mantissa; splitting each compressed mantissa according to a preset rule and determining high digits and low digits of the compressed mantissa; and performing a multiply-add operation on each compressed mantissa based on the high digits and low digits of the compressed mantissa.

Abstract: In an arithmetic processing device, a controller includes: a second non-linear converter that, when a selector has branched off to a second processing side, performs non-linear arithmetic processing on the result of a cumulative addition processing of a first adder; and a second pooling processing part to which the results of the cumulative addition processing of k first adders that have been subject to the non-linear arithmetic processing by the second non-linear converter are inputted, the second pooling processing part performing a pooling process on the simultaneously inputted data. A data-storing memory manager writes the same data to k different data-storing memories when the number of input feature map data is less than or equal to N/k. The controller performs a control so that the selector branches off to the second processing side when the number of input feature map data is less than or equal to N/k.

Abstract: An entropy provider for providing entropy to a computing device external to the entropy provider, the entropy provider comprising a power source and an entropy supply, wherein the power source is adapted to provide power to the entropy supply and wherein the entropy provider comprises a transmitter for transferring the entropy from the entropy supply to an external computing device.

Abstract: The present disclosure pertains to a circuitry for generating random data. The random data can be numbers. The circuitry includes a ring oscillator, a metastable oscillator, a first circuitry, and an analogue circuitry. The ring oscillator has a ring oscillator output frequency selectable through a selectable input of the ring oscillator. The metastable oscillator has a metastable oscillator output frequency selectable through a selectable input of the metastable oscillator. The first circuitry has a ring oscillator chain size selection logic circuit. The analogue circuitry has a capacitor and a switch used for varying frequency of the ring oscillator. The switch is configured to be controlled by the selection logic circuit of the first circuitry.

Abstract: Provided is a random number generator including a single-photon emitter configured to emit single photons by pumping, a waveguide configured to guide the single photons emitted from the single-photon emitter to the inside of the waveguide, the waveguide including a first output terminal and a second output terminal that are respectively provided at both end portions of the waveguide, the single photons being output from the first output terminal and the second output terminal, and a first single-photon detector and a second single-photon detector respectively provided at the first output terminal and the second output terminal and configured to detect the single photons output from the first output terminal and the second output terminal, respectively.

Abstract: Systems, methods, and non-transitory computer readable media are provided for managing pipelines of operations on data. A system may access data and provide a set of functions for the data. The system may receive a user's selection of one or more functions from the set of functions. The system may generate a pipeline of operations for the data based on the user's selection. The pipeline of operations may include the function(s) selected by the user.

Abstract: A report repository may store report results, and a web intelligence report server may include an SDK component to manage sessions, states, security, and resource access and to receive web intelligence data model authoring information, associated with a document, via an authoring API. The web intelligence report server may further include data sources associated with a plurality of data source types and data access associated with a plurality of data layers. A compound database platform of an in-memory database may create a report result via a data flow merge operation that combines multiple data sources into a single data source, based on the web intelligence data model authoring information, the data sources, and the data access. The report result may be stored in the report repository, and the web intelligence data model may be associated with a Web intelligence document as a data Source (“WaaS”) reusable in other documents.

Abstract: Disclosed herein is a software technology for facilitating an interactive conversational session between a user (e.g., a client, a patient, etc.) and a digital conversational character. For instance, in one aspect, the disclosed process may involve two primary phases: (1) an authoring phase that involves a first user accessing a content authoring tool to create a given type of visual conversation application that facilitates interactions between a second user and a digital conversational character in an interactive conversational session, and (2) a rendering phase that involves the second user accessing the created visual conversation application to interact with the digital conversational character in an interactive conversational session.

Abstract: A method for designing a logic flow for a user interface is provided. The method comprises receiving from a first task for an automation process file from a user. The automation process file defines a set of system activities. The first task is added to the automation process file and submitted to a machine learning engine, which determines a number of suggested tasks to be performed after the first task. The suggested tasks are based on frequencies with which previous users have used each task after the first task. The suggested tasks are then presented to the user. A second task is received from the user to be performed after the first task. The second task may be selected from the suggested tasks but not necessarily so. The second task is then added to the automation process file.

Abstract: A disclosed example includes generating a binary translation of a native code section in response to a determination that the binary translation of the native code section is not present in a translation cache; storing the binary translation of the native code section in the translation cache; determining that a stop has occurred during the generation of the binary translation; subsequent to the determination that the stop has occurred, generating a binary translation state map of at least a portion of the binary translation; storing, for at least a portion of a duration of the stop, the binary translation state map in memory; and discarding the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map.

Abstract: Systems, methods, and computer-readable media are disclosed for a systems and methods for improved smart infrastructure data transfer. An example method may involve identifying that a software update is available for a smart infrastructure system. The example method may also involve determining, by a processor of the smart infrastructure system and using a signal strength between a first vehicle and the smart infrastructure system, that the first vehicle is within a threshold range of the smart infrastructure system. The example method may also involve establishing, by the smart infrastructure system, a first ad-hoc peer-to-peer communication link with the first vehicle. The example method may also involve sending, to the vehicle, a request for the software update. The example method may also involve receiving, from the vehicle, at least a first portion of the software update that is transferred using the first ad-hoc peer-to-peer communication link.

Abstract: In an approach, a processor receives input data comprising: (i) a code level for an update, (ii) a scheduled time for the update; (iii) a target system for the update, and (iv) authorization data, where the authorization data: (i) allows for scheduling of the update and (ii) is provided via a channel external from a connection to the target system without an inbound connection. A processor receives a set of data from the target system. A processor, responsive to receiving the set of data from the target system, sends a response packet to the target system that includes the input data. A processor receives, at the scheduled time, a request to process the update. A processor, responsive to the request, sends code for processing the update corresponding to the code level for the update. A processor receives status messages corresponding to progress of the update.

Abstract: Disclosed are an online program update method and device for an optical amplifier. The method comprises: when a program update instruction is sent, a Microcontroller Unit MCU receiving update programs of MCU and a programmable logic device FPGA, storing them in a program memory device, and sending an update instruction to FPGA; FPGA terminating operations of a digital-to-analog converter DAC according to the instruction and a current state remaining unchanged; MCU loading new codes of MCU and FPGA while DAC remains in state of halting refreshing; and after MCU and FPGA run the new codes, reading previously stored data, and starting switching from a previous operation state to enter normal operation state. On basis of conventional optical amplifier control, the invention combines characteristics of MCU and FPGA, and ensures uninterrupted service of optical amplifiers, achieving smooth transition of service, thereby improving stability and reliability of whole optical communications systems.

Abstract: Systems, methods, and computer-readable media are disclosed for smart infrastructure data transfer. An example system is provided with a processor and a memory storing computer-executable instructions that are executed by the processor. The processor sends, over a network, a first software image to a first smart device of a system of smart devices to update a first group of smart devices of the system; and performs a discovery process to identify a second group of smart devices of the system. The second group of smart devices being based on a number or type of smart devices accessible on the system. The processor also creates a second software image including a software update for the second group of smart devices; and sends, over the network, the second software image to the first smart device to update the second group of smart devices.

Abstract: A software upgrade method includes a vehicle-mounted terminal device that obtains upgrade requirement information of a software package and a vehicle status corresponding to the vehicle-mounted terminal device, where the upgrade requirement information indicates a first status or a second status. When the vehicle status is associated with the first status, the vehicle-mounted terminal device starts an upgrade of the software package; or when the vehicle status is associated with the second status, the vehicle-mounted terminal device determines not to start an upgrade of the software package.

Abstract: A function extension system includes a first electronic control device, a second electronic control device, and a server. The first electronic control device includes a user information transmission unit configured to transmit user information to the server. The second electronic control device includes a specification information transmission unit configured to transmit specification information indicative of a specification of the second electronic control device to the server and a download unit configured to, when receiving an application list including at least one piece of application specifying information for specifying an application available to the at least one second electronic control device, download an application program specified by the application specifying information from the server.

Abstract: Techniques for action execution based on management controller received action requests are provided. In one aspect, a utility program running under the control of an operating system on a server computer may retrieve an indication of an action request. The action request may be stored in a management controller accessible storage. Storage of the action request may not require operating system administrator credentials. The action specified in the request may be executed by the utility program.

Abstract: A method of generating an output differential firmware update. Differential firmware update characteristic data is sent from a trusted execution environment (TEE) to an authorizing entity. The differential firmware update characteristic data indicates at least one characteristic associated with generation of the output differential firmware update within the TEE. The TEE obtains a key from the authorizing entity, and is thereby authorized by the authorizing entity to generate the output differential firmware update. The TEE obtains an encrypted version of a firmware portion of the firmware. The encrypted version of the firmware portion is decrypted using the key to obtain a decrypted version of the firmware portion. The output differential firmware update is generated using the decrypted version of the firmware portion.

Abstract: To generate code for a system, in a first step, configuration information for the system is retrieved, which describes a system management scheme. Based on this configuration information, code is generated for managers of the system, the code comprising a system management library for each manager, which contains interfaces required by the manager for sending and receiving messages. In addition, code for software platforms of the system is generated, the code comprising a system management router for each software platform, which enables an exchange of messages between managers. Optionally, system management tests may be generated for the system management libraries or the system management routers.

Abstract: A management method for managing compatibility between a first piece of equipment and a second piece of equipment connected together by communication interfaces. The method comprises the following steps: the first piece of equipment sending first compatibility information to the second piece of equipment, which first compatibility information is representative of the first data formats; the second piece of equipment preparing second compatibility information identifying at least one of the first formats that corresponds to the second format; and the second piece of equipment determining a level of compatibility with the first piece of equipment from the second compatibility information. A system for implementing the method.

Abstract: The present disclosure provides a management method for software versions to improve transaction safety of software. In the management method, among management apparatuses, a first token management apparatus obtains request information indicating a requested version requested by a user, and first transaction data indicating that the user provides predetermined number of tokens to a software developer who has developed the requested version is stored in distributed ledgers through execution of a consensus algorithm by the management apparatuses.

Abstract: One embodiment of the invention provides a method for automated code annotation in machine learning (ML) and data science. The method comprises receiving, as input, a section of executable code. The method further comprises classifying, via a ML model, the section of executable code with a stage classification label indicative of a stage within a workflow for automated ML that the executable code applies to. The method further comprises categorizing, based on the stage classification label, the section of executable code with a category of annotation that is most appropriate for the section of executable code. The method further comprises generating a suggested annotation for the section of executable code based on the category of annotation. The method further comprises providing, as output, the suggested annotation to a display of an electronic device for user review. The suggested annotation is user interactable via the electronic device.

Abstract: Apparatuses and methods of controlling scheduling of displays presented in response to data indicative of user inputs from user terminals in a computerised system are disclosed. A performance metric is determined for a response by a data processing apparatus configured to respond to user terminals, the response being provided in accordance with a strategy of scheduling displays when responding to data indicative of at least one user input. A response performance score is computed based on the determined performance metric and a reference metric representative of a preferred result when responding data indicative of user inputs. It can then be determined, based on the response performance score, whether the strategy of scheduling displays when responding data indicative of user inputs needs a change.

Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.

Abstract: A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline.

Abstract: Examples include techniques four use of a large scale multi-literal matching algorithm. Implementation of the large scale multi-literal matching algorithm includes processing a chunk of input data via performance of a SHIFT-OR operation using the chunk of input data to identify a match candidate for a target literal character pattern. A single input multiple data (SIMD) instruction may be utilized by a processor to perform the SHIFT-OR operation as a parallel table lookup of rows of SHIFT-OR mask table for the chunk of input data to facilitate identification of the match candidate.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

Abstract: This application discloses example synchronization instruction insertion methods and example apparatuses. One example method includes obtaining a first program block comprising one or more statements, where each of the one or more statements includes one or more function instructions. A first function instruction and a second function instruction between which data dependency exists in the first program block can then be determined. A synchronization instruction pair between a first statement including the first function instruction and a second statement including the second function instruction can then be inserted.

Abstract: A microprocessor that includes a plurality of instruction sets and has a reduced code size is provided. A microprocessor includes a plurality of instruction sets and executes a program while switching instruction sets on the basis of an instruction set switching bit that is included in an instruction code having been read in and represents an instruction set that should be executed next at the time of execution of the program. Each instruction set includes a set of collected instruction codes that are to be used when each intermediate language instruction that is classified in accordance with a process content is executed. Then, for each instruction set, instruction sets that are possible to be selected and should be executed next are limited in an instruction code.

Abstract: The present disclosure relates to computer-implemented methods, software, and systems for dynamic rate limiting of execution of operation. A request from a user account for execution of an operation by an application service is. A total number of operations registered at an operations registry is determined. In response to determining that all of registered operations exceeds a first threshold value, a number of registered operations associated with a group account of the user account is determined. If it is determined that (i) the total number of registered operations exceeds a first threshold value and that the number of registered operations associated with the group account does not exceed a second threshold value or (ii) if it is determined that the total number of registered operations does not exceed the first threshold value, the operation is registered at the operations registry. An instruction to execute the registered operation is sent.

Abstract: A memory architecture includes processing circuits co-located with memory subarrays for performing computations within the memory architecture. The memory architecture includes a plurality of decoders in hierarchical levels that include a multicast capability for distributing data or compute operations to individual subarrays. The multicast may be configurable with respect to individual fan-outs at each hierarchical level. A computation workflow may be organized into a compute supertile representing one or more “supertiles” of input data to be processed in the compute supertile. The individual data tiles of the input data supertile may be used by multiple compute tiles executed by the processing circuits of the subarrays, and the data tiles multicast to the respective processing circuits for efficient data loading and parallel computation.

Abstract: Disclosed herein is a highly energy-efficient architecture targeting the ultra-low-power sensor domain. The architecture achieves high energy-efficiency while maintaining programmability and generality. The invention introduces vector-dataflow execution, allowing the exploitation of the dataflows in a sequence of vector instructions and to amortize instruction fetch and decode over a whole vector of operations. The vector-dataflow architecture allows the invention to avoid costly vector register file accesses, thereby saving energy.

Abstract: Restoring speculative history used for making speculative predictions for instructions processed in a processor. The processor can be configured to speculatively predict an outcome of a condition or predicate of a conditional control instruction before its condition is fully evaluated in execution. Predictions are made by the processor based on a history that is updated based on outcomes of past predictions. If a conditional control instruction is mispredicted in execution, the processor can perform a misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline back to the mispredicted conditional control instruction, and then re-fetching instructions in the correct instruction flow path for execution.

Abstract: Apparatus and method for correcting quantum bit states. For example, one embodiment of an apparatus comprises: a phase error evaluator to evaluate a quantum instruction sequence of a quantum program to determine accumulated phase error; phase correction hardware logic to insert one or more phase correction instructions into the quantum instruction sequence to generate a modified quantum instruction sequence to correct the accumulated phase error; and wherein the modified quantum instruction sequence or a translated version thereof is to be executed by a qubit controller chip.

Abstract: Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.

Abstract: The present subject matter relates to techniques for storing POST codes in electronic tags. In an example, a POST code corresponding to each test of a Power ON Self-Test (POST) process may be stored in a Complementary Metal-Oxide Semiconductor (CMOS) chip of a motherboard. The POST code may be indicative of a status of a respective test of the POST process. The POST code corresponding to each test of the POST process is simultaneously stored in a memory of an electronic tag. The electronic tag may be communicatively coupled to the motherboard and the CMOS chip. The POST codes are retrievable from the memory of the electronic tag by an end user of the computing device when the motherboard is powered OFF.

Abstract: A System Control Processor (SCP) cloning system includes a first computing system coupled to second computing systems via a network. The first computing system includes a first SCP subsystem coupled to a central processing system and first computing system components in the first computing system. The first SCP subsystem receives a first cloning command via the network from a management system and, based on the first cloning command, retrieves respective first SCP component state information from each of a plurality of first SCP components that are included in the first SCP subsystem, uses the respective first SCP component state information to generate a first SCP subsystem image that is configured for installation on an SCP subsystem to configure that SCP subsystem the same as the first SCP subsystem, and transmits the first SCP subsystem image to a second SCP subsystem in each of at least one second computing system.

Abstract: A method for iteratively autotuning a high-performance computing system that depends on a set of parameters. Performance is first evaluated two or more times with the current values of the parameters. Afterward at least two evaluations, the median performance is evaluated. The median is then tested against a rule based on a filtering threshold. If the median does not the rule, the current values of the parameters are discarded, and the method is restarted with at least one other value generated by an optimization module; otherwise, a resampling method is performed based on the median and on a confidence interval that decreases with the number of steps of the optimization method.

Abstract: An electronic device (such as an access point) that selectively changes to an alternative or different partition is described. During operation, when the electronic device is in a first power state (such as a lower power state), an integrated circuit in the electronic device may detect or receive an error state or a change instruction. In response, the integrated circuit may change an active partition in the electronic device from a first partition to a second partition. Next, the integrated circuit may transition the electronic device to a second power state (such as a higher power state). Furthermore, a processor in the electronic device (which may be the same as or different from the integrated circuit) may install and execute an operating system of the electronic device in the second partition.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple addresses of a volatile memory medium VMM of an information handling system (IHS); for each IHS initialization executable/OS executable pair of multiple IHS initialization executable/OS executable pairs: retrieve, from a first non-volatile memory medium (NVMM), an IHS initialization executable of the IHS initialization executable/OS executable pair; copy, by the IHS initialization executable, an OS executable of the IHS initialization executable/OS executable pair from the first NVMM to the VMM; call, by the IHS initialization executable, the subroutine; store, by the subroutine, an address associated with the OS executable via a data structure stored by the VMM; and copy, by a first OS executable, the OS executable from the VMM to a second NVMM based at least on the address associated with the OS executable.

Abstract: In one aspect, a first device may include at least one processor and storage accessible to the at least one processor. The storage may include instructions executable by the at least one processor to load a driver responsive to a boot command, where the driver may be loaded prior to the first device loading a guest operating system (GOS) stored at the first device. The instructions may then be executable to use the driver to communicate with a second device to receive a disk image over a wired connection to the second device. The instructions may be further executable to continue booting the first device using the disk image rather than the GOS and to, responsive to the first device being booted using the disk image, communicate with the second device over the wired connection to diagnose one or more issues with the first device.

Abstract: Techniques are provided for path management and failure prediction in a multipath environment using target port power levels. One method comprises obtaining, by a first entity that communicates with a second entity via multiple paths, a transmit power level and/or a receive power level of a target port associated with the second entity; evaluating the transmit power level and/or the receive power level of the target port relative to a threshold; and setting, by the first entity, a path state of one or more paths between the first entity and the target port to a standby state based on the evaluating, wherein the first entity establishes paths between the first entity and one or more other target ports of the second entity in an active state. Existing communications on the one or more paths between the first entity and the target port may be allowed to complete in the standby state.