Abstract: Methods for activating a p-type dopant in a group III-Nitride semiconductor are provided. In embodiments, such a method comprises annealing, in situ, a film of a group III-Nitride semiconductor comprising a p-type dopant formed via metalorganic chemical vapor deposition (MOCVD) at a first temperature for a first period of time under an atmosphere comprising NH3 and N2; and cooling, in situ, the film of the group III-Nitride semiconductor to a second temperature that is lower than the first temperature under an atmosphere comprising N2 in the absence of NH3, to form an activated p-type group III-Nitride semiconductor film.

Abstract: A semiconductor review tool receives absolute Z-height values for the semiconductor wafer, such as a semiconductor wafer with a beveled edge. The absolute Z-height values can be determined by a semiconductor inspection tool. The semiconductor review tool reviews the semiconductor wafer within a Z-height based on the absolute Z-height values. Focus can be adjusted to within the Z-height.

Abstract: A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.

Abstract: A substrate cleaning method according to an aspect of the present disclosure includes: supplying a film-forming treatment liquid containing a volatile component to a substrate to form a film on the substrate; supplying a peeling treatment liquid, which peels off a treatment film from the substrate, to the treatment film formed by solidifying or curing the film-forming treatment liquid on the substrate due to volatilization of the volatile component; and supplying a hydrophobic liquid, which hydrophobizes the substrate, to the substrate to which the peeling treatment liquid has been supplied.

Abstract: A substrate processing method includes forming, by supplying a chemical liquid onto a central portion of a substrate while rotating a rotary table at a first speed, a liquid film of the chemical liquid having a first thickness; forming, by supplying the chemical liquid onto the central portion while rotating the rotary table at a second speed lower than the first speed after the forming of the liquid film having the first thickness, a liquid film of the chemical liquid having a second thickness larger than the first thickness; and heating, by heating the rotary table in a state that the rotary table is rotated at a third speed lower than the second speed or in a state that the rotating of the rotary table is stopped after the forming of the liquid film having the second thickness, the substrate and the liquid film of the chemical liquid.

Abstract: An etching method enables plasma etching of a silicon-containing film with reduced lateral etching. The etching method includes providing a substrate in a chamber included in a plasma processing apparatus. The substrate includes a silicon-containing film. The etching method further includes setting a flow rate proportion of a phosphorus-containing gas with respect to a total flow rate of the process gas so as to establish a predetermined ratio of an etching rate of an alternate stack of a silicon oxide film and a silicon nitride film to an etching rate of the silicon oxide film.

Abstract: A substrate liquid processing apparatus includes a processing tub configured to store a processing liquid therein; a processing liquid supply configured to supply the processing liquid into the processing tub; a processing liquid drain device configured to drain the processing liquid from the processing tub; and a controller configured to control the processing liquid supply and the processing liquid drain device. The controller calculates, in response to an instruction to change a concentration of a preset component of the processing liquid stored in the processing tub, a drain amount and a feed amount of the processing liquid from/into the processing tub based on information upon a current concentration of the preset component, information upon a concentration increment thereof per unit time and information upon the changed concentration thereof, and controls the processing liquid supply and the processing liquid drain device based on the calculation result.

Abstract: A semiconductor processing system comprises a first, a second, and a third process module assembly. The third process module assembly is between the first and the second process module assemblies, and includes an opening for providing substrates to be processed in the various process module assemblies. The process modules are arranged laterally relative to the opening. The first and second process module assemblies each include an associated transfer chamber, an associated substrate transfer device, and a plurality of associated process modules attached the associated transfer chamber. The third process module assembly may include an associated transfer chamber, an associated substrate transfer device, and a single associated process module attached to the associated transfer chamber.

Abstract: A device may detect a semiconductor wafer to be transferred from a source wafer carrier to a target wafer carrier, and may cause a light source to illuminate the semiconductor wafer. The device may cause a camera to capture images of the semiconductor wafer after the light source illuminates the semiconductor wafer, and may perform image recognition of the images of the semiconductor wafer to determine whether an edge of the semiconductor wafer is damaged. The device may cause the semiconductor wafer to be provided to the source wafer carrier when the edge of the semiconductor wafer is determined to be damaged, and may cause the semiconductor wafer to be provided to the target wafer carrier when the edge of the semiconductor wafer is determined to be undamaged.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: A pedestal assembly for a processing region and comprising first pins coupled to a substrate support, configured to mate with first terminals of an electrostatic chuck, and are configured to be coupled to a first power source. Each of the first pins comprises an interface element, and a compliance element supporting the interface element. Second pins are coupled to the substrate support, configured to mate with second terminals of the electrostatic chuck, and configured to couple to a second power source. Alignment elements are coupled to the substrate support and are configured to interface with centering elements of the electrostatic chuck. The flexible element is coupled to the substrate support, configured to interface with a passageway of the electrostatic chuck, and configured to be coupled to a gas source.

Abstract: Herein disclosed are a micro-component transfer head, a micro-component transfer device, and a micro-component display. Said micro-component transfer head comprises a carrying surface that corresponds to a micro-component extraction area. Said extraction area conforms with a first geometric object, which comprises at least an acute angle. A second geometric object comprises at least a right angle and is constituted of n copies of the first geometric object, n being an integer greater than 1. The shape of the first geometric object differs from that of the second.

Abstract: A micro pick-up array used to pick up a micro device is provided. The micro pick-up array includes a substrate, a pick-up structure, and a soft polymer layer. The pick-up structure is located on the substrate. The pick-up structure includes a cured photo sensitive material. The soft polymer layer covers the pick-up structure. A manufacturing method of a micro pick-up array is also provided.

Abstract: An electrostatic chuck heater includes a ceramic plate, an electrostatic electrode, first and second zone heater electrodes, and first and second zone gas grooves. The ceramic plate includes, on its surface, a wafer placement surface. The electrostatic electrode is embedded in the ceramic plate. The first and second zone heater electrodes are embedded in the ceramic plate, corresponding to respective multiple heater zones into which the wafer placement surface is divided, and allow electric power to be individually supplied to the heater zones. Zone gas grooves are provided corresponding to respective multiple gas supply zones into which the wafer placement surface is divided independently of the heater zones, and allow a gas to be individually supplied to the gas supply zones.

Abstract: A substrate processing apparatus including an electrostatic chuck on which a substrate is mountable; a ring surrounding the electrostatic chuck, the ring including a first coupling groove; and a first floating electrode in the first coupling groove of the ring, the first floating electrode having a ring shape, wherein a top surface of the first floating electrode is exposed at the ring, and the first floating electrode has a tapered shape including an inclined surface that is inclined in a downward direction toward the electrostatic chuck.

Abstract: A substrate processing apparatus includes: a disk including a plurality of electrostatic chucks periodically disposed at a constant radius from a central axis; a disk support supporting the disk; a DC line electrically connected to the plurality of electrostatic chucks through the disk support; and a power supply configured to supply power to the DC line. The DC line includes: a first DC line penetrating through the disk support from the power supply; a power distribution unit configured to distribute the first DC line to connect the first DC line to each of the plurality of electrostatic chucks; and a plurality of second DC lines respectively connected to the plurality of electrostatic chucks in the power distribution unit.

Abstract: A processing method of a wafer includes a modified layer forming step of positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the wafer to the inside of a planned dividing line and executing irradiation along the planned dividing line to form modified layers inside and a water-soluble resin coating step of coating the front surface of the wafer with a water-soluble resin before or after the modified layer forming step. The processing method also includes a dividing step of expanding a dicing tape to divide the wafer into individual device chips together with the water-soluble resin with which the front surface of the wafer is coated and a modified layer removal step of executing plasma etching and removing the modified layers that remain at the side surfaces of the device chips in a state in which the dicing tape is expanded and the front surfaces of the individual device chips are coated with the water-soluble resin.

Abstract: Provided is a substrate holding device that inhibits drop in holding accuracy of a substrate. A Bernoulli chucking pad suctions and holds a front surface or a back surface of a substrate S. A position determiner 54 is capable of pushing the substrate S in contact with a side surface 82 of the substrate S, and positioning the suctioned substrate S. A pin 66 enables the position determiner 54 to come in contact with the side surface 82 of the substrate S. The pin 66 brings the position determiner 54 into contact with the side surface 82 of the substrate S, and the position determiner 54 thereby positions the substrate S.

Abstract: Provided are a die pickup module and a die bonding apparatus including the same. The die pickup module includes a wafer stage for supporting a wafer including dies attached on a dicing tape, a die ejector arranged under the dicing tape and for separating a die to be picked up from the dicing tape, a non-contact picker for picking up the die in a non-contact manner so as not to contact a front surface of the die, a vacuum gripper for partially vacuum adsorbing a rear surface of the die picked up by the non-contact picker and an inverting driving unit for inverting the vacuum gripper to invert the die so that a rear surface of the die gripped by the vacuum gripper faces upward.

Abstract: A die ejection apparatus operable to eject a die from a support has at least two ejector components configured to lift a die located on the support. The ejector components are moveable to a position in which a lifting force is exertable by the ejector components on the support, so as to lift a die located on the support. Movement of the die ejector components is initiated towards the support, and a moment when each of the die ejector components reaches the position is determined. A height offset of each die ejector component relative to a height of another die ejector component is determined upon reaching the said position, and relative heights of the die ejector components are adjusted in dependence upon the evaluated height offset.

Abstract: In an embodiment, a system includes: a gas distributor assembly configured to dispense gas into a chamber; and a chuck assembly configured to secure a wafer within the chamber, wherein at least one of the gas distributor assembly and the chuck assembly includes: a first portion comprising a convex protrusion, and a second portion comprising a concave opening, wherein the convex protrusion is configured to engage the concave opening.

Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

Abstract: A method of forming vias and skip vias is provided. The method includes forming a blocking layer on an underlying layer, and forming an overlying layer on the blocking layer. The method further includes opening a hole in the overlying layer that overlaps the blocking layer, and etching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer

Abstract: A lift-off method includes a dividing step of dividing a buffer layer and an optical device layer stacked on a front side of a substrate to thereby form separate buffer layers and separate optical device layers, a transfer member bonding step of bonding a transfer member to a front side of the separate optical device layers, a buffer layer breaking step of applying a pulsed laser beam to the separate buffer layers to thereby break the separate buffer layers, and an optical device layer transferring step of transferring the separate optical device layers from the substrate to the transfer member. An energy density of each pulse of the pulsed laser beam is set to 1.0 to 5.0 mJ/mm2.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a stack over a substrate. The stack includes alternating first semiconductor layers and second semiconductor layers. The method also includes forming a polishing stop layer over the stack and a dummy layer over the polishing stop layer, recessing the dummy layer, the polishing stop layer and the stack to form a recess, forming a third semiconductor layer to fill the recess, and planarizing the dummy layer and the third semiconductor layer until the polishing stop layer is exposed. The method also includes patterning the polishing stop layer and the stack into a first fin structure and the third semiconductor layer into a second fin structure, removing the second semiconductor layers of the first fin structure to form nanostructures, and forming a gate stack across the first fin structure and the second fin structure.

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of semiconductor nanosheets, a plurality of source/drain (S/D) features and a gate stack. The semiconductor substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin, and a top surface of the first fin is lower than a top surface of the second fin. The plurality of semiconductor nanosheets are disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of semiconductor nanosheets. The gate stack wraps each of the plurality of semiconductor nanosheets.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 ?m to 13 ?m.

Abstract: A method includes providing semiconductor channel layers over a substrate; forming a first dipole layer wrapping around the semiconductor channel layers; forming an interfacial dielectric layer wrapping around the first dipole layer; forming a high-k dielectric layer wrapping around the interfacial dielectric layer; forming a second dipole layer wrapping around the high-k dielectric layer; performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer; removing the second dipole layer; and forming a work function metal layer wrapping around the high-k dielectric layer.

Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

Abstract: The disclosure relates to a dimension measurement apparatus that reduces time required for dimension measurement and eliminates errors caused by an operator. Therefore, the dimension measurement apparatus uses a first image recognition model that extracts a boundary line between a processed structure and a background over the entire cross-sectional image and/or a boundary line of an interface between different kinds of materials, and a second image recognition that output information for dividing the boundary line extending over the entire cross-sectional image obtained from the first image recognition model for each unit pattern constituting a repetitive pattern, obtains coordinates of a plurality of feature points defined in advance for each unit pattern, and measures a dimension defined as a distance between two predetermined points of the plurality of feature points.

Abstract: A magnetic property measuring system includes a stage configured to hold a sample and a magnetic structure disposed over the stage. The stage includes a body part, a magnetic part adjacent the body part, and a plurality of holes defined in the body part. The magnetic part of the stage and the magnetic structure are configured to apply a magnetic field, which is perpendicular to one surface of the sample, to the sample. The stage is configured to move horizontally in an x-direction and a y-direction which are parallel to the one surface of the sample.

Abstract: A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Z1/2 centers of the SiC epitaxial layer is 5% or less.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the bound

Abstract: A semiconductor module, including a ceramic board, a circuit pattern metal plate formed on a principal surface of the ceramic board, an external connection terminal bonded, via a solder, to the circuit pattern metal plate, and a low linear expansion coefficient metal plate located between the circuit pattern metal plate and the external connection terminal. The circuit pattern metal plate has a first edge portion and a second edge portion, which are opposite to each other and are respectively at a first side and a second side of the circuit pattern metal plate. The low linear expansion coefficient metal plate has a linear expansion coefficient lower than a linear expansion coefficient of the circuit pattern metal plate.

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.