Abstract: A data storage device is disclosed comprising a storage medium and a head configured to access the storage medium, wherein the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal. The second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node. A first bias signal is applied to the first terminal of the WA1, a second bias signal is applied to the first terminal of the WA2, and a common mode voltage is applied to the common node.

Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Abstract: A magnetic head includes a main pole configured to serve as a first electrode, an upper pole containing a trailing magnetic shield configured to a serve as a second electrode, and an electrically conductive portion located in a trailing gap between the main pole and the trailing magnetic shield. The electrically conductive portion is not part of a spin torque oscillator stack, and the electrically conductive portion includes first and second electrically conductive, non-magnetic material layers. The spin torque oscillator stack is coupled to the first electrically conductive, non-magnetic material layer. The main pole and the trailing magnetic shield are electrically shorted by the electrically conductive portion across the trailing gap between the main pole and the trailing magnetic shield such that an electrically conductive path is present between the main pole and the trailing magnetic shield through the electrically conductive portion.

Abstract: The present disclosure is generally related to a tape head assembly narrower than the width of a tape, wherein the tape head assembly comprises one or more heads, wherein each of the one or more heads comprise a curved surface comprising a first beveled wing, a second beveled wing, and a flat-lapped surface disposed between the first beveled wing and the second beveled wing. The first beveled wing and the second beveled wing each comprise outer corners recessed from a top surface of the flat-lapped surface such that there is no interaction between the outer corners of the beveled wings and the tape.

Abstract: According to one embodiment, a magnetic head includes first and second magnetic poles, and a stacked body provided between the first and second magnetic poles. The stacked body includes a first magnetic layer, a second magnetic layer provided between the second magnetic pole and the first magnetic layer, a third magnetic layer provided between the second magnetic pole and the second magnetic layer, a first non-magnetic layer provided between the first magnetic layer and the first magnetic pole, a second non-magnetic layer provided between the second and first magnetic layers, a third non-magnetic layer provided between the third and second magnetic layers, and a fourth non-magnetic layer provided between the second magnetic pole and the third magnetic layer. A thickness of the first magnetic layer is thicker than a thickness of the second magnetic layer. A thickness of the third magnetic layer is thicker than the second layer thickness.

Abstract: The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device that comprises a first shield, a first spin hall effect layer, a first free layer, a gap layer, a second spin hall effect layer, a second free layer, and a second shield. The gap layer is disposed between the first spin hall effect layer and the second spin hall effect layer. Electrical lead connections are located about the first spin hall effect layer, the second spin hall effect layer, the gap layer, the first shield, and/or the second shield. The electrical lead connections facilitate the flow of current and/or voltage from a negative lead to a positive lead. The positioning of the electrical lead connections and the positioning of the SOT differential layers improves reader resolution without decreasing the shield-to-shield spacing (i.e., read-gap).

Abstract: A hard disk drive enclosure base includes a non-uniform disk shroud surface extending from a top to a floor, the shroud surface including a first portion having a first radius and clearance along the circumference of the shroud surface and a second portion having a lesser second radius and clearance. The second portion of the shroud surface may be positioned at multiple locations where the drive form factor is especially constraining and in view of the need for a sufficient seal land surface for applying a gasket seal around the perimeter of the inner cavity of the base part. Widening the disk shroud clearance where possible can reduce the shear stress exerted at the disk edges thereby reducing the windage drag and associated disk spindle motor power consumption, especially in the context of helium-filled drives in which disk flutter is less of an issue.

Abstract: A seek operation of a first actuator in a multi-actuator drive is modified, so that one or more disturbance-generating portions of the seek operation do not adversely affect operation of a second actuator in the drive. Radial motion of the aggressor actuator is controlled by limiting a slew rate of the first actuator during one or more portions of the seek operation to be less than or equal to a threshold value. Because slew rate of the first actuator is the rate of change of radial acceleration of the aggressor actuator with respect to time, limiting the slew rate of the first actuator prevents or reduces mechanical disturbances caused by jerk associated with motion of the first actuator.

Abstract: An object is to provide a magnetic recording medium having excellent traveling stability and a thin total thickness. The present technology provides a tape-shaped magnetic recording medium including: a magnetic layer; an underlayer; a base layer; and a back layer, in which a surface on a side of the magnetic layer has a kurtosis of 3.0 or more, a surface on a side of the back layer has a kurtosis of 2.0 or more, the surface on the magnetic layer side has arithmetic average roughness Ra of 2.5 nm or less, the base layer includes a polyester as a main component, the magnetic recording medium has an average thickness tT of 5.6 ?m or less, the magnetic recording medium includes a lubricant, the lubricant includes a fatty acid and a fatty acid ester, and a mass ratio between the fatty acid and the fatty acid ester extracted with hexane satisfies fatty acid/fatty acid ester?0.

Abstract: A method for ensuring data quality integrity on a magnetic tape includes the steps of writing object data to the magnetic tape; dividing the object data into a plurality of data chunks; generating a hash tree from the plurality of data chunks, the hash tree being formed in a plurality of levels, the hash tree including (i) a plurality of chunk hashes wherein a separate chunk hash is generated for each of the plurality of data chunks, and (ii) at least one second level hash that is generated from concatenation of at least two of the plurality of chunk hashes; and checking integrity of a first data chunk of the plurality of data chunks by evaluating at least one of the plurality of chunk hashes and the at least one second level hash.

Abstract: Disclosed are a video automatic editing method and system based on machine learning. The video automatic editing system based on machine learning includes at least one processor, and the at least one processor includes a video acquirer configured to acquire input video, a highlight frame extractor configured to extract at least one highlight frame from the input video using a highlight extraction model pre-trained through machine learning, and a highlight video generator configured to generate highlight video from the at least one extracted highlight frame.

Abstract: Systems and techniques for modifying a subsection of uploaded media are presented. An instruction component receives a media file and a media enhancement instruction that includes enhancement data and media interval data for a first segment of the media file. A processing component modifies the first segment of the media file associated with the media interval data based on the enhancement data to generate an edited first segment of the media file. A finalization component generates an edited version of the media file that includes the edited first segment of the media file and at least a second segment of the media file that is not modified based on the enhancement data.

Abstract: Methods and devices are provided for adding lyrics to a short video. The device obtains a music material required by the short video and obtains a first playback duration of the short video. The device obtains a target music material having a playback duration matching the first playback duration. The device obtains a lyric sticker corresponding to the target music material based on the lyrics extracted from the target music material and displays a processed short video after adding with the lyric sticker.

Abstract: Indexing of media sources available to media composition applications, such as video editing applications and digital audio workstations, is extended to sources of an arbitrary type, including non-file type sources. Examples of such sources include devices using baseband video and audio protocols, network ports and physical devices connected via USB, Thunderbolt, etc. The sources are discovered and indexed even when not previously known to the application with the result that any available bitstream becomes available to the application. Applications access the sources via feeders, which are addressable portals through which media essence is received. The indexing methods involve the instantiation of a hierarchy of plug-in software modules by a format-handling subsystem of the application or by a media indexing service servicing one or more applications.

Abstract: A method, apparatus, computer program product and computer accessible code configured to link or otherwise associate content filters with a multimedia presentation, e.g., a movie. The content filter data includes an identifier value with an aspect ratio identifier or as a function of an aspect ratio for a particular multimedia presentation associated with the filter information. In one implementation, association between a filter set and a multimedia presentation involves a filtering application that searches a particular multimedia presentation to locate aspect ratio information and further searches filter information for a matching aspect ratio identifier.

Abstract: A voltage generation circuit includes a noise attenuation circuit configured to attenuate a noise of a second power voltage which has a level that is at least two times higher than that of a first power voltage, and a multi-stage voltage pump configured to receive a noise-attenuated second power voltage from the noise attenuation circuit and generate at least one of plural target voltages, each target voltage having a different level. The first and second power voltages are individually input from an external device via different pins or pads.

Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.

Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

Abstract: An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising: responsive to receiving a memory access command, determining that the memory access command is a dual-address command comprising a source address and a destination address; generating a first content addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing, to the memory device, the read command associated with the first CAM entry.

Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

Abstract: A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

Abstract: A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.

Abstract: An electronic device includes a drive control signal generation circuit and an internal voltage drive circuit. The drive control signal generation circuit detects a level of an internal voltage to generate a drive control signal that adjusts a level of the internal voltage. The internal voltage drive circuit drives the internal voltage based on the drive control signal.

Abstract: A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M?1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M?1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M?1) reference voltages, At least two sense amplifiers of the (M?1) sense amplifiers have different sensing characteristics.

Abstract: A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.

Abstract: A memory device includes an open-for-contact region located between the memory blocks, and a row decoder disposed between global lines to which an operating voltage is supplied and the local lines and configured to transfer the operating voltage to one memory block among the memory blocks in response to a row address, wherein a plurality of contacts are formed in the open-for-contact region and configured to transmit a voltage between the bit lines and a peripheral circuit, wherein a dummy region is included in the row decoder and disposed paced apart from the open-for-contact region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global lines in response to a discharge signal.

Abstract: An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

Abstract: In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

Abstract: An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

Abstract: Embodiments of the present invention provide a computer system, a voltage resistance controlling apparatus, and a method that comprises at least two electrodes on proximal endpoints; a first layer disposed on the at least two electrodes, wherein the first layer is a made of a metal-oxide; a second layer disposed on the second layer, wherein the second first layer is made of an electrically conductive metal-oxide; a forming contact disposed on the second layer, wherein a combination of the forming contact disposed on the first layer disposed on the second layer operatively connects the at least two electrodes; and a computer system operatively connected to the forming contact, wherein the computer system is configured to apply a predetermined voltage to the first layer and the second layer respectively and display an overall resistance increase using a user interface.

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.

Abstract: A method for programming a memory device including a first plane and a second plane is provided. The method includes simultaneously initiating programming of the first plane and the second plane, and in response to the first plane being successfully programmed and the second plane not being successfully programmed, suspending the programming of the first plane, and keeping the programming of the second plane.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

Abstract: A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.

Abstract: A circuit includes a linear regulator coupled with a memory array and a pump regulator coupled with a charge pump, the charge pump to provide a supply voltage to the linear regulator. A digital-to-analog converter (DAC) has an output coupled with the pump regulator. Control logic is coupled with the DAC and is to perform operations including causing a digital input value to be provided to the DAC to selectively adjust the supply voltage based on a programmable offset value.