Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

Abstract: A power amplifier module including an input configured to receive an input radio frequency signal, the input radio-frequency signal including a series of data symbols, an output configured to provide an output radio-frequency signal, a power amplifier having a signal input to receive the input radio-frequency signal and a power supply input to receive a supply voltage, the power amplifier configured to amplify the input radio-frequency signal to provide the output radio-frequency signal, and a controller to receive an indication of a peak output power level of an upcoming data symbol in the series of data symbols, to adjust at least the supply voltage provided to the power amplifier based on the peak output power level of the upcoming data symbol, and to configure the power amplifier module to maintain a substantially constant gain over the series of data symbols.

Abstract: According to one embodiment, a class-D amplifier including: a PWM modulator that outputs a PWM modulation signal in response to an input signal; and a drive circuit that amplifies the PWM modulation signal, and supplies it to an output end. The drive circuit includes: a first output transistor whose main current path is connected between a power source supplying end and the output end; a second output transistor having a size larger than a size of the first output transistor; and a resistance element that is connected between the main current path of the first output transistor and the output end.

Abstract: An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

Abstract: A surface acoustic wave device includes a piezoelectric substrate and a pair of interdigital transducer electrodes. The pair of interdigital transducer electrodes include an alternating region as a region where the electrode fingers connected to one busbar and the electrode fingers connected to the other busbar are alternately provided. When a region on an end portion side of the alternating region and a region including distal end portions of the plurality of electrode fingers is referred to as an edge region, a propagation velocity of a surface acoustic wave in the edge region is slower than a propagation velocity of a surface acoustic wave in the alternating region. A propagation velocity of a surface acoustic wave in a busbar region as a region where the busbar is disposed is faster than the propagation velocity of the surface acoustic wave in the alternating region.

Abstract: A method for packaging chips includes: flip-chip bonding a plurality of filter chips to be packaged on a substrate to be packaged; applying a first mold material layer on the filter chips to be packaged; applying a second mold material layer on a side of the first mold material layer away from the filter chip to be packaged, the first mold material layer and the second mold material layer forming a first mold layer; thinning the first mold material layer and the second mold material layer to expose substrates of the filter chips to be packaged, and thinning the substrates of the filter chips to be packaged to a preset thickness; applying a second mold layer on the exposed substrates of the filter chips to be packaged to obtain a mold structure; and cutting the mold structure into a plurality of particle chips.

Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include four resonator devices and four shunt resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.

Abstract: In general, one aspect disclosed features an active choke circuit, including a first three-winding choke; a second three-winding choke; and an amplifier; wherein a first winding of the first three-winding choke is electrically coupled in series with a first winding of the second three-winding choke; wherein a second winding of the first three-winding choke is electrically coupled in series with a second winding of the second three-winding choke; wherein a third winding of the first three-winding choke is electrically coupled to an input of the amplifier; and wherein a third winding of the second three-winding choke is electrically coupled to an output of the amplifier.

Abstract: A programmable delay device that provides delays of more than 100 ns over a broad bandwidth is disclosed. The device includes an input stage that employs M sampling switched capacitor elements such that each sampling switched capacitor element samples at a rate of only 1/M of the fundamental sampling rate. The device includes a programmable delay stage with M programmable switched capacitor banks, each programmable switched capacitor bank having N delay switched capacitor storage elements. Thus, the programmable delay stage includes a total of M×N delay switched capacitor storage elements, thereby reducing the sampling rate by a factor of M×N. This reduced sampling rate permits much smaller sampling switches, resulting in reduced leakage current and enabling far longer programmable delay times. Lastly, the device includes an output reconstruction stage that reconstructs a delayed version of the input RF signal by combining signals from the programmable delay stage.

Abstract: A method of controlling a switch, including: a) applying a control signal to a control terminal of the switch, said control signal exhibiting at least one first switching between a switch turn-on control state and a switch turn-off control state; and b) applying a switch turn-off potential on said control terminal after a first delay starting at said first switching, the first delay being greater than the turn-off time.

Abstract: A timing generator includes a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a signal synthesizer, and a timing difference extractor. The first current source is for generating a first current according to the input voltage. The second current source is for generating a second current according to the input voltage. The first switch includes a control terminal for receiving a charging signal. The second switch includes a control terminal for receiving a timing difference signal. The third switch includes a control terminal for receiving a reset signal. The capacitor is coupled between a charging terminal and a ground terminal. The signal synthesizer is for generating a timing signal according to a charging voltage and a reference voltage. The timing difference extractor is for generating a timing difference signal according to the timing signal and a deformed timing signal.

Abstract: Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Abstract: A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

Abstract: A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Abstract: Driver circuitry for driving a power semiconductor switch having a control input and main terminals is described. The driver circuitry includes control terminal driver circuitry coupled to the control input and configured to provide a drive signal, a sense terminal coupled to the main terminal, a current mirror coupled to the sense terminal to mirror a current input into the sense terminal during turn-off, a first current comparator configured to compare a current signal received from the current mirror to a first current threshold and output a first signal representative of the comparison, and a second comparator configured to compare a signal received from the sense terminal to a turn-on threshold and output a second signal representative of the comparison. The turn-on threshold represents a highest voltage of the main terminal during turn-on. The first current threshold represents a highest voltage of the main terminal during turn-off.

Abstract: In one aspect, a solid-state switching apparatus is provided that includes a pair of anti-parallel thyristors, a quasi-resonant turn-off circuit, a sensor, and a control circuit. The turn-off circuit is coupled in parallel with the pair of anti-parallel thyristors and includes a first selectively conductive path and a second selectively conductive path. The sensor is configured to sense a thyristor current conducted by at least one of the pair of anti-parallel thyristors. The control circuit is configured to receive the sensed thyristor current from the sensor and determine a magnitude of the sensed thyristor current and a polarity of the sensed thyristor current. The control circuit is further configured to activate, in response to determining that the magnitude is greater than a threshold value, one of the first selectively conductive path and the second selectively conductive path based on the polarity to commutate and interrupt the thyristor current.

Abstract: A power semiconductor device of the present disclosure includes: a first switching element; a second switching element connected in parallel to the first switching element, and having a higher short circuit capability than the first switching element; drive circuits to drive the first switching element and the second switching element; and determination circuits to compare a target current as a sum of a current flowing through the first switching element and a current flowing through the second switching element to a first threshold and a second threshold greater than the first threshold. The drive circuits switch off the first switching element when the determination circuits determine that the target current is equal to or greater than the first threshold, and switch off the second switching element when the determination circuits determine that the target current is equal to or greater than the second threshold.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: A system and method for high speed switching comprises receiving voltage inputs at a bridge rectifier, generating a control signal from a transistor, and driving a gate of a field effect transistor (FET) via the control signal of the transistor, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The system and method further comprises limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

Abstract: A system for sensing touch or proximity include: a first number of input terminals configured to couple one or more capacitive sensors, a second number of transferring units configured to transfer charges from the one or more capacitive sensors through the first number of input terminals in transferring phases of cycles of the one or more capacitive sensor, wherein at least one of the first and second numbers is equal to or greater than two, and a first switching unit, coupled between the first number of input terminals and the second number of transferring units, configured to selectively electrically couple any one of the first number of input terminals to any one of the second number of transferring units in the transferring phases.

Abstract: A capacitive logic cell with complementary control, including a variable-capacitance electromechanical device having a fixed part and a mobile part, the electromechanical device comprising first, second, third and fourth electrodes mounted on the fixed part, and a fifth electrode mounted on the mobile part, the first electrode being connected to a terminal for supplying a first input logic signal, the second electrode being connected to a terminal for supplying a second input logic signal, complementary to the first input logic signal, the third electrode being connected to a terminal for supplying a first output logic signal, and the fourth electrode being connected to a terminal for supplying a second output logic signal, complementary to the first output logic signal.

Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.

Abstract: A NOT logic circuit is provided comprising: one or more memory devices; wherein a first memory address location of the one or more memory devices stores first content data, wherein the first content data includes a first ternary value and a corresponding first priority value, wherein the first ternary value includes a continuous sequence of X-state values that represent a first range of non-X ternary values; wherein a second memory address of the one or more memory device stores second content data that includes a second ternary value and a corresponding second priority value, wherein the second ternary value includes a continuous sequence of non-X state values represent a non-X ternary value that is within the first range of non-X ternary values; an interface is coupled to receive a ternary value from a processing device; comparator circuitry operable to compare a received ternary key with the outputted first ternary value and to compare the received ternary key with the outputted second ternary value; prior

Abstract: This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.

Abstract: Described herein is an apparatus and a method for a low noise infinite radio frequency (RF) delayed-locked loop (DLL). The apparatus comprises a phase detector having a first input configured to receive a first RF signal, a second input, and an output; an infinite phase shifter having a first input configured to receive a second RF signal, an input bus, and an output connected to the second input of the phase detector; and a controller having a first input connected to the output of the phase detector and an output bus connected to the input bus of the infinite phase detector, wherein the output of the infinite phase shifter comprises a low noise signal in phase alignment with the first RF signal.

Abstract: A time-to-digital converter (TDC) circuit includes control logic and a first self-referenced delay cell circuit coupled to the control logic. The first self-referenced delay cell circuit includes: a first bank of capacitors coupled to a first node between a first positive input and a first positive output, where the first bank of capacitors is selectively controlled by a first control signal from the control logic, the first control signal including a first up value corresponding to a first positive threshold; and a second bank of capacitors coupled to a second node between a first negative input and a first negative output, where the second bank of capacitors is selectively controlled by a second control signal from the control logic, the second control signal including a first down value corresponding to a first negative threshold.

Abstract: In a wireless power transmitting device, a control circuit outputs a control signal for setting a frequency and a phase of an F-PLL signal generated by an F-PLL, the F-PLL generates the F-PLL signal having the frequency and the phase set by the control signal output from the control circuit, and a frequency conversion circuit generates a transmission signal by converting a frequency of the F-PLL signal generated by the F-PLL.

Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

Abstract: The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

Abstract: A switch-mode power supply includes a pair of input terminals, a pair of output terminals, and at least one switch coupled between the input terminals and the output terminals. The power supply further includes an analog-to-digital converter (ADC) for converting a sensed analog current value at the output terminals to an output digital value, an interface for receiving a user configurable current setting, and a control circuit coupled with the interface, the ADC and the at least one switch. The control circuit is configured to determine a raw digital value of the ADC that corresponds to the received current setting by processing an iterative loop, and turn on and turn off the at least one switch according to the determined raw digital value and the output digital value of the ADC, to supply an output current at the pair of output terminals that corresponds to the received current setting.

Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

Abstract: Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: A multi-band radio frequency front-end device, a multi-band receiver, and a multi-band transmitter, the multi-band radio frequency front-end device including a first radio frequency front-end circuit, where the first radio frequency front-end circuit works on a first band, a second radio frequency front-end circuit, where the second radio frequency front-end circuit works on a second band, a first input/output matching network, and a second input/output matching network, where routing of the first input/output matching network and routing of the second input/output matching network on a layout are annular and nested.

Abstract: A first UE may transmit, to a second subset of one or more second UEs, one or more pilot signals associated with DPD training. The first UE may receive, from a third subset of the one or more second UEs, one or more feedback messages associated with DPD training. The one or more feedback messages may be based on the one or more pilot signals. Each second UE in the third subset of the one or more second UEs may correspond to one of the one or more feedback messages. The second UE may calculate one or more DPD parameters based on the one or more feedback messages. The second UE may transmit a first signal based on the calculated one or more DPD parameters.

Abstract: A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Abstract: In a signal detection apparatus, a quadrature detection circuit subjects a reception signal to quadrature detection. An intensity detection circuit detects a signal intensity by referring to an absolute value of an amplitude of a signal subjected to quadrature detection. A zero cross detection circuit detects the number of times of zero crosses of the signal in a predetermined period of time that is based on a modulation index of the reception signal. A signal determination circuit that determines that the signal is the reception signal when the signal intensity is equal to or higher than a threshold value and the number of times of zero crosses is within a predetermined range.

Abstract: A noise reduction device includes: a combiner to shift a phase of one of a first signal propagating through a first propagation path and a second signal propagating through a second propagation path by a predetermined angle and combine the phase-shifted one signal of the first signal and the second signal with the other signal of the first signal and the second signal; and a phase difference absorption circuit having a phase shift characteristic that reduces a difference between a phase difference between two signals each having a lower limit frequency of a band of the broadcast wave and passing through the first propagation path and the second propagation path and a phase difference between two signals each having an upper limit frequency of the band of the broadcast wave and passing through the first propagation path and the second propagation path.

Abstract: A radio frequency circuit with font routing to replace a resistor includes a routing layer and a ground layer. The routing layer includes a first pad, a second pad and a font routing unit. The second pad is corresponding to the first pad. The font routing unit is connected between the first pad and the second pad, and has a trace width. The trace width is less than a 50 ohm trace width. The ground layer is disposed below the routing layer and is separated from the routing layer by a height. The font routing unit has a second equivalent impedance at the radio frequency, the second equivalent impedance is determined according to the trace width, the height and the radio frequency, and the second equivalent impedance is the same or similar to a first equivalent impedance.

Abstract: Various data transmission detection systems are described. A receiver input through which a wireless data transmission signal is received may be present. A plurality of mixers in communication with the receiver input may be present, which may be digitally implemented. A data transmission detector may be present that receives a mixed wireless data transmission signal from each mixer and creates a plurality of scores. A match detection module may be present that receives the scores and identifies a highest score. The signal mapped to the highest score to be selected for further processing.

Abstract: A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

Abstract: Portable electronic devices are provided. Each device may be formed from two parts. A first part may be provided with components such as a display, a touch screen, a cover glass, and a frame. A second part may be provided with a plastic housing, circuit boards containing electrical components, and a bezel. Engagement members may be connected to the first and second parts. The engagement members may be formed from metal clips with holes and springs with flexible spring prongs that mate with the holes in the clips. The metal clips may be welded to frame struts on the frame and the springs may be welded to the bezel. During assembly, the first part may be rotated into place within the second part. Retention clips attached to the frame may be used to secure the two parts together. Assembly instructions and associated connector numbers may be provided within the devices.

Abstract: Examples relate to a cable modem, to an apparatus, device and method for a cable modem, and to an apparatus, device and method for a cable communication system. The apparatus or device for the cable modem comprises interface circuitry/communication means for communicating with transceiver circuitry/transceiving means of the cable modem, and processing circuitry/processing means. The processing circuitry/means is configured to determine information on a power level of received transmissions at a plurality of points in time in a plurality of frequency bands of an upstream spectrum via the transceiver circuitry, to determine, for each of the plurality of frequency bands, numeric information on an occurrence of one or more power levels of the received transmissions in the respective frequency band, and aggregate the numeric information on the occurrence of the one or more power levels of the received transmissions by frequency band.

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.