Abstract: The present invention relates to audio coding systems which make use of a harmonic transposition method for high frequency reconstruction (HFR). A system and a method for generating a high frequency component of a signal from a low frequency component of the signal is described. The system comprises an analysis filter bank providing a plurality of analysis subband signals of the low frequency component of the signal. It also comprises a non-linear processing unit to generate a synthesis subband signal with a synthesis frequency by modifying the phase of a first and a second of the plurality of analysis subband signals and by combining the phase-modified analysis subband signals. Finally, it comprises a synthesis filter bank for generating the high frequency component of the signal from the synthesis subband signal.

Abstract: Apparatus, methods and computer-readable medium are provided for processing wind noise. Audio input is processed by receiving an audio input. A wind noise level representative of a wind noise at the microphone array is measured using the audio input and a determination is made, based on the wind noise level, whether to perform either (i) a wind noise suppression process on the audio input on-device, or (ii) the wind noise suppression process on the audio input on-device and an audio reconstruction process in-cloud.

Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for information processing. The method may be applied to an electronic equipment. The electronic equipment may collect environmental audio information when the electronic equipment plays multimedia. The electronic equipment may also perform noise detection on the environmental audio information to determine whether the environmental audio information represents a target noise scenario. The electronic equipment may also process a parameter of the multimedia played by the electronic equipment when the environmental audio information represents the target noise scenario.

Abstract: A computer implemented method, system and computer program product are provided that implement a neural network (NN) audio filter. The method, system and computer program product obtain an electronic audio signal comprising a speech impaired message and apply the audio signal to the NN audio filter to modify the speech impaired message to form an unimpaired message. The method, system and computer program product output the unimpaired message.

Abstract: Audio processing with audio transparency can include receiving a user content audio signal and receiving a microphone signal. The microphone signal can contain sensed sound of a user environment. Strength of the sensed sound can be increased based on strength of the user content audio signal, to reduce a masking of the sensed sound during playback. The sensed sound and the user content audio signal can be combined in a composite output audio signal used to drive a speaker. Other aspects are also described and claimed.

Abstract: In an approach, a processor extracts an audio signal from a video clip. A processor converts the audio signal into a text sequence. A processor selects a first set of keywords from the text sequence, the first set of keywords corresponding to a first audio segment of the audio signal. A processor tags a target video segment of the video clip with the first set of keywords, the target video segment corresponding to the first audio segment.

Abstract: Providing contextual help in an interactive voice system includes receiving a plurality of user interaction events during a user interaction window, wherein each of the user interaction events comprises one of a low quality voice transcription event from a speech-to-text (STT) service or a no-intent matching event from a natural language processing (NLP) service and receiving a respective transcription confidence score from the STT service for each of the plurality of user interaction events. For a one of the plurality of user interaction events, a determination is made of how to respond to a user providing the user interaction events based on how many events comprise the plurality of events and the transcription confidence score for the one event; and then instructions are provided to cause the determined response to be presented to the user in accordance with the determination of how to respond.

Abstract: The present disclosure is generally directed towards magnetic recording systems comprising a dual free layer (DFL) read head and a magnetic recording head having stable magnetization. The magnetic recording head comprises a main pole disposed at a media facing surface (MFS), and a plurality of shields, such as a lower leading shield, an upper leading shield, a pair of side shields, and a trailing shield. Each of the shields individually comprises a first leg disposed at and parallel to the MFS and a second leg coupled to the first leg, the second leg being recessed from the MFS. When the kind of magnetization initialization needed by the DFL read head is applied to the magnetic recording head during the manufacturing process, the second leg of each of the shields of the magnetic recording device causes the magnetization directions of the shields to individually switch to a stable state.

Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a main pole at a media facing surface (MFS), a trailing shield at the MFS, and a heavy metal layer disposed between the main pole and the trailing shield at the MFS. Spin-orbit torque (SOT) is generated from the heavy metal layer and transferred to a surface of the main pole as a current passes through the heavy metal layer in a cross-track direction. The SOT executes a torque on the surface magnetization of the main pole, which reduces the magnetic flux shunting from the main pole to the trailing shield. With the reduced magnetic flux shunting from the main pole to the trailing shield, write-ability is improved.

Abstract: A magnetic recording head assembly is provided and is configured to read from and write to a magnetic media. The head assembly includes a first module having a first media facing surface (MFS), a first closure, and a first recessed portion disposed between the first MFS and the first closure. The first MFS includes AlTiC. A second module is provided having a second MFS, a second closure, and a second recessed portion disposed between the second MFS and the second closure. The second MFS includes AlTiC. An overcoat disposed within the first and second recessed portions includes an adhesive layer and a protective layer disposed within the first and second recessed portion.

Abstract: Certain embodiments are directed to a spin torque oscillator (STO) device in a microwave assisted magnetic recording (MAMR) device. The magnetic recording head includes a seed layer, a spin polarization layer over the seed layer, a spacer layer over the spin polarization layer, and a field generation layer is over the spacer layer. In one embodiment, the seed layer comprises a tantalum alloy layer. In another embodiment, the seed layer comprises a template layer and a damping reduction layer over the template layer. In yet another embodiment, the seed layer comprises a texture reset layer, a template layer on the texture reset layer, and a damping reduction layer on the template layer.

Abstract: The present disclosure generally relates to a tape drive including a tape head. The tape head comprises at least one same gap verify (SGV) module comprising a plurality of write transducer and read transducer pairs disposed on a substrate. Each pair comprises a null shield disposed between the write transducer and the read transducer. One or more of a position between the write transducer and the read transducer of each pair, a width, a height, a thickness, and a permeability of the null shield is adjusted to create a null region, and the read transducer is disposed in the null region. The SGV module is configured to write data to a tape using the write transducer of each pair and read verify the data written on the tape using the read transducer of each pair such that the write transducer and read transducer of each pair are concurrently operable.

Abstract: A Permanent Magnet Degausser Mechanism for Destroying the Functionality of Data Bearing Components of Magnetic Media Data Bearing Devices. This permanent magnet degausser mechanism provides reconciliation and tracking with a unique. identification tag using a secure and proprietary database, destruction of the functionality of the data bearing components of magnetic media data bearing devices using an automated movement system, a NSA Certified high strength degausser, digital pre-degaussing and post-degaussing readings to indicate the completion of the process of destroying the functionality of the data bearing components including storage of readings and containment of the remains of the magnetic media devices for verification.

Abstract: In response to a rotation of timing-based servo (TBS) patterns of a first servo band and a second servo band, heights of top and bottom portions of servo stripes of servo frames of the TBS patterns are adjusted to compensate for changes in a usable height of the servo stripes caused by the rotation.

Abstract: A magnetic-disk substrate has a pair of main surfaces, and an arithmetic average roughness Ra of each of the main surfaces is 0.11 nm or less. The arithmetic average roughness Ra is a value obtained through measurement using an atomic force microscope provided with a probe having a probe tip provided with a carbon nanofiber rod-shaped member. The magnetic-disk substrate is made of glass or aluminum alloy.

Abstract: A ring-shaped glass spacer is configured to be arranged in contact with a magnetic disk in a hard disk drive apparatus. A surface resistivity of a surface of a glass material of the glass spacer at 22 (° C.) is lower than a surface resistivity of an inner portion of the glass material at 22 (° C.).

Abstract: An archival data storage system library includes magnetic-recording disk media, a storage enclosure in which the media are housed, data storage devices (DSDs) configured to write to and read from the media, an automated disk handling mechanism configured to transfer at least some of the media between the storage enclosure and the DSD, and a hermetic enclosure containing the foregoing components. The storage system may further include a gas circulation system for filtering contaminants from the hermetic enclosure. Such a storage system may be implemented as a rack-mountable unit, or as an entire cleanroom facility, as well as in intermediate form factors between those. In the context of a cleanroom storage system, the system may further include an automated disk handling shuttle to receive the media from the disk handling mechanism and an automated disk loading mechanism for accessing the media from the shuttle for installing into the DSD.

Abstract: The technology disclosed herein pertains to a system and method for managing off-track retry. An implementation of a method of determining offset direction for read off-track retry includes storing analog to digital converter (ADC) values of data read from a data sector by a data reader in a read channel buffer, calculating an indicator value of the distribution of the ADC values, determining an amount of offset for the data reader based on the indicator value, and moving the data reader by the amount of offset before performing a read retry operation.

Abstract: This application provides a hard disk format conversion method and apparatus, and a storage device, and belongs to the field of storage technologies. In this application, a storage format of a storage unit is converted from an SMR format to a PMR format. Because IOPS in the PMR format is higher than IOPS in the SMR format, IOPS in the storage unit can be increased after the storage format is converted. Alternatively, a storage format of a storage unit is converted from the PMR format to the SMR format. Because a storage capacity in the SMR format is higher than a storage capacity in the PMR format, a storage capacity of the storage unit can be increased after the storage format is converted.

Abstract: The technology disclosed herein pertains to a system and method for managing write failures in a disc drive. Implementations disclosed herein provide a method including monitoring write fault events per sector for a storage device, in response to a write fault event, updating a write fault repeat count table, wherein the repeat count table tracks a number of write fault repeat counts per sector, comparing a write fault repeat count for a sector to a predetermined threshold write fault repeat count, and in response to determining that the write fault repeat count for a sector is above the predetermined threshold write fault repeat count, performing a write-reassign operation.

Abstract: According to one embodiment, a magnetic disk device includes a plurality of magnetic disks, a plurality of magnetic heads provided correspondingly to the plurality of magnetic disks and configured to carry out read/write of data from/to the magnetic disks, and a control section configured to control read/write of the magnetic heads. Each of the plurality of magnetic disks includes a first storage section storing therein control information concerning read/write of the magnetic head. The control section switches the first storage section which is a storage destination of first information that is at least a part of the control information from the magnetic disk to another magnetic disk.

Abstract: A base member serves as a part of a housing of a hard disk drive device. The base member includes a base body being a cast product, a first machined surface obtained by machining a portion formed with a convex portion of the base body, and a coating film covering a surface of the base body. The base body includes a coated surface obtained by covering the first machined surface with the coating film, and a second machined portion obtained by machining a part of the base body other than the first machined surface.

Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Abstract: Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Abstract: A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

Abstract: A data writing control device includes a control signal generator, a data strobe enable signal generator and a data strobe index generator. The control signal generator receives a write command, a preamble setting value and a latency setting value, and generates an internal write pulse and preamble information according to the write command, the preamble setting value and the latency setting value. The data strobe enable signal generator is coupled to the control signal generator and generates a data strobe pipeline enable signal according to the internal write pulse and the preamble setting value. The data strobe index generator is coupled to the data strobe enable signal generator, and generates a plurality of data strobe indexes according to the data strobe pipeline enable signal and the preamble information.

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

Abstract: According to an embodiment, a magnetoresistive memory device includes a layer stack. The layer stack includes a first ferromagnet, an insulator on the first ferromagnet, and a second ferromagnet on the insulator. A nonmagnet is provided above the layer stack. A first conductor is provided on the nonmagnet. A hard mask is provided above the first conductor. The nonmagnet includes a material that is removed at a first etching rate against a first ion beam. The first conductor includes a material that is removed at a second etching rate against the first ion beam. The first etching rate is lower than the second etching rate.

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Abstract: A memory device includes a page made of a plurality of memory cells arranged in rows on a substrate. A page write operation is performed, during which, in each of the memory cells included in the page, a first voltage V1 is applied to a first drive control line PL, a second voltage V2 is applied to a word line WL, a third voltage V3 is applied to a source line SL, a fourth voltage V4 is applied to a bit line BL, a group of holes generated by an impact ionization phenomenon is retained in an inside of the channel semiconductor layer. A page erase operation is performed, during which the voltages to be applied to the first drive control line PL, the word line WL, the source line SL, and the bit line BL are controlled to discharge the group of holes from the inside of the channel semiconductor layer, and the voltage of the channel semiconductor layer is decreased.

Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.

Abstract: A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Abstract: Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.

Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

Abstract: A resistive random access memory (RRAM) circuit and related method limits current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

Abstract: Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.