Abstract: A retaining ring comprises a generally annular body. The body comprises a top surface, a bottom surface, an outer surface connected to the top surface at an outer top perimeter and the bottom surface at an outer bottom perimeter, and an inner surface connected to the top surface at an inner top perimeter and the bottom surface at an inner bottom perimeter. The inner surface comprises seven or more planar facets. Adjacent planar facets are connected at corners. The inner bottom perimeter comprises straight edges of the planar facets connected at the corners.

Abstract: In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Abstract: A temporary protective film for semiconductor sealing molding includes a support film and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent. The content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

Abstract: An improved fluid delivery system and method that directly controls the concentration of constituent components in a fluid mixture delivered, for example, to a process chamber. Pressure of the fluid mixture can also be directly controlled. A concentration sensor capable of measuring concentration of all of the constituent components in a fluid mixture is used to provide signals used to vary the flow rate of constituent gases under a closed loop feedback system. The signal output of one or more pressure sensors can also be used to provide a signal used to vary the flow rate of constituent gases under a closed loop feedback system. By directly controlling these two extremely important process variables, embodiments of the present invention provide a significant advantage in measurement accuracy over the prior art, enable real-time process control, reduce system level response time, and allow for a system with a significant footprint reduction.

Abstract: According to one embodiment, a processing apparatus for processing substrates having different base shapes includes a stage comprising a first portion having a substrate facing surface and an opening extending therethough connected to a source of a cooling fluid, and a second portion located outwardly of the first portion, a substrate support, having a substrate support surface thereon, extending over the second portion, a process fluid outlet overlying the first portion, and a driving unit coupled to one of the stage and the first portion, wherein the driving unit is configured to move at least one of the substrate support surface and the substrate facing surface such that the relative locations of the substrate support surface and the substrate facing surface of the stage are changeable based on the shape of a substrate to be processed in the apparatus.

Abstract: A cleaning system for processing a substrate after polishing includes a sulfuric peroxide mix (SPM) module, at least two cleaning elements, and a plurality of robots. The SPM module includes a sulfuric peroxide mix (SPM) cleaner having a first container to hold a sulfuric peroxide mix liquid and five to twenty first supports to hold five to twenty substrates in the liquid in the first container, and a rinsing station having a second container to hold a rinsing liquid and five to twenty second supports to hold five to twenty substrates in the liquid in the second container. Each of the at least two cleaning elements are configured to process a single substrate at a time. Examples of a cleaning element include a megasonic cleaner, a rotating brush cleaner, a buff pad cleaner, a jet spray cleaner, a chemical spin cleaner, a spin drier, and a marangoni drier.

Abstract: A substrate treatment apparatus according to an embodiment includes: a tank configured to store a liquid chemical with which a plurality of substrates are treated; a piping having an ejection port that ejects the liquid chemical or bubbles into the tank; a plurality of rods that support the plurality of substrates in the tank; and a converter that is provided in the plurality of rods or the tank and that converts vibration applied to each substrate by the liquid chemical or the bubbles ejected from the piping into rotation in one direction around a center of the substrate as a rotational axis.

Abstract: A workpiece cutting method of cutting a workpiece along a plurality of crossing division lines formed on a front side of the workpiece, by using a cutting blade having a thickness gradually decreasing toward an outer circumference of the cutting blade. The workpiece cutting method includes a shape checking step of checking a shape of the cutting blade; a cut depth setting step of setting a cut depth by the cutting blade into the workpiece according to the shape checked in the shape checking step such that a width of a cut groove to be formed on the front side of the workpiece becomes a previously set value; and a cutting step of cutting the workpiece with the cut depth set in the cut depth setting step, by forcing the cutting blade into the workpiece from the front side thereof.

Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.

Abstract: Apparatus and methods for handling die carriers are disclosed. In one example, a disclosed apparatus includes: a load port configured to load a die carrier operable to hold a plurality of dies into a processing tool; and a lane changer coupled to the load port and configured to move at least one die in the die carrier to an input of the processing tool and transfer the at least one die into the processing tool for processing the at least one die.

Abstract: A storage device for use with at least one batch furnace for batch treatment of wafers supported in a wafer boat is disclosed. The storage device comprises a cassette storage carousel for storing a plurality of wafer cassettes on rotatable platform stages. A carousel housing bounds a mini-environment chamber in which the platform stages are accommodated. A gas recirculation circuit of the storage device subsequently comprises a gas inlet channel, a gas inlet filter, the mini-environment chamber, a plurality of gas outlet openings in a bottom wall of the carousel housing, a plenum housing bounding a plenum chamber, a plenum chamber outlet, a gas circulation pump connecting the plenum chamber outlet to an inlet end of the gas inlet duct.

Abstract: A pellicle removal tool including a stage that holds a photomask and an associated pellicle, two or more arms positioned around the stage and configured to engage pellicle side wells of the pellicle, and two or more actuators each configured to adjust at least a vertical position of a corresponding one of the two or more arms so as to apply a lifting force to the pellicle for removal of the pellicle from the photomask.

Abstract: Aspects of the present disclosure relate to one or more implementations of a substrate support for a processing chamber. In one implementation, a substrate support includes a body having a center, and a support surface on the body configured to at least partially support a substrate. The substrate support includes a first angled wall that extends upward and radially outward from the support surface, and a first upper surface disposed above the support surface. The substrate support also includes a second angled wall that extends upward and radially outward from the first upper surface, the first upper surface extending between the first angled wall and the second angled wall. The substrate support also includes a second upper surface extending from the second angled wall. The second upper surface is disposed above the first upper surface.

Abstract: A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.

Abstract: Substrate supports comprising a top plate positioned on a shaft are described. The top plate including a primary heating element a first depth from the surface of the top plate, a inner zone heating element a second depth from the surface of the top plate and an outer zone heating element a third depth from the surface of the top plate. Substrate support assemblies comprising a plurality of substrate supports and methods of processing a substrate are also disclosed.

Abstract: The present disclosure relates to a spin head, apparatus and method for treating a substrate including the spin head. The spin head includes a supporting plate where a substrate is placed and a chuck pin placed on the supporting plate and supporting a lateral portion of the substrate, wherein the chuck pin includes an outer body and an inner body inserted in the outer body and provided with a different material from the outer body, wherein each outer body and the inner body is provided with any one of a first material or a second material, and wherein one material of the first material and the second material is provided with a material having lower heat conductivity and better thermal resistance than another one.

Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: There may be provided a method for inspecting a top redistribution layer conductors of an object. The top redistribution layer (RDL) is positioned above at least one lower RDL and above at least one other dielectric layer. The method may include (i) illuminating the object with radiation, the at least one lower dielectric layer significantly absorbs the radiation; (ii) generating, by a detector, detection signals that represent radiation reflected from the object, and (iii) processing, by a processor, the detection signal to provide information about the top RDL. The processing may include distinguishing detection signals related to the top RDL from detection signals related to the at least one lower RDL.

Abstract: Devices for fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a base substrate having an opening; and a first gate layer formed in the opening. In the first gate layer closes a top of the opening and the first gate layer includes at least one void. The semiconductor structure further includes a second gate layer formed on the first gate layer. An atomic radius of the material of the second gate layer is smaller than gaps among atoms of the material of the first gate layer and the void is filled by atoms of one of the material of the first gate layer and the material of the second gate layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respect

Abstract: A system, method, and computer-readable medium are disclosed automatic validation of light emitting diodes (LEDs) of disk drives in disk processor enclosures (DPEs) or disk array enclosures (DAEs) during the manufacturing and integration of computer systems. An automated test script is performed in support of the integration of the computer system that includes the LEDs and includes a validation and checking step for the LEDs. A determination is made if a camera is properly calibrated to identify the LEDs as part of the validating and checking step for the LEDs. A DPE or DAE that contains disk drive units that include the LEDs are identified, and an indication is performed as to which LEDs pass or fail.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.

Abstract: A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.

Abstract: A power semiconductor module includes an insulating circuit substrate; a printed circuit board disposed over the insulating circuit substrate; and a plurality of terminals each having a rod-shaped portion and including a first protrusion and a second protrusion each protruding laterally form a side face of the rod-shaped portion; wherein at least one of the plurality of terminals is inserted to one of the through-holes of the printed circuit board and is locked to the one of the through-holes via the first protrusion, and wherein at least another one of the plurality of terminals is inserted to another one of the through-holes of the printed circuit board and is locked to said another one of the through-holes via the second protrusion, and an end of the at least another one of the plurality of terminals is electrically connected to a conductive plate on the insulating circuit substrate.

Abstract: A module includes components on an upper surface and a lower surface of a substrate, a second sealing resin layer laminated on the upper surface of the substrate, a first sealing resin layer on the lower surface of the substrate, and terminal blocks on the lower surface of the substrate. Each of the terminal blocks is formed by integrating a plurality of connection conductors, each of the plurality of connection conductors including a terminal portion and a substrate connecting portion formed by bending an end portion of the connection conductor, and each of the terminal blocks forms an external connection terminal of the module or functions as a shield wall for the components. Each of the terminal blocks 6 can be formed by mounting a terminal assembly onto the lower surface of the substrate, sealing the terminal assembly with a resin, and removing connecting portions.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

Abstract: An arrangement includes a panel configured as a pre-form for manufacturing a plurality of component carriers; a protection layer covering a surface portion of a main surface of the panel, wherein the protection layer is detachable from the surface portion without leaving residues on the panel. A handling tool for handling the panel includes a surface onto which the panel is arrangeable. The panel includes a handling surface, with which the panel is arrangeable onto the handling tool, wherein the handling surface comprises at least part of the surface portion covered by the protection layer.

Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Abstract: An electronic system includes a plurality of heat sources. At least two of the plurality of heat sources vary in height and each of the plurality of heat sources includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each of the plurality of heat sources is positioned adjacent to the first side of the substrate. The electronic system further includes a cover member provided above the plurality of heat sources and a sintering thermal interface material provided between the cover member and the first side of one of the at least two heat sources that vary in height.

Abstract: To provide a method for manufacturing a heat dissipation component having excellent heat dissipation properties, in which there is minimal return of warping after the bonding of a circuit board, and to provide a heat dissipation component manufactured using the method. Provided is a method for manufacturing a warped flat-plate-shaped heat dissipation component containing a composite part that comprises silicon carbide and an aluminum alloy, wherein the method for manufacturing the heat dissipation component is characterized in that the heat dissipation component is sandwiched in a concave-convex mold having a surface temperature of at least 450° C. and having a pair of opposing spherical surfaces measuring 7000-30,000 mm in curvature radius, and pressure is applied for 30 seconds or more at a stress of 10 kPa or more such that the temperature of the heat dissipation component reaches at least 450° C.

Abstract: Disclosed herein are integrated circuit (IC) packages with asymmetric adhesion material regions, as well as related methods and devices. For example, in some embodiments, an IC package may include a solder thermal interface material (STIM) between a die of the IC package and a lid of the IC package. The lid of the IC package may include an adhesion material region, in contact with the STIM, that is asymmetric with respect to the die.

Abstract: A semiconductor assembly includes a power semiconductor, a housing containing the power semiconductor, and electrically conductive channels. The electrically conductive channels are arranged to direct coolant through the housing. Heat generated by the power semiconductor can therefore be absorbed by the coolant. The electrically conductive channels are also electrically connected with the power semiconductor to form terminals for the power semiconductor.

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

Abstract: An electronic device includes: a flexible substrate including a through hole; a connecting element disposed in the through hole; a semiconductor disposed on the flexible substrate; and a first conductive element disposed under the flexible substrate, wherein the first conductive element electrically connects to the semiconductor through the connecting element, wherein a distance between the semiconductor and the connecting element ranges from 5 ?m to 500 ?m.

Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.

Abstract: A semiconductor package includes a terminal pad having at least one first terminal lead structurally connected to the terminal pad, a semiconductor chip attached to an upper surface of the terminal pad by using a first adhesive, a heat radiation board attached to a lower surface of the terminal pad by using a second adhesive, and at least one second terminal lead electrically connected to the semiconductor chip. The second terminal lead is spaced apart from the terminal pad and is separated from the radiation board. The package further includes a metal clip electrically connecting the semiconductor chip to the second terminal lead, and a package housing covering parts of the first terminal lead, the second terminal lead, and the terminal pad. The package housing includes an adhesive spread space to expose the lower surface of the terminal pad.