Abstract: Herein disclosed is a voltage isolation circuit coupled to power supplies. The voltage isolation circuit comprises a series switch group controlled by a first control signal, a parallel switch group controlled by a second control signal, and a first high impedance element. The series switch group comprises a transistor arranged in a first current loop and having two channels connected to one of the power supplies respectively. The first high impedance element, coupled to the transistor in parallel, has a measurement terminal and two ends, connected to one of the power supplies respectively. When the series switch group is conducted, the power supplies are coupled in series in the first current loop. When the parallel switch group is conducted, the power supplies are coupled in parallel in a second current loop. Impedance values measured from the measurement terminal to each end of the first high impedance element are identical.

Abstract: Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: A closed-loop feedback system and method of active noise cancellation to maintain a desired operating frequency of a qubit during a quantum computation, even when that frequency is relatively sensitive to flux noise. A series of Ramsey experiments is performed on the qubit to estimate an offset between its actual and desired operating frequencies, and the error is accumulated. After the probing is complete, the accumulated error is supplied to an arbitrary waveform generator that produces a magnetic flux that is coupled to the qubit, thereby tuning the qubit and actively controlling its operating frequency. Having corrected the operating frequency of the qubit and extended its coherence time, the quantum state of the qubit is allowed to evolve according to the computation.

Abstract: There is described herein a topologically protected quantum circuit with superconducting qubits and method of operation thereof. The circuit comprises a plurality of physical superconducting qubits and a plurality of coupling devices interleaved between pairs of the physical superconducting qubits. The coupling devices comprise at least one ?-Josephson junction, wherein a Josephson phase ?0 of the ?-Josephson junction is non-zero in a ground state, the coupling devices have a Josephson energy EJ?, the physical superconducting qubits have a Josephson energy EJq, and the circuit operates in a topological regime when E J ? q 2 > - E J ? ? ? cos ? ? 0 > E J ? q 3 .

Abstract: A switch device includes a main module, which includes at least one main electronic control circuit, connections to the electrical system of a building and/or to equipment or devices to be controlled, one or more touch sensors or contacts connected to the at least one main electronic control circuit, a main box-shaped housing element for the preceding components, and one or more systems that provide a reversible electric or electronic and mechanical connection of the main module to an accessory module.

Abstract: Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.

Abstract: The present disclosure relates to the technical field of integrated circuits, and specifically to a delay-locked loop, a control method for a delay-locked loop, and an electronic device. The delay-locked loop includes: a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

Abstract: An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator, a threshold generator and a controller. The comparator receives an analog signal and the SAR ADC outputs an output codeword. The comparator performs a plurality of first comparisons and a plurality of second comparisons. The controller determines a plurality of most significant bits of the output codeword according to a plurality of first comparison results corresponding to the first comparisons. The first comparisons are performed by comparing the analog signal with a plurality of first thresholds. The controller determines a plurality of least significant bits of the output codeword according to a plurality of second comparison results corresponding to the second comparisons. The second comparisons are performed by comparing the analog signal with a second threshold.

Abstract: A method to automatically optimize waveform captures from an electrical system includes capturing at least one energy-related waveform using at least one Intelligent Electronic Device (IED) in the electrical system. The at least one captured energy-related waveform is analyzed to determine if the at least one captured energy-related waveform is capable of being compressed, while maintaining relevant attributes for characterization, analysis and/or other use. In response to determining the at least one captured energy-related waveform is capable of being compressed, while maintaining relevant attributes for characterization, analysis, and/or use, the at least one captured energy-related waveform may be compressed using at least one compression technique to generate at least one compressed energy-related waveform. One or more actions may be taken based on or using the at least one compressed energy-related waveform.

Abstract: A network element is configured to efficiently load balance packets through a computer network. The network element receives a packet associated with flow attributes and generates a Load Balancing Flow Vector (LBFV) from the flow attributes. The network element partitions the LBFV into a plurality of LBFV blocks and reorders the LBFV blocks to generate a reordered LBFV. The LBFV blocks are reordered based on a reordering sequence that is different from reordering sequences on other network elements in the computer network. The network element hashes the reordered LBFV to generate a hash key for the packet and selects a next hop link based on the hash key. The next hop link connects the network elements to a next hop network element in the computer network.

Abstract: A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

Abstract: A method and an apparatus for decoding polar codes, the method comprising: determining a starting level for processing an overflow according to a number of encoded bits of a received polar encoded codeword, an input bit-width, and an internal bit-width of a decoder; multiplying an output Log-Likelihood Ratio (LLR) value and two input LLR values of the G function by a first coefficient and a second coefficient respectively; and finally, the LLR values corresponding to the received codeword are decoded to obtain decoded bits.

Abstract: A method and a decoder for receiving a message encoded in Turbo Codes and modulated for transmission as an analog signal includes: (a) demodulating the analog signal to recover the Turbo Codes; and (b) decoding the Turbo Codes to recover the message using an iterative Turbo Code decoder, wherein the decoding includes performing an error detection after a predetermined number of iterations of the Turbo Code decoder to determine whether or not an error has occurred during the transmission. The predetermined number of iterations may be, for example, two. Depending on the result of the error detection, the decoding may stop, a request for retransmission of the message may be sent, or further iterations of decoding in the Turbo Code decoder may be carried out.

Abstract: There is provided an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.

Abstract: A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

Abstract: This application discloses a data transmission method, apparatus, and system. The method includes: generating a to-be-sent bit sequence, where the to-be-sent bit sequence includes one or more bits in a bit sequence having a length of (N?M), where N is a length of a mother code for polar encoding, M is a length of encoded bits obtained after rate matching is performed on a bit sequence having a length of N, N is m raised to the power of an integer, m is a positive integer greater than 1, M is a positive integer, and N>M; and sending the generated bit sequence. A corresponding apparatus and system are further disclosed. In this application, in this data transmission solution, an additional coding gain is generated during decoding, so that a decoding FER is reduced, and decoding performance is improved.

Abstract: A half-bride combiner can be implemented as a coupling circuit having a common node and configured to couple the common node to one of first and second groups of filters through a first path and to couple the common node to the other group through a second path. The coupling circuit can be further configured such that the impedance provided by each filter of the one of the first and second groups for a signal in each band of the other group results in the signal being sufficiently excluded from the first path.

Abstract: A connecting member in a radio control transmitter for transmitting a control signal to a control target by controlling an operating portion detachably attached to a main body is provided. The connecting member is disposed between the main body and the operating portion to randomly set a position of the operating portion with respect to the main body, wherein the connecting member has outer fitting holes arranged along a circumference of a large diameter and inner fitting holes arranged along a circumference of a small diameter to be concentric with arrangement of the outer fitting holes.

Abstract: The embodiments include a stackable computing device that includes an integrated heatsink and antenna structure and a housing structure. The housing structure includes a housing casing that surrounds the integrated heatsink and antenna structure. The integrated heatsink and antenna structure includes a heatsink base and one or more radio frequency (RF) antenna portions. The heatsink base includes a connector port that provides an interface between components of the computing device and other computing or peripheral devices. For example, the heatsink base may include platform that is configured to have circuitry fixedly secured on a first side of the platform with a connector of the circuitry aligned with an aperture of the connector port such that a connection to the circuitry is accepted by circuitry of another computing device.

Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

Abstract: A method of cancelling interference signals may comprise: receiving, from a transmitting communication node, a first polarization signal including an interference signal and a second polarization signal that is orthogonal to the first polarization signal and includes the interference signal; generating a combined signal by combining the first polarization signal and the second polarization signal using initial combining coefficients; calculating a correlation between the combined signal and one of the first polarization signal and the second polarization signal; selecting final combining coefficients based on the correlation; and generating an output signal by combining the first polarization signal and the second polarization signal using the final combining coefficients.

Abstract: A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.

Abstract: A dynamic specific absorption rate (SAR) may be implemented by monitoring and controlling power utilization of the various radio frequency (RF) emitting components over time within a mobile device. Power utilization may be tracked and modified to control the time-averaged RF exposure over a rolling time window. Periodically calculations of the updated rolling averages for RF transmissions may be performed based on the transmission data received from the mobile device components, and the continuously updated rolling averages of RF transmissions may be compared to time-average power utilization limits. Based on such comparisons, the mobile device may dynamically adjust the current transmissions of the radio transceivers and other RF emitting components on the mobile device.

Abstract: A transceiver circuit includes a counter device, a compensation circuit and an adjusting circuit. The counter device is configured to count an execution time of a reception operation and accordingly generate a counting result. The compensation circuit is coupled to the counter device and configured to receive the counting result, determine a plurality of compensation values according to the counting result and sequentially output the compensation values in a transmission operation. The transmission operation follows the reception operation. The adjusting circuit is coupled to the compensation circuit, and configured to receive the compensation values and sequentially adjust amplitude of a signal according to the compensation values in the transmission operation. The compensation values are respectively applied to different portions of the signal.

Abstract: A cross-division duplex (XDD) system includes an apparatus having a transceiver configured to communicate via an uplink channel and a downlink channel concurrently. The apparatus also includes a transmit antenna, a receive antenna, and a processor. The processor is configured to: estimate a non-linear component corresponding to a transmit path in the transceiver; apply an equalizer function to a received signal; and subtract, in a self-interference cancel (SIC) circuitry, the estimated non-linear component from the equalized signal.

Abstract: According to an embodiment, a communication apparatus creates a prediction model taking into consideration of the actual fluctuation of a self-interference signal. The communication apparatus selects, where the self-interference signal has largely fluctuated, a prediction model in accordance with a fluctuation pattern at an early stage of the fluctuation. The communication apparatus generates a cancel signal by control applying a gain and an amount of phase shift represented by the prediction model.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: an ultra-wideband (UWB) communication unit configured to set up a UWB communication channel with a first external communication device; a further communication unit configured to set up a further communication channel with a second external communication device; an antenna configured to be selectively used by the UWB communication unit and the further communication unit; wherein the UWB communication unit is operatively coupled to the further communication unit, and wherein the further communication unit is configured to grant the UWB communication unit access to said antenna in response to receiving a request from the UWB communication unit. This aspect represents a solution to the problem of how to facilitate avoiding that UWB ranging rounds fail in a co-existence system.

Abstract: Systems and methods for detecting fraud. One method includes providing an input device, the input device having processing circuitry, a memory, and at least one information receiving module for receiving information associated with a user of the input device. The method also includes providing a sensor in electronic communication with the processing circuitry. The sensor has a sensor coil, and the sensor coil is disposed proximate the at least one information receiving module. Further, the method includes flowing alternating electrical current through the sensor coil to generate a magnetic field, measuring at least one electrical characteristic of the sensor, and providing first information representative of the at least one electrical characteristic to the processing circuitry. Finally, the method includes storing in the memory second information representative of at least one predetermined value of the at least one electrical characteristic and comparing the first information with the second information.

Abstract: A method for operating a wireless power transmission system includes providing, a driving signal for driving a transmission antenna. The method further includes receiving, by at least one transistor of an amplifier, the driving signal at a gate of the at least one transistor and inverting a direct current (DC) input power signal to generate an AC wireless signal. The method further includes determining an operating mode for signal damping during transmission or receipt of wireless data signals by selecting one of a switching mode and an activation mode for the operating mode and determining damping signals based on the operating mode. The damping signals are configured for switching the damping transistor to control signal damping during transmission or receipt of wireless data signals. The method further includes selectively damping, by the damping circuit, the AC wireless signals, during transmission of the wireless data signals based on the damping signals.

Abstract: Disclosed herein are a number of embodiments for wireless and non-conductive transfers of power and data to electronic devices. These technological advances can be implemented in retail security products (e.g., merchandising display positions for devices such as smart phones, tablet computers, wearables (e.g., smart watches), digital cameras, etc.) as well as docking systems for tablet computers.

Abstract: The present disclosure relates to electronic device, communication method and storage medium in a wireless communication system. There is provided an electronic device on user device side, comprising a processing circuitry configured to: receive, from a control device, configuration on an association between a first reference signal and a second reference signal; receive, from the control device, an indication for the first reference signal; and in response to the indication for the first reference signal, implement reception of a third reference signal by using spatial reception parameters for the second reference signal based on the association between the first reference signal and the second reference signal.

Abstract: A system, in a radio frequency (RF) transmitter device, selects one or more reflector devices that comprises an active reflector device, along an optimized non-line-of-sight (NLOS) radio path based on a defined criteria. Further, the selected one or more reflector devices are controlled based on one or more conditions. The optimized NLOS radio path is determined from a plurality of NLOS radio paths. In an RF receiver device that communicates with the selected one or more reflector devices using the determined optimized NLOS path. The active reflector device comprises at least a first antenna array and a second antenna array. The first antenna array transmits a first set of beams of RF signals to at least the RF transmitter device and the RF receiver device. The second antenna array receives a second set of beams of RF signals from at least the RF transmitter device and the RF receiver device.

Abstract: A method by which a first wireless device maintains beamforming in a wireless AV system, according to one embodiment of the present invention, comprises the steps of: transmitting a packet including a non-training field and a plurality of training fields to a second wireless device, wherein the non-training field is transmitted on the basis of the best sector combination from among a plurality of candidate sector combinations predetermined between the first wireless device and the second wireless device, and the plurality of training fields is transmitted on the basis of the plurality of candidate sector combinations; receiving candidate beam feedback information as a response to the plurality of training fields; determining, on the basis of the candidate beam feedback information, whether a channel change due to an obstacle occurs; and updating the best sector combination on the basis of the candidate beam feedback information when it is determined that the channel change occurs.

Abstract: Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Abstract: A relay device relaying, to a reception device, a signal stream transmitted by a transmission device through MIMO transmission, the relay device including a lattice base reduction processing unit transforming bases of the signal stream transmitted by the transmission device through MIMO transmission, to increase orthogonality of a lattice of the signal stream, a MIMO equalization unit detecting, by equalization, reception symbols in the signal stream with the bases transformed by the lattice base reduction processing unit, a symbol quantization unit performing quantization by mapping the reception symbols detected by the MIMO equalization unit, to a region on a complex plane delimited by quantization threshold values, and a transmission unit transmitting, to the reception device, at least a signal quantized by the symbol quantization unit.

Abstract: Aspects of the disclosure relate to beam configuration for RF repeaters. An RF repeater is configured to measure received power of one or more signals in the repeater for each of a plurality of beam directions. Further, the repeater determines a beam forming configuration for a fronthaul link between the repeater and at least one base station based on the measured received power of each of plurality of beam directions. The repeater may also be configured to determine beam configurations for access links between the repeater and user equipment.

Abstract: Disclosed is a precoding method comprising the steps of: generating a first coded block and a second coded block with use of a predetermined error correction block coding scheme; generating a first precoded signal z1 and a second precoded signal z2 by performing a precoding process, which corresponds to a matrix selected from among the N matrices F[i], on a first baseband signal s1 generated from the first coded block and a second baseband signal s2 generated from the second coded block, respectively; the first precoded signal z1 and the second precoded signal z2 satisfying (z1, z2)T=F[i] (s1, s2)T; and changing both of or one of a power of the first precoded signal z1 and a power of the second precoded signal z2, such that an average power of the first precoded signal z1 is less than an average power of the second precoded signal z2.

Abstract: Systems and methods are disclosed herein for determining a power to be used for a set of antenna ports for a physical uplink shared channel transmission. In some embodiments, a User Equipment (UE) comprises processing circuitry configured to derive a power P to be used for uplink power control for a physical uplink shared channel transmission and determine a power to be used for a set of antenna ports based on the power P according to a rule that depends on whether the UE is utilizing codebook based transmission or non-codebook based transmission for the physical uplink shared channel transmission. The set of antenna ports is antenna ports on which the physical uplink shared channel transmission is transmitted with non-zero power.

Abstract: A design for reference signals dedicated for positioning measurements in UL and DL directions and a mechanism for Tx/Rx beam pair selection for positioning is disclosed. The design can improve performance of positioning operation in NR communication systems, can improve resource efficiency of positioning operation in NR communication systems, and can reduce the amount of resources needed for PRS transmission, reduce latency and increase the positioning measurement quality.