Abstract: The disclosure relates to an autonomous apparatus, moving and performing preset work in a defined working area, the autonomous apparatus including an energy module supplying energy to the autonomous apparatus, a motor, a sensor circuit, and a control circuit, the motor obtaining the energy from the energy module, to drive the autonomous apparatus to move and/or work in the working area, the sensor circuit detecting working parameters and environmental parameters of the autonomous apparatus, and transmitting detection results to the control circuit, the control circuit controlling the operation of the motor according to a signal transmitted by the sensor circuit, where the motor is a sensorless brushless motor, and before the motor rotates, the control circuit measures a resistance value of the motor, and estimates, one the basis of the resistance value of the motor, a rotor position of the motor, so as to control the operation of the motor.

Abstract: A method and apparatus for estimating a rotor position of a motor, and a motor control system. The method includes: obtaining a position error signal by injecting a high-frequency signal into a stator winding of the motor; obtaining a load parameter indicating a load of the motor, obtaining a direct-current component disturbance value according to the load parameter and a first preset relationship, obtaining a harmonic component disturbance value according to the load parameter and a second preset relationship, and obtaining an observer parameter value according to the load parameter and a third preset relationship; compensating the position error signal according to the direct-current component disturbance value and the harmonic component disturbance value to obtain a compensated position error signal; adjusting an observer parameter according to the observer parameter value, and adjusting the compensated position error signal through an adjusted observer to obtain the rotor position and a rotor speed.

Abstract: An electric machine is provided. A polyphase machine is provided. A power inverter is electrically connected to the polyphase machine. A controller is electrically connected to the power inverter, wherein the controller provides switching signals to the power inverter, wherein the controller comprises a trajectory calculator that provides an optimized trajectory for transitioning the polyphase machine from a first torque to a second torque.

Abstract: In a method for monitoring the operation of an electric motor and a lifting mechanism, the motor current is acquired, and the electric motor has, for example, an electromagnetically actuable brake, e.g., a holding brake. In the method, a pre-magnetization is performed when the electric motor is switched on, the characteristic of the acquired values of the motor current is monitored for an exceeding of a permissible measure of deviation from a setpoint characteristic, and a brake of the electric motor is activated, e.g., remains applied.

Abstract: Systems and methods for determining proper phase rotation in a linear motor that may be used in an ESP system, where the phase rotations associated with power and return strokes are initially unknown. The method includes providing power to the motor for multiple cycles and monitoring the load (e.g., by monitoring current drawn by the motor) on the motor to determine in which direction (phase rotation) the load on the motor increases. This direction corresponds to the power stroke of the motor. The direction of increasing load is then associated with the power stroke and the motor is operated normally.

Abstract: A motor/generator/transmission system includes: an axle; a stator ring having a plurality of stator coils disposed around the periphery of the stator ring, wherein each phase of the plurality of stator coils includes a respective set of multiple parallel non-twisted wires separated at the center tap with electronic switches for connecting the parallel non-twisted wires of each phase of the stator coils all in series, all in parallel, or in a combination of series and parallel; a rotor support structure coupled to the axle; a first rotor ring and a second rotor ring each having an axis of rotation coincident with the axis of rotation of the axle, at least one of the first rotor ring or the second rotor ring being slidably coupled to the rotor support structure and configured to translate along the rotor support structure in a first axial direction or in a second axial direction.

Abstract: The invention relates to a method for the external monitoring of a converter (10), the converter (10) being controlled by means of a first electronic control system (12) and the method being implemented by means of a second electronic control system (14) which is independent from the first electronic control system (12). Said method comprises detection (S1) of a current (I) received by the converter (10) and a voltage (U) received by the converter (10) by means of a current/voltage sensor device (16) which is independent from the first electronic control system (12). The invention also relates to a device for monitoring a converter (10), to a computer program product, to a machine-readable storage medium, to a drive train of a motor vehicle, and to a corresponding motor vehicle.

Abstract: Provided are a short circuit state analyzer to compare difference value when the AC excitation current is applied at a first frequency with a threshold value, to estimate a short circuit resistance from the difference value based on data indicating a relationship between the short circuit resistance and the difference value at the first frequency when the difference value is smaller than the threshold value, to cause an excitation power supply to apply the AC excitation current to the field windings at a second frequency lower than the first frequency when the difference value is equal to or greater than the threshold value, and to estimate the short circuit resistance from a difference value obtained by the AC excitation current at the second frequency based on data indicating a relationship between the short circuit resistance and the difference value at the second frequency.

Abstract: The present disclosure relates to a day-night photovoltaic system. More specifically, power supplied to a solar panel from a DC power supply part is output as a final output power PV together with power produced by the solar panel during the daytime, and is output as the final output power together with an ultra-high frequency wavelength generated by the sun explosion and induced to the solar panel during the night time. This provides the effects of stably supplying the power not only during the daytime but also during the night time.

Abstract: A modular power supply apparatus for use in harsh climates that comprises a portable, low cost, easily maintained, durable power supply for energy production as well as systems, methods for forming, and methods of using same.

Abstract: Surface mount assembly for mounting to a solar panel frame to an installation surface is disclosed. In some embodiments, a surface mount assembly includes a base and an enclosure. The base includes a lower member and an upper member. The lower member could include a brace, a center aperture extending through the lower and upper members for receiving a fastener to facilitate the mounting to a solar panel frame; the upper member could include a hub from which a plurality of arms may extend. The mount enclosure could include a chamber with a chamber aperture for receiving a fastener from the surface mount, a post support extending upward from the chamber and forming a post aperture for receiving a post, and a horizontal member with one or more sealant grooves extending horizontal outward from the chamber.

Abstract: Solar tracker systems include a torque tube, a column supporting the torque tube, a solar panel connected to the torque tube, and a locking assembly. The locking assembly includes a first end pivotably connected to the torque tube and a second end pivotably connected to the column. A shell defines a fluid chamber and a piston is positioned within the shell. The piston includes a seal and defines compression and extension portions of the fluid chamber. A flow path extends between the compression portion and the extension portions. A first valve assembly controls fluid flow in a first direction through the flow path and a second valve assembly controls fluid flow in a second direction through the flow path. The valve assemblies are each passively moveable from an unlocked state to a locked state in response to movement of the piston.

Abstract: A junction box used for making electrical connections to a photovoltaic panel. The junction box has two chambers including a first chamber and a second chamber and a wall common to and separating both chambers. The wall may be adapted to have an electrical connection therethrough. The two lids are adapted to seal respectively the two chambers. The two lids are on opposite sides of the junction box relative to the photovoltaic panel. The two lids may be attachable using different sealing processes to a different level of hermeticity. The first chamber may be adapted to receive a circuit board for electrical power conversion. The junction box may include supports for mounting a printed circuit board in the first chamber. The second chamber is configured for electrical connection to the photovoltaic panel. A metal heat sink may be bonded inside the first chamber.

Abstract: Apparatus and methods for generating multiple oscillating signals. An example circuit generally includes a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors comprising a first transistor and a second transistor, a first inductive element coupled between a first node and the drain of the first transistor, a second inductive element coupled between the first node and the drain of the second transistor, a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node, and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

Abstract: One example includes a differential amplifier, a voltage weighting element, coupled to a voltage source which provides an input voltage, to provide a reference voltage with a constant power limit when the input voltage varies, an error amplifier configured to receive and compare the reference voltage provided from the voltage weighting element and a feedback sensed voltage provided from the differential amplifier to identify whether the sensed voltage exceeds the reference voltage, and a pulse width modulation (PWM) controller, coupled to a power transformer and the error amplifier, that reduces a transformer input current provided to the power transformer based on the comparison of the reference voltage from the voltage weighting element and the feedback sensed voltage from the differential amplifier.

Abstract: A method for a fast settling ripple reduction loop for high speed precision chopper amplifiers includes amplifying an input signal with a signal path to generate a first output, the signal path comprising chopping the input signal to generate a first chopper output, amplifying the first chopper output with an amplifier to generate an amplifier output and chopping the amplified output to generate a second chopper output. An output ripple of the first output is reduced with a Ripple Reduction Loop comprising chopping the second chopper output to generate a third chopper output, filtering the third chopper output with a filter to generate a Direct Current (DC) offset correction, and combining the DC offset correction with the amplifier output, wherein the third chopper output is driven to the output voltage of the filter and the RRL is disconnected from the low frequency signal path in response to a non-linear event.

Abstract: An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Abstract: A phase-synchronized RF power generator includes: an RF power amplifier for amplifying an RF power signal; a first directional coupler; an isolator for adjusting impedance mismatch generated by the first directional coupler, and transferring the RF power signal transferred by the first directional coupler to the output terminal; a second directional coupler for transferring part of the feedback signal transferred by the first directional coupler to be compared with a frequency of a reference signal provided by a crystal oscillator, and transferring rest of the feedback signal to a feedback loop; a digital phase shifter for adjusting a phase of the feedback signal transferred by the second directional coupler at predetermined intervals; an analog phase shifter for continuously adjusting the phase of the feedback signal discretely adjusted by the digital phase shifter; and a frequency comparator.

Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: An electronic device and method that automatically adjusts an audio output volume level based on a live environmental acoustic scenario input via a microphone using a machine learning algorithm trained with Human Activity Recognition (HAR). Equipped with such an intelligence the electronic device classifies ambient sounds occurring in the environment of the listening area in which the device is situated into different acoustic scenario mappings such a voice or conversation, for an ambient human conversation detected event, and noise, such as for example a vacuum cleaner or dish washer noise detected event, and automatically adjust the audio output volume accordingly.

Abstract: Dynamic automatic gain controller configuration in multiple input and multiple output receivers is provided by monitoring a given section of wireless spectrum for higher-priority signals using a first antenna set associated with a first Automatic Gain Controller (AGC) set while concurrently monitoring the given section of wireless spectrum for wireless packet-based traffic using a second antenna set associated with a second AGC set; in response to detecting a packet via the second antenna set: re-associating the first antenna set and the second antenna set to a third AGC set; receiving the packet via the first antenna set and the second antenna set using the third AGC set; and in response to the packet being received, re-associating the first antenna set to the first AGC set and the second antenna set to the second AGC set.

Abstract: A system comprising audio processing circuitry is provided. The audio processing circuitry is operable to receive audio signals. The audio processing circuitry is operable to process the audio signals to detect strength of a chat component of the audio signals and strength of a game component of the audio signals. The audio processing circuitry is operable to automatically control a volume setting based on one or both of: the detected strength of the chat component, and the detected strength of the game component. The combined-game-and-chat audio signals may comprise a left channel signal and a right channel signal. The processing of the combined-game-and-chat audio signals may comprise measuring strength of a vocal-band signal component that is common to the left channel signal and the right channel signal.

Abstract: A method includes depositing a first metal layer on a semiconductor substrate; etching the first metal layer to form a first electrode having a first lead; depositing a piezoelectric layer on the semiconductor substrate and first electrode; etching the piezoelectric layer to a shape of the gyrator to be formed within the circulator; depositing a second metal layer on the piezoelectric layer; etching the second metal layer to form a second electrode having a second lead, the second electrode being positioned opposite the first electrode, wherein the first lead and the second lead form an electrical port; depositing a magnetostrictive layer on the second electrode; etching the magnetostrictive layer to approximately the shape of the piezoelectric layer; depositing a third metal layer on the magnetostrictive layer; and etching the third metal layer to form a metal coil that has a gap on one side to define a magnetic port.

Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.

Abstract: A micro-electrical-mechanical system (MEMS) resonator device includes at least one functionalization material arranged over at least a central portion, but less than an entirety, of a top side electrode. For an active region exhibiting greatest sensitivity at a center point and reduced sensitivity along its periphery, omitting functionalization material over at least one peripheral portion of a resonator active region prevents analyte binding in regions of lowest sensitivity. The at least one functionalization material extends a maximum length in a range of from about 20% to about 95% of an active area length and extends a maximum width in a range of from about 50% to 100% of an active area width. Methods for fabricating MEMS resonator devices are also provided.

Abstract: A bulk-acoustic wave resonator comprises a substrate, a resonant portion comprising a first electrode, a piezoelectric layer, and a second electrode sequentially stacked on the substrate, and further comprising a center portion and an extension portion that is disposed along a periphery of the center portion, and an insertion layer that is disposed in the extension portion between the first electrode and the piezoelectric layer, and the insertion layer is formed of an aluminum alloy containing scandium (Sc).

Abstract: A solidly mounted resonator having an electromagnetic shielding structure and a method for manufacturing the same. The solidly mounted resonator includes: a substrate; an acoustic-wave reflecting layer formed on the substrate; a resonance function layer formed on the acoustic-wave reflecting layer; and a metal shielding wall formed on the substrate, wherein the metal shielding wall surrounds an effective region in the acoustic-wave reflecting layer and the resonance function layer. The electromagnetic shielding structure is formed simultaneously with the resonator, and it is not necessary to provide an additional electromagnetic shielding device. An influence of an external or internal electromagnetic interference source on the resonator is avoided while ensuring a small dimension and a high performance of the resonator.

Abstract: The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.

Abstract: An elastic wave device includes an IDT electrode on a second main surface of an element substrate that includes a piezoelectric layer, a support layer on the second main surface and surrounding the IDT electrode, a cover member on the support layer, and routing wiring lines extending from the second main surface of the element substrate onto side surfaces of the element substrate.

Abstract: An acoustic wave device includes an element substrate having piezoelectricity, a functional electrode on a first main surface of the element substrate, an extended wiring line electrically connected to the functional electrode and extending from the first main surface to a side surface of the element substrate, an external terminal electrically connected to the extended wiring line and on a second main surface of the element substrate, a first resin portion to seal the acoustic wave device, and a second resin portion at least between the extended wiring line on the side surface and the first resin portion. The second resin portion has a lower Young's modulus than the first resin portion.

Abstract: A resonator circuit device. This device can include a piezoelectric layer having a front-side electrode and a back-side electrode spatially configured on opposite sides of the piezoelectric layer. Each electrode has a connection region and a resonator region. Each electrode also includes a partial mass-loaded structure configured within a vicinity of its connection region. The front-side electrode and the back-side electrode are spatially configured in an anti-symmetrical manner with the resonator regions of both electrodes at least partially overlapping and the first and second connection regions on opposing sides. This configuration provides a symmetric acoustic impedance profile for improved Q factor and can reduce the issues of misalignment or unbalanced boundary conditions associated with conventional single mass-loaded perimeter configurations.

Abstract: According to one embodiment, in a biquad filter, an output terminal of a first integrator is connected to an input terminal in a negative pole side of a second integrator, an output terminal of the first integrator is connected to a first input terminal in a negative pole side of an adder through the inversion amplifier, an output terminal of the second integrator is connected to a second input terminal in the negative pole side of the adder, an input terminal to which an input signal is input is connected to a third input terminal in the negative side of the adder, and an output terminal of the adder is connected to an input terminal in a negative pole side of the first integrator.

Abstract: According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

Abstract: A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.

Abstract: A circuit, for generating ultrahigh-precision digital pulse signals comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.

Abstract: Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

Abstract: A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

Abstract: The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: System and method for controlling one or more light emitting diodes. For example, the system for controlling one or more light emitting diodes includes a current generator configured to generate a first current flowing through one or more light emitting diodes. The one or more light emitting diodes are configured to receive a rectified voltage generated by a rectifying bridge coupled to a TRIAC dimmer. Additionally, the system includes a bleeder configured to receive the rectified voltage, and a controller configured to receive a sensing voltage from the current generator and output a control signal to the bleeder. The sensing voltage indicates a magnitude of the first current.

Abstract: An apparatus includes a first leg having a plurality of transistors connected in series between a first node and a second node. Each of the plurality of transistors includes a respective body diode. The apparatus further includes a second leg connected between the first node and the second node and in parallel to the series connection of the plurality of transistors of the first leg. The second leg includes a first transistor. The second leg has lower reverse recovery losses relative to the first leg.

Abstract: According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.

Abstract: Systems, methods, techniques and apparatuses of a semiconductor control system are disclosed. One exemplary embodiment is a method for protecting a semiconductor switch comprising receiving a first voltage during a second blanking period following a first blanking period; determining whether a short circuit fault is occurring by comparing the first voltage to a fast detection threshold corresponding to a first value of a drain-source voltage of the semiconductor switch; if a short circuit is not occurring: receiving a second voltage after the second blanking period ends; determining whether a short circuit fault is occurring by comparing the second voltage to a slow detection threshold corresponding to a second value of the drain-source voltage; and if a short circuit fault is occurring, opening the semiconductor switch, wherein the first value of the drain-source voltage is greater than the second value of the drain-source voltage.

Abstract: An overcurrent protection circuit configured to limit an output current flowing through an output transistor includes a sense transistor that provides a sense current proportional to the output current, a sense resistor through which the sense current flows, a current limiting circuit that detects a sense voltage generated by the sense resistor and controls a gate voltage of the output transistor, and a current correction circuit that provides the sense resistor with a corrected sense current added to the sense current based on a difference of voltage between a drain voltage of the output transistor and a drain voltage of the sense transistor.

Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.

Abstract: A method includes detecting a signal on a switching node connected to a power switch, detecting a gate drive voltage of the power switch, during a gate drive process of the power switch, reducing a gate drive current based on a first comparison result obtained from comparing the signal with a first threshold, and during the gate drive process of the power switch, increasing the gate drive current based on a second comparison result obtained from comparing the gate drive voltage with a second threshold.

Abstract: A drive circuit of a power semiconductor element comprises a gate drive voltage generator to generate, based on an ON/OFF drive timing signal input to an input terminal, a gate drive voltage to be applied to a gate electrode of a switching element having the gate electrode for controlling a main current that flows between a first main electrode and a second main electrode, wherein the gate drive voltage generator includes a gate current limiting circuit in which a current limiter to limit a current and a voltage limiter to limit the magnitude of a voltage applied to both ends of the current limiter are connected in parallel.