Abstract: A power distribution unit (PDU) comprises a housing, an input on the housing, and an input connector coupled to the input on the housing. The input connector is connectable to a power source that provides power for distribution by the PDU to one or more power consuming devices. The PDU includes an output including output connectors that provide blind-mate connection with a connection interface coupled to the one or more power consuming devices.

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

Abstract: A computing equipment box assembly can include a mechanical chassis component, which can include a support sheet configured for supporting computing components. A plurality of passages can be formed through the support sheet. A mechanical cable can be routable down through at least one of the passages and up through at least one other of the passages. A tensioner can be couplable with the cable and adjustable to modify an amount of tension in the cable so as to alter an amount of pre-bow or pre-bend present in the mechanical chassis component. For example, the mechanical cable may be tensioned to apply a force to the support sheet and counteract an upward pre-bend or pre-bow so that the computing components are prevented from protruding into an adjacent upper volume for an upper computer server overhead and from sagging into an adjacent lower volume for a lower computer server underneath.

Abstract: An expansion bay for a computer system having a rotatable fastening mechanism is disclosed. The expansion bay includes a bay housing having two facing side walls, a front open end and a bottom panel. A front tab and a rear tab extend from the interior of one of the side walls. A tray supporting an expansion component has a guide block with a threaded aperture. The tray may be positioned between an open position and a closed position. The rotatable fastener mechanism moves the tray into and out of the bay housing. A rod is inserted through apertures of the first tab and the second tab, allowing free rotation of the rod. The rod includes a threaded exterior section to rotationally engage the threaded aperture of the guide block. A knob is attached to an end of the rod to allow a user to rotate the rod and move the tray.

Abstract: A head-mountable device can provide a cooling module that effectively manages heat while also minimizing noise, vibration, leakage, power consumption, size, and weight. To dissipate heat, the cooling module with a fan can be operated to move air through a chamber within the head-mountable device. An integrated heat sink can provide heat dissipation properties by drawing heat away from heat-generating components and into the chamber. The integrated heat sink can include a base plate that defines at least a portion of the chamber in which the blades of the fan are positioned. The integrated heat sink can further include fins between the chamber and an outlet. The fins can be integrated with the base plate to maximize heat dissipation and reduce the number of interfaces between separate parts.

Abstract: The cooling module comprises a main supply connector, a main return connector, an internal cooling loop, a plurality of cooling plates, a base layer and a lid. The base layer includes a plurality of supply sub-connectors and return sub-connectors and a plurality of cooling areas corresponding to a plurality of cooling plates. Each cooling plate has a supply connector, a return connector and a contacting area. The plurality of supply sub-connectors and return sub-connectors are connected with the internal cooling loop. Each cooling area is to contact with a contacting area of a corresponding cooling plate. Each supply sub-connector is to be connected to a supply connector of the corresponding cooling plate, and each return sub-connector is to be connected to a return connector of the corresponding cooling plate. The corresponding cooling plate is to be removably attached with the base layer and to be serviced independently.

Abstract: A electronic device includes: a plurality of substrates each including a substrate main body and a heat generating element, the plurality of substrates being provided side by side in a plate thickness direction; a cooler which is provided between the substrates adjacent to each other, and configured to cool the heat generating element; and a piping which is made of metal, and is connected to the cooler. The piping includes: an inner piping portion which is arranged in an inter-substrate region, and is connected to the cooler; an inner piping extending portion provided so as to extend from the inner piping portion to an outer side of the inter-substrate region; and an outer piping portion which is arranged to be shifted from the inter-substrate region, and is connected to the inner piping extending portion. The outer piping portion includes a movable piping portion that is deformable.

Abstract: An enclosure for providing liquid film cooling to heat generating components includes a chassis, a sump, a first pump, a plumbing system, tube plates, and a heat exchanger. The chassis includes cassettes that hold one or more heat generating components. The sump stores a liquid to be supplied to the heat generating components. The first pump draws the liquid from the sump and supplies the liquid to the tube plates through the plumbing system. Each tube plate is positioned between two cassettes to deliver the liquid to the heat generating components. The tube plates directly spray the liquid onto the heat generating components by way of nozzles embedded on the tube plates. The liquid is evaporated into vapors upon contact with the plurality of heat generating components. The heat exchanger condenses the vapors into condensed liquid upon contact. The condensed liquid is collected in the sump to be re-circulated.

Abstract: An electronic apparatus with convenient airflow-reversing function includes a chassis, a rotation mechanism, a fan device, a connection rod, and a handle. The chassis includes a bottom plate. The rotation mechanism is pivoted on the bottom plate. The fan device is disposed on the rotation mechanism. The connection rod is pivoted on the rotation mechanism. The handle is pivoted on the chassis, and is rotatably connected to the connection rod. When the handle is rotated, the connection rod drives the rotation mechanism and the fan device to rotate to change the airflow direction.

Abstract: This disclosure is directed to, in one aspect, a thermal management system for a data center. The thermal management system can include an air to air heat exchanger operable in a dry mode and a wet mode. The thermal management system can also include a liquid to air heat exchanger. The liquid to air heat exchanger can have a coil that receives the cooling liquid, with the coil being positioned in communication with the air of the data center such that the cooling liquid can absorb heat therefrom. Still further, the thermal management system can include a direct expansion cooling loop with a condenser and an evaporator. The system further provides multiple combinational operating conditions among multiple cooling modes. Other aspects are described.

Abstract: A thermal management module includes a fluid system in fluid communication with a main cooling fluid source; a first cooling fluid manifold, and a second cooling fluid manifold. The first cooling fluid manifold is in fluid communication with the fluid system and provides a cooling fluid between the fluid system and a first server rack adjacent to the thermal management module. The second cooling fluid manifold is in fluid communication with the fluid system and provides the cooling fluid between the fluid system and a second server rack adjacent to the thermal management module. The manifold is in internal position when no rack liquid is needed adjacently, and it is extended to the adjacent rack once fluid distribution is needed from the rack.

Abstract: A chassis-mounted electronic device includes a conductive chassis, an upper EMI gasket, and a lower EMI gasket. An upper chassis and a lower chassis of the conductive chassis are coupled to form an interior of the chassis housing an electronic device. The upper EMI gasket is attached to the upper chassis, and resiliently contacts a portion of the electronic device. The lower EMI gasket is attached to the lower chassis, and resiliently contacts a different portion of the electronic device. The upper and lower EMI gaskets include perforations to allow cooling air through the EMI gaskets and into the interior of the chassis. The conductive chassis, the upper EMI gasket, and the lower EMI gasket provide EMI shielding for the electronic device.

Abstract: Disclosed is an electromagnetic shielding film, including a supporting layer and N conductive layers. The supporting layer has a first side surface and a second side surface arranged oppositely, the N conductive layers are stacked on at least one of the first side surface and the second side surface, and N?2. Each of the N conductive layers includes a conductive grid, the conductive grid includes a conductive material filled in a grid-shaped trench, and at least two of the N conductive layers have conductive materials for shielding different bands, respectively. Different conductive layers have different conductive materials, and therefore can shield different bands, thereby broadening a shielding band of the electromagnetic shielding film, which can better meeting market demands.

Abstract: A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions.

Abstract: A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes forming multiple openings in staircase regions, periphery device regions, and substrate contact regions of a 3D NAND memory device. The openings can be formed by a photolithography process followed by multiple etching processes. The openings can include complete openings that expose the underlying layer and mid-way openings where a remaining portion of the photoresist still exists between the opening and the underlying layer. The remaining portion of the photoresist can delay the etching process in the shorter openings for the upper level staircase structure during the formation of the deeper openings for the lower level staircase structure. Conductive material is deposited into the openings to form contact structures for structures such as substrate contact pads, upper and lower level staircase structures, and/or peripheral devices.

Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

Abstract: A semiconductor device includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes, which are alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern between the substrate and the gate structure. The source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern. The channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern. A lower surface of the channel pattern is at a level higher than an upper surface of the upper source conductive pattern, but lower than a lower surface of a lowermost one of the gate electrodes in a cross-sectional view of the semiconductor device with the substrate providing a base reference level.

Abstract: Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions.

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.

Abstract: A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

Abstract: Electrically formed memory arrays, and methods of processing the same are described herein. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a first plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, a storage element material formed around each respective one of the first plurality of conductive extensions, a second plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a plurality of single element materials formed around each respective one of the second plurality of conductive extensions.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: Embodiments of the disclosed subject matter provide a full-color pixel arrangement for a full-color display is provided, the arrangement having a plurality of pixels, with each pixel including a first sub-pixel comprising a Group III-V inorganic emissive thin film configured to emit light of a first color, where there is at least one first sub-pixel per pixel of the full-color pixel arrangement. Each pixel may include an organic second sub-pixel and an organic third sub-pixel that are configured to emit light of a different color than the first color.

Abstract: An organic optoelectronic device comprises a substrate having first and second regions, a first electrode positioned over the first region of the substrate, a shutter electrode positioned over the second region of the substrate, an organic heterojunction layer comprising an organic heterojunction material, positioned over at least a portion of the first electrode, an insulator layer positioned over at least a portion of the shutter electrode, an organic channel layer, comprising an organic channel material, positioned over at least a portion of the heterojunction and insulator layers, and a second electrode positioned over the channel layer in the second region of the substrate, wherein the shutter electrode is configured to generate a repulsive potential barrier in the channel layer, suitable to at least reduce movement of charge in the channel layer. A method of measuring received light in an optoelectronic device is also described.

Abstract: An organic electric element, a display panel and a display device including the organic electric element are provided. The organic electric element includes a first electrode; a second electrode; and an organic layer positioned between the first electrode and the second electrode. The organic layer includes a first layer having a first compound and a second compound, and a emitting layer having a third compound. A specific general formula related to energy levels of the component compounds is satisfied so that they may have excellent efficiency or lifespan.

Abstract: A display panel and a method of manufacturing thereof are provided. A hole injection layer, a hole transport layer, a light emitting layer, and a planarization layer are formed by an inkjet-printing method. Specifically, solvents including hole injecting layer material, hole transporting layer material, light emitting layer material, and planarization layer material are evaporated by vacuum drying so as to uniformize the surface of the entire layer, thereby improving light uniformity. Moreover, a notch of the light emitting layer can be effectively filled by disposing a planarization layer on the light emitting layer, so a uniform layer can be formed, which can reduce the current accumulated at the notch. Therefore, the light uniformity of the display panel is improved, and the risk of leakage current at the notch is also reduced.

Abstract: The present disclosure generally pertains to methods of preparing a well-ordered nanoparticle coating on a substrate. A nanoparticle solution having nanoparticles in a solvent is deposited on a sub-phase of a denser, immiscible liquid. A constrained area on the top surface of the sub-phase is provided, where nanoparticle solution spreading is physically limited and the nanoparticles spontaneously form a uniformly ordered monolayer on the sub-phase within the constrained area. Notably, no compression of the nanoparticle film occurs after the spreading phase in order to form the monolayer. After the monolayer is formed, a substrate is placed into contact with the monolayer and coated with a well-ordered nanoparticle coating.

Abstract: An organic light emitting display apparatus can include an insulating film disposed on a substrate, a first electrode disposed on the insulating film, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer, wherein the first electrode can be provided with a contact area that covers a contact hole passing through the insulating film, and a protrusion vertically protruded from an upper surface of the first electrode on a boundary surface of the contact hole.

Abstract: A display device includes a substrate including a display area and a pad area, a lower electrode, a light emitting layer, an upper electrode on the light emitting layer, and a pad electrode in the pad area. The lower electrode is in the display area, the lower electrode including a first electrode, a second electrode, and a third electrode. The first electrode has a first etching rate with respect to an etching process. The second electrode is on the first electrode. The second electrode has a second etching rate with respect to the etching process that is higher than the first etching rate. The third electrode is on the second electrode. The third electrode has a third etching rate with respect to the etching process that is lower than the second etching rate and higher than the first etching rate. The light emitting layer is over the first electrode.

Abstract: Disclosed relates to a transparent display panel and manufacturing method of thereof, and the transparent display panel including a patterned cathode with improved transparency as a whole.

Abstract: The present disclosure provides a light emitting diode, a method of preparing the same, and a display device. The light emitting diode includes an anode, a quantum dot light emitting layer, an electron transport layer, a cathode, and a transition layer located between the electron transport layer and the cathode, the cathode including a transparent conductive oxide material, and a material of the transition layer having a work function WF between an LUMO of a material of the electron transport layer and a work function WF of a material of the cathode.

Abstract: The present disclosure provides a display device and a method for manufacturing the same. The display device includes a display substrate; a first cover plate on a side of the display substrate; at least one support layer on a side of the first cover plate distal to the display substrate. The support layer includes a support structure and a second cover plate. The second cover plate is on a side of the first cover plate distal to the display substrate, and the support structure is configured to support the second cover plate.

Abstract: Disclosed are a display panel, a manufacturing method thereof, and a displaying device. The display panel comprises a pixel layer, a support layer, a lens unit and a cover plate which are stacked in sequence. The support layer is located on a luminescent layer of the pixel layer. The lens unit comprises a lens layer, wherein the lens layer comprises a lens area and a non-lens area, and the lens area comprises multiple lenses arranged in an array. The display panel further comprises a polarization unit disposed on a light path between the pixel layer and the lens layer and configured to filter out light emitted from the pixel layer to the non-lens area.

Abstract: The present disclosure provides a display panel, a display device and a display method. The display panel includes a base substrate, and an organic electroluminescent device layer, a detection sensor and a color switchable structure which are successively located on the base substrate and are insulated from each other, where the organic electroluminescent device layer includes a plurality of sub-pixels, and the color switchable structure includes sub-units disposed in one-to-one correspondence with the sub-pixels; the sub-units are configured to transmit light emitted by the sub-pixels under the control of applied different signals, or to display light of colors corresponding to the applied signals; and the detection sensor is configured to detect display parameters of the sub-pixels or the sub-units.