Abstract: Intelligent collection and analysis of in-app failure data is disclosed herein. Upon an application failure in a client device, the client device may collect failure information uniquely identifying a specific failure and provide the failure information to an analysis system. The analysis system may identify a specific failure that identifies the application and a specific portion of the code in the application, based on the failure information and match an action correlated to the specific failure where the action is uniquely designed to resolve the specific failure in the application. The action may include instructions for the client device used to intelligently lead to a resolution of the specific failure. The analysis system may transmit the action to the client device to perform the action and provide any follow up information to the analysis server. The analysis server may use the information to further analyze the specific failure.

Abstract: Embodiments of the present disclosure provide systems, methods, and computer-readable storage media that leverage artificial intelligence and machine learning to identify, diagnose, and mitigate occurrences of network faults or incidents within a network. Historical network incidents may be used to generate a model that may be used to evaluate real-time occurring network incidents, such as to identify a cause of the network incident. Clustering algorithms may be used to identify portions of the model that share similarities with a network incident and then actions taken to resolve similar network incidents in the past may be identified and proposed as candidate actions that may be executed to resolve the cause of the network incident. Execution of the candidate actions may be performed under control of a user or automatically based on execution criteria and the configuration of the fault mitigation system.

Abstract: A troubleshooting technique provides faster and more efficient troubleshooting of issues in a distributed system, such as a distributed storage system provided by a virtualized computing environment. The distributed system includes a plurality of hosts arranged in a cluster. The troubleshooting technique uses cluster-wide correlation analysis to identify potential causes of a particular issue in the distributed system, and executes workflows to remedy the particular issue.

Abstract: A processor may analyze a specific area. The processor may determine whether a threshold number of attempts to perform an action by a device has been exceeded. The processor may activate one or more scanning devices. The processor may record an attempt to perform the action. The processor may automatically provide a repair for a failure attempt. The repair may allow the device to not subsequently exceed the threshold.

Abstract: The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.

Abstract: Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.

Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

Abstract: An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.

Abstract: In one implementation, storage system includes embedded storage devices, where each embedded storage device includes a direct-mapped solid state drive (SSD) storage portion and storage system controllers. The storage system controllers may be operatively coupled to the embedded storage devices via a bus. The storage system controllers may receive data to be written to the plurality embedded storage devices, select a plurality of available allocation units from the direct-mapped SSD storage portions of the plurality of embedded storage devices, respectively, and calculate a verification signature corresponding to the data. The storage system controllers may also write the data and the verification signature to a first subset of the plurality of available allocation units, calculate an erasure code corresponding to the data and the verification signature, and write the erasure code to a second subset of allocation units.

Abstract: Several embodiments of systems incorporating memory components are disclosed herein. In one embodiment, a memory system can include a memory component and a processing device configured to access quality metrics corresponding to memory regions of the memory component. In some embodiments, the processing device can compare the quality metrics to one or more memory management thresholds. In some embodiments, when the quality metrics meet and/or exceed a first threshold, a refresh operation can be scheduled and/or performed on a corresponding memory region. In these and other embodiments, when the quality metrics meet and/or exceed a second threshold, the memory region is retired and removed from an active pool of memory regions.

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.

Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.

Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: A method of performing partial redundant array of independent disks (RAID) stripe parity calculations is disclosed. The method includes receiving a last portion of a RAID stripe among multiple portions of the RAID stripe, all portions for a successful write of the RAID stripe being previously received except for the last portion. The method also includes calculating a parity value based on the last portion of the RAID stripe and a previous parity value without calculating the parity value using a previous portion of the RAID stripe. The method further includes writing of the RAID stripe.

Abstract: Apparatus for tiered storage of data in a storage network. In an example of operation, a computing device receives a data object for storage and forwards the data object for storage in a first plurality of memory devices of a first memory type. The computing device determines a system level storage efficiency for the data object based, at least in part, on a data attribute associated with the data object. The computing device further selects, based at least in part on the system level storage efficiency preference, a second plurality of memory devices comprised of a second memory type. The computing device determines error encoding parameters based on the second plurality of memory devices, retrieves the data object from the first plurality of memory devices, and encodes the data object with the error encoding parameters to generate a plurality of encoded data slices for storage in the second plurality of memory devices.

Abstract: A method for execution by a computing device of a storage network includes determining an encoded data slice reduction scheme for a set of encoded data slices stored in a set of storage units of the storage network, where a data segment of data is encoded into the set of encoded data slices in accordance with encoding parameters, and where the encoding parameters include a pillar width number and a decode threshold number. The method further includes maintaining storage of the set of encoded data slices in accordance with the encoded data slice reduction scheme, where the maintaining storage includes keeping a number of encoded data slices of the set of encoded data slices equal to or greater than the decode threshold number and less than the pillar width number.

Abstract: Apparatus and methods an artificial intelligence method of reducing failure in an informational flow of a data stream controlled by an Extract Transform Load process using a machine learning (“ML”) model training system are provided. The method may include deploying a software sensor that periodically captures data points for an extract job executed during an extract phase of the process. The method may also include building a behavior profile concurrently with the receipt of each of the data points. The method may further include comparing the behavior profile to behavior profiles stored in an Adverse Behavior Model database and behavior profiles stored in a Normal Behavior Model database. When the behavior profile is determined to have a threshold number of match points matching the behavior profile to behavior profiles in the Adverse Behavior Model database, the method may include increasing a target database storage capacity.

Abstract: An example memory sub-system includes one or more memory devices and a processing device, operatively coupled to the one or more memory devices.

Abstract: In an embodiment, two or more storage systems are requested to prepare respective local checkpoints for a dataset, wherein each of the two or more storage systems stores portion of the dataset. The two or more storage systems are determined to have established the checkpoint. In response to determining that the local checkpoints have been established, a coordinated checkpoint is completed.

Abstract: Systems and methods for managing incremental data backups on an object store. A computing device receives first data representing a changed chunk of data in a revision of a data volume on a storage device, the changed chunk includes data having changes from previous data of a previous revision. The computing device creates a block of data representing a copy of the changed chunk on the object store, the object store also includes a previous revision block representing previous revision data. The computing device determines a previous index stored on the object store corresponding to the previous revision, which includes entries including at least one corresponding to the previous revision block. The computing device creates a copy of at least one previous index from the object store, and a revised index that updates the corresponding entry with updated entry data representing the change block.

Abstract: A device comprising a memory controller coupled to a non-volatile memory (NVM) device with a shadow tracker memory region. The controller comprises a low-overhead and low recovery time for integrity-protected systems by recovering a secure metadata cache. The controller is configured to persistently track addresses of blocks in the secure metadata cache in the NVM device when a miss occurs, and track the persistent addresses, after the miss. The controller is configured to rebuild affected parts of the secure metadata cache associated with the persistent addresses in the NVM device. A system is provided which includes the memory controller interfaced with an NVM device with the shadow tracker memory region.

Abstract: Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary and a secondary replica for an instance, with each capable of residing in a separate data zone or geographic location to provide a level of reliability and availability. A database running on the primary instance can have information synchronously replicated to the secondary replica at a block level, such that the primary and secondary replicas are in sync. In the event that the monitoring component is not able to communicate with one of the replicas, the monitoring component can attempt to determine whether those replicas can communicate with each other, as well as whether the replicas have the same data generation version. Depending on the state information, the monitoring component can automatically perform a recovery operation, such as to failover to the secondary replica or perform secondary replica recovery.

Abstract: A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (?) and a standard deviation (?) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (?) and the standard deviation (?) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.

Abstract: Providing for high availability in a data analytics pipeline without replicas, including: creating a data analytics pipeline, wherein each component of the data analytics pipeline is deployed within a container; creating a failover container; detecting that a component within the data analytics pipeline has failed; and responsive to detecting that the component within the data analytics pipeline has failed, deploying the component within the data analytics pipeline that has failed in the failover container.

Abstract: A Highly Available system utilizes at least one host fit to send data, and a primary server fit to receive data. The primary server comprises, a failover server capable of communicating with a http server and able to receive data from the host, and where the http server can receive data from the failover server, and an adapter capable of receiving data from the http server for processing. The Highly Available system also utilizes at least one secondary server fit to receive data from the host, and further fit to process data on failure of primary server or its components. The secondary server comprises a second failover server capable of communicating with a second http server and able to receive data from the host, and where the second http server can receive data from the second failover server, and an adapter capable of receiving data from the second http server for processing.

Abstract: Systems, methods and article provide the services of heterogeneous resources, for example the services analog processors, e.g., quantum processors, in a robust manner that can include high availability, failover, and load balancing of the heterogeneous resources. A virtual solver is selected based at least in part on a first set of requirements, a first set of analog processors is identified based at least in part on the first set of requirements, and a first handle returned to the first virtual solver. A load balancer may balance loads. Failure over may be implemented.

Abstract: Failover methods and systems for a storage environment are provided. During a takeover operation to take over storage of a first storage system node by a second storage system node, the second storage system node copies information from a first storage location to a second storage location. The first storage location points to an active file system of the first storage system node, and the second storage location is assigned to the second storage system node for the takeover operation. The second storage system node quarantines storage space likely to be used by the first storage system node for a write operation, while the second storage system node attempts to take over the storage of the first storage system node. The second storage system node utilizes information stored at the second storage location during the takeover operation to give back control of the storage to the first storage system node.

Abstract: Sets of asynchronous replication operations may be tracked to ensure consistency. A tracking service may receive notifications of pending asynchronous replication tasks, and responsive to receiving a manifest indicating a request to be notified upon completion of a set of pending replication asynchronous tasks, matches individual ones of the tasks within the set to tasks indicated as pending. The tracking service may then select a routing table based on a most recent sequence number associated with the set of tasks, determine one of more tracking nodes assigned to track the set of tasks, and send the manifest to each of the tracking nodes. As individual ones of the tasks complete, notifications of completion may be sent to the tracking nodes and an aggregator node aggregates the completion notifications for the set. Once all completion notifications are received, a response to the request indicating completion may be sent.

Abstract: A redundant array of independent disks (RAID) management method includes, when detecting that a component in a storage medium fails, recovering, based on a RAID policy, data stored in the failed component, saving the recovered data into a pre-defined redundant space of the RAID, and mapping an address of the failed component with the address of the redundant space, converting, according to the mapping, an address of to-be-accessed data comprised in an accessing request into an address within the redundant space, and accessing the to-be-accessed data from the redundant space according to the address within the redundant space.

Abstract: Disclosed methods and systems may perform testing and test management operations in which an information handling resource is provisioned with a programming hook corresponding to an operation associated with the resource. Extended testing operations may be performed when the hook is triggered. These operations may include selecting a particular test service docker from among one or more extended test service dockers. The particular test service docker may then be downloaded and executed. The triggering operation may be associated with a standard pre-check/post-check test framework and, in such cases, the extended testing operations include one or more tests in addition to the pre-check and post-check. Suitable test service dockers may be maintained in a public and/or private cloud. Some embodiments support customer-defined test service dockers, which may initiate as private dockers, but which may be published to the public cloud and linked to the hook.

Abstract: A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.

Abstract: In some examples, an electronic device records, in an entry of a time-state data structure that includes a plurality of entries to store respective times, a time in response to invocation of a time-lapse process that lasts a predefined time duration independently of a time clock of the electronic device. The electronic device determines whether times in successive entries of the plurality of entries of the time-state data structure are within a threshold of one another, the threshold based on the predefined time duration. Based on the determining, the electronic device sets a parameter representing a quality of the time clock.

Abstract: Methods, systems, and computer-readable storage media for receiving, by an anomalous operation detection service, current signal data representing a driving current applied to a device over a time period, processing, by an anomalous operation detection service, the current signal data through a deep neural network (DNN) module, a frequency spectrum analysis (FSA) module, and a time series classifier (TSC) module to provide a set of indications, each indication in the set of indications indicating one of normal operation of the device and anomalous operation of the device, processing, by an anomalous operation detection service, the set of indications through a voting gate to provide an output indication, the output indication indicating one of normal operation of the device and anomalous operation of the device, and selectively transmitting one or more of an alert and a message based on the output indication.

Abstract: A system and method for processing application performance using application phase differentiation and detection is disclosed. Phase detection may be accomplished in a number of different ways, including by using a deterministic algorithm that looks for changes in the computing resource utilization patterns (as detected in the performance data collected). Machine learning (ML) and neural networks (e.g. sparse auto encoder SAE) may also be used. Performance data is aggregated according to phase and stored in a database along with additional application and computing system information. This database may then be used to find similar applications for performance prediction.

Abstract: A process in a system can monitor available free storage space on a storage device, and, based on preset log file parameters, can act upon log files being stored on or written to the storage device to keep the storage device from running out of storage space due to excessive logging. The process monitors the device free space as reported by the file system to determine space utilization. A threshold of free space can be specified as a parameter. A log file action can also be specified as a parameter and is an action designed to reduce the space being used by a log file or log files. Once the process recognizes that the free space is under the threshold it will perform the configured action.

Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to receive, by a trace filter system, a trace chunk from a trace buffer associated with a processor core in a processing device, where the trace buffer is comprised of a plurality of trace chunks, to filter, by the trace filter system, the trace chunk, and to store the filtered trace chunk in the trace buffer.

Abstract: High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen.

Abstract: Systems and methods are described for automated classification of defective code from bug tracking tool data. An example method includes receiving a plurality of datasets representing a plurality of bug reports from a bug tracking application. Each dataset may be generated by vectorizing and clustering a source code associated with a respective bug report represented by the dataset. Each dataset may comprise a plurality of classes. At least one class of each dataset may indicate at least one known bug. For each dataset of the plurality of datasets, a respective supervised feature vector may be generated. Each supervised feature vector may be associated with an index of the at least one class with the at least one known bug. Using the supervised feature vectors, a classification model is trained to detect a new bug presence in a new source code.

Abstract: A system and method may cause a computing device to operate according to a selected operational mode. A diagnostic application may selectively execute one or more tests on the computing device; record a result of executing a test; and perform an action based on the result. An operational mode selected may be a safe mode that includes executing only a portion of an operating system and the diagnostic application. A test may include executing an application and selectively validating performance of one or more resources of a computing device while the application is executing. A test may include executing an application selected based on a rule related to a category of applications.

Abstract: Test cases written to test a software application can be dynamically distributed among a set of software application instances such that different sets of test cases can execute simultaneously in parallel, thereby speeding up testing relative to executing the test cases sequentially. To avoid database conflicts that may occur when different test cases are executed in parallel, each software application instance can be associated with a different database instance. Accordingly, a first test case executing in association with a first database instance can avoid interfering with a second test case executing in association with a second database instance.

Abstract: Comparing the performance of multiple versions or branches/paths of an application (e.g., a web service or application) may be conducted within a suitable computing environment. Such an environment may be virtual in nature, cloud-based, or server-based, and is hosted with tools for simultaneously (or nearly simultaneously) executing multiple containers or other code collections with the same or similar operating conditions (e.g., network congestion, resource contention, memory management schemes). By arranging the performance test of different application versions in different sequences executed in parallel in separate containers, fair comparisons of the tested applications will be obtained. Testing sequences may be executed multiple times, and metrics are collected during each execution. Afterward, the results for each metric for each code version are aggregated and displayed to indicate their relative performance quantitatively and/or qualitatively.

Abstract: The present disclosure involves systems, software, and computer implemented methods for executing integration scenario regression tests in customer landscapes. One example method includes identifying a request to create a test case for an integration scenario for a cloud platform customer. The test case is created for the scenario, including enabling the test case to run in an isolated customer environment specific to the customer. An update to the cloud platform is identified. The update is provisionally applied to the cloud platform for the customer. The test case is executed in the isolated customer environment, to test the scenario for the customer. A determination is made as to whether execution of the test case succeeded. In response to determining successful test case execution, the update to the cloud platform is finalized for the customer. In response to determining unsuccessful test case execution, the update is rolled back for the customer.

Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).