Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

Abstract: Embodiments of information handling systems (IHSs) and methods are provided herein to improve the security and performance of a shared cache memory contained within a multi-core host processor. Although not strictly limited to such, the techniques described herein may be used to improve the security and performance of a shared last level cache (LLC) contained within a multi-core host processor included within a virtualized and/or containerized IHS. In the disclosed embodiments, cache security and performance are improved by using pre-boot Memory Reference Code (MRC) based cache initialization methods to create page-sized cache namespaces, which may be dynamically mapped to virtualized and/or containerized applications when the applications are subsequently booted during operating system (OS) runtime.

Abstract: Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective portions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, the target range partition is divided into two partitions, the partition that excludes the data value is designated as uncached; the values therein are evicted. If the cache has space, the data value is copied onto the cache; otherwise the division/eviction are repeated until the cache has space.

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table.

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

Abstract: A method and system configured to receive a first report from a computer peripheral device by a receiver, determine that the first report is corrupted or received at a rate slower than the first report rate, compute a current trajectory of the computer peripheral device based on one or more intervals of movement data in the first report, compute a predicted trajectory of the computer peripheral device based on the first report, compute an incremental displacement of the computer peripheral device based on the predicted trajectory. The method and system can further generate data indicative of a position or displacement of the computer peripheral device based on the predicted trajectory of the computer peripheral device and send the data indicative of a position or displacement of the computer peripheral device at an interval that is less than twice a period of the first report rate to the host computing device.

Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.

Abstract: Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).

Abstract: An apparatus is provided that includes a network interface to transmit and receive data packets over a network; a memory including one or more buffers; an arithmetic logic unit to perform arithmetic operations for organizing and combining the data packets; and a circuitry to receive, via the network interface, data packets from the network; aggregate, via the arithmetic logic unit, the received data packets in the one or more buffers at a network rate; and transmit, via the network interface, the aggregated data packets to one or more compute nodes in the network, thereby optimizing latency incurred in combining the received data packets and transmitting the aggregated data packets, and hence accelerating a bulk data allreduce operation. One embodiment provides a system and method for performing the allreduce operation. During operation, the system performs the allreduce operation by pacing network operations for enhancing performance of the allreduce operation.

Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).

Abstract: A system and method for performing a combined storage operation, the method including using a direct memory access (DMA) controller to obtain a modified DMA command, wherein the modified DMA command includes parameters of a data manipulation and one of a user read command or a user write command; retrieve data according to the user read command or the user write command; manipulate the data according to the parameters of a data manipulation, inline with the user read command or the user write command; and transmit the manipulated data according to the user read command or the user write command.

Abstract: The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: A relay device includes a first connecting unit, a second connecting unit, a first notifying unit, a second notifying unit, and a communicating unit. The first connecting unit is connected with a first interface of a first device, the first interface being not compliant with USB (Universal Serial Bus) standard. The second connecting unit is connected with a second interface of a second device, the second interface being compliant with the USB standard. The first notifying unit notifies the second device that the relay device is a USB device. The second notifying unit notifies the first device that the second device has been connected to the second connecting unit. The communicating unit relays communication carried out between the second device and the first device.

Abstract: A universal serial bus (USB) signal transmission device, an operation method thereof, and a USB cable are provided. The USB signal transmission device includes a signal processing circuit, a switch circuit, and a control circuit. A first terminal of the switch circuit is coupled to a first USB circuit. A second terminal of the switch circuit is coupled to a second USB circuit. The control circuit turns off the switch circuit during a detection period to detect both terminals of the switch circuit to obtain a detection result. The control circuit turns on the switch circuit during a transmission period, and controls a transmission direction of the signal processing circuit according to the detection result.

Abstract: A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.

Abstract: An information handling system includes a processor that provides a USB-2 channel and a USB-3 channel to a device. The device provides the USB-2 and -3 channels to selected ports. Each port includes a USB-3 enable setting. When the USB-3 enable setting for each particular USB port is in a first state, the associated device USB-3 channel is active, and when the USB-3 enable setting for each particular USB port is in a second state, the associated device USB-3 channel is inactive. The USB-3 enable setting for at least one of the USB ports is placed into the second state to reduce electromagnetic interference between the associated USB-3 channel and an antenna.

Abstract: An endpoint interface device architecture utilized in multi-drop communication networks, such as the RS485 architecture, that utilizes control logic software/firmware within the endpoint microprocessor to isolate shorted lines from the communication transceiver, and to communicate status information to a first or second data source.

Abstract: Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

Abstract: A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. An I3C master receives a max read length and a max write length from an I3C slave. Then, when transmitting/receiving data to/from the I3C slave, the I3C master controls transmission/reception of the data so that the data to be transferred in one data transfer has a data length equal to or shorter than the max read length and the max write length, and transmits transfer length information indicating the data length of the data to be transferred, prior to data transfer of the data. The present technology is applicable to a bus IF, for example.

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

Abstract: The technology disclosed partitions a dataflow graph of a high-level program into memory allocations and execution fragments. The memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph. The execution fragments represent operations on the data. The technology disclosed designates the memory allocations to virtual memory units and the execution fragments to virtual compute units. The technology disclosed partitions the execution fragments into memory fragments and compute fragments, and assigns the memory fragments to the virtual memory units and the compute fragments to the virtual compute units. The technology disclosed then allocates the virtual memory units to physical memory units and the virtual compute units to physical compute units.

Abstract: Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.

Abstract: Techniques are provided for coordinating snapshot operations across multiple file systems. A notification may be received that a snapshot of data stored across a persistent memory file system and a storage file system is to be generated. Forwarding, of modify operations from a persistent memory tier to a file system tier for execution through the storage file system, may be enabled. Framing may be initiated to notify the storage file system of blocks within the persistent memory file system that comprise more up-to-date data than corresponding blocks within the storage file system. In response to the framing completing, a consistency point operation is performed to create the snapshot and to create a snapshot image as part of the snapshot.

Abstract: A request is received to retrieve at least a portion of a file from a compressed data archived image stored in a backup storage device. The compressed data archived image comprises a backup of a file system having a number of directories and a number of files. The compressed data archived image comprises a file that includes a compression of the number of files. An address of the at least the portion of the file within the compressed data archived image is determined. The at least the portion of the file is retrieved at the address in the compressed data archived image, without decompressing the compressed data archived image.

Abstract: Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Abstract: A client identifies a first data unit to be shared from a first file to a second file and sends an operation to copy that indicates the first data unit to be shared. The operation to copy the first data unit from the first file to the second file is received. In response to receiving the operation to copy the first data unit from the first file to the second file, it is determined whether the first data unit can be shared with the second file. In response to determining that the first data unit cannot be shared with the second file, the first data unit is copied to the second file. In response to determining that the first data unit can be shared with the second file, the first data unit is shared between the first file and the second file.

Abstract: In a rack comprising a group of servers and at least two top-of-rack switches, a link fault is detected. A smart data cable connects each of the servers to both top-of-rack switches. A control signal indicates an active communication path from one of the top-of-rack switches to the servers. In response to detecting a failure of the active communication path, the control signal indicates a switch to the second of the top-of-rack switches. In response to the updated control signal, a switching mechanism of the data cable changes the active communication path to the second of the top-of-rack switches.

Abstract: The present disclosure discloses construction method, device, computing device, and storage medium for constructing patent knowledge database. The method comprises: obtaining patent resource data; analyzing the patent resource data to obtain explicit information and implicit information, the explicit information comprises attribute information of each entity in a preset entity set, the implicit information comprises an entity relationship of technical elements; fusing the implicit information to obtain fused implicit information; and constructing the patent knowledge database according to the explicit information and the fused implicit information.

Abstract: According to an embodiment, a method of building a database in which voice signals match texts comprises providing a captcha-purposed voice signal including a first voice signal matched with a first text and a second voice signal matched with no text, sending a request for a first input text and a second input text for the captcha-purposed voice signal, when the first input text and the second input text are received, comparing the first text with the first input text, and when the first text is identical to the first input text, matching the second voice signal with the second input text and storing the match. Embodiments of the present invention may be related to artificial intelligence (Al) modules, unmanned aerial vehicles (UAVs), robots, augmented reality (AR) devices, virtual reality (VR) devices, and 5G service-related devices.

Abstract: There is a need for more effective and efficient cross-dataset field integration.

Abstract: Solutions for data unification include: receiving a data record, the data record comprising a plurality of data fields; selecting, from among the plurality of data fields, a subset of the data fields, the subset of the data fields being fewer in number than the plurality of data fields, wherein selecting the subset of the data fields comprises: applying a first rule to select at least a first one of the data fields within the data record for inclusion in the subset of the data fields; using content of the subset of the data fields, generating a stable identifier (stableID) for the data record; and inserting the stableID into a primary key data field of the data record.

Abstract: Technologies are provided for automated generation of revision summaries for an electronic document. In some embodiments, a computing system can determine that a first section of a first version of the electronic document includes changes relative to a second section of a second version of the electronic document. The second section corresponds to the first section. The computing system also can generate respective descriptions of the first section and the second section. The computing system can then generate a summary of the changes by comparing the respective descriptions. The computing system can determine that the summary has a defined placement in a ranking of similarity scores, where a first similarity score in the ranking defines similarity between the respective descriptions. The computing system can add metadata to the first version of the electronic document. The metadata controls presentation of a visual element indicative of the summary within a user interface.

Abstract: In one embodiment, a method comprises creating and storing an ontology for a data store in response to receiving first user input defining the ontology, wherein the ontology comprises a plurality of data object types and a plurality of object property types; creating one or more parser definitions in response to receiving second user input defining the parser definitions, wherein each of the parser definitions specifies one or more sub-definitions of how to transform first input data into modified input data that is compatible with one of the object property types; and storing each of the one or more parser definitions in association with one of the plurality of object property types.

Abstract: A system and method is provided for providing searchable customer call indexes. Consistent with disclosed embodiments, a system may receive call information associated with telephone conversations between callers and a vendor, the call information including an audio recording or transcript for each telephone conversation. The system may also identify one or more keywords from the audio recordings or transcripts and index the call information into one or more indexes based on the identified keywords. Finally, the system may determine search results responsive to a search query based on the indexing. In some embodiments, changes to customer service may be identified based on the search results.

Abstract: The present disclosure provides a method of reading data maintained in a tree data structure, such as B+ tree, using near data processing (NDP) in a cloud native database. According to embodiments, a desired LSN will be used in NDP page reads on the master computing node (e.g. master SQL node). When the master computing node (e.g. master SQL node) reads the regular page, the maximum desired LSN (e.g. the latest page version number) for that regular page will be used. Embodiments use features of the desired LSN and page locking, wherein correct versions of pages can be obtained by using the desired LSN associated with a page, in combination with page locking, and can enable the reading of a consistent tree structure and achieve good read/write concurrency.

Abstract: A system includes storage of data into a target memory location allocated to a target leaf node of a tree-based index structure, the target leaf node being a child node of a parent node of the tree-based index structure, where the tree-based index structure comprises one or more other leaf nodes which are child nodes of the parent node, and each of the target leaf node and the one or more other leaf nodes is associated with a plurality of allocated memory locations, incremental identification of all unused allocated memory locations between a first allocated memory location of a left-most one of the target leaf node and the one or more other leaf nodes and a last used allocated memory location of a right-most one of the target leaf node and the one or more other leaf nodes, and movement of data stored in the target leaf node and the one or more other leaf nodes into the identified unused allocated memory locations.

Abstract: Systems and methods are described to generate reverse dependency lists for cells in a workbook data store. In one aspect, a system populates, for a first cell in the data store, a reverse dependency list identifying a second cell, wherein the second cell comprises a second cell value that depends, at least in part, on a first cell value of the first cell. The system then detects a change to cell information for the first cell, and based on the detected change to the cell information: marks the second cell for recalculation based on the second cell being identified in the reverse dependency list for the first cell and the detected change to the cell information. For each marked cell, the system performs recalculation on the marked cell, performs recalculation recursively on any cells on which the marked cell depends, and stores recalculated cell values in a recalculated cache.

Abstract: A sub-archive is initiated. The sub-archive saves changes that have occurred since a previous final archive. Changes to an operational database (i.e., the operational database that is being archived) are allowed during the first sub-archive. A final archive is initiated in series after the sub-archive has completed. The final archive does not allow changes to the operational database when the final archive is active. In one embodiment, the sub-archive may comprise a plurality of sub-archives that depend on an amount of outstanding changes that exist in the operational database.

Abstract: A data analysis system is provided in the invention. The data analysis system includes a storage device, a field-data-description-file generating module, and a general data readiness analysis module. The storage device stores a plurality of raw data. The field-data-description-file generating module generates the field-data-description files corresponding to the raw data. The general data readiness analysis module obtains a score of the consistency indicator of the raw data according to the field-data-description files. The general data readiness analysis module obtains the data of the category which needs to be analyzed from the raw data according to the category of each field-data-description file. The general data analysis module obtains the score of the completeness indicator, the score of the accuracy indicator, the score of the validity indicator, and the score of the compaction indicator which all correspond to the data of the category which needs to be analyzed.

Abstract: Described are techniques for evaluating technology add-ons used with a data intake and query system to identify errors that may be present in or associated with configuration files defining the functions of the technology add-on or with operation of the technology add-on. For example, the technology add-on may be used to provide searching of event data stored by the data intake and query system using a late-binding schema, where the technology add-on provides for formalized interpretation of non-standard event data according to a user- or vendor-defined scheme. The disclosed techniques can identify errors and determine if the technology add-on is compliant with a schema definition for a common information model.

Abstract: In an embodiment, a server computer (“server”) identifies planting datasets of planting data values that correspond to separate planting passes in a field and harvesting datasets of harvesting data values that correspond to separate harvesting passes in the field, each planting data value and each harvesting data value including a location value. The server normalizes the planting datasets based on a heading direction of a first agricultural equipment, a row-unit shift of the first agricultural equipment, or a direct measurement of a first measurement device value. The server also normalizes the harvesting datasets based on a heading direction of a second agricultural equipment, a row-unit shift of the second agricultural equipment, or a direct measurement of a second measurement device value.