Abstract: A process for manufacturing a piezoelectric structure for a radiofrequency device comprises providing a substrate of piezoelectric material, providing a carrier substrate, providing a dielectric bonding layer on the substrate of piezoelectric material, a step of joining the substrate of piezoelectric material to the carrier substrate via the dielectric bonding layer, and a thinning step for forming the piezoelectric structure, which comprises a layer of piezoelectric material joined to a carrier substrate via the dielectric bonding layer.

Abstract: A front-end module may include an acoustic wave filter with a first and second interdigital transducer electrode, and a low noise amplifier (LNA) that converts a differential input to a single-ended output with respect to ground. The first interdigital transducer electrode may be single-ended with a first input bus bar configured to receive an input signal and a second input bus bar connected to ground. The second interdigital transducer electrode may be differential with a first output bus bar connected to a first output terminal and a second output bus bar connected to a second output terminal. The LNA may have a differential input connected to the acoustic wave filter, a first input transistor that receives a first signal from the first output terminal of the acoustic wave filter, and a second input transistor that receives a second signal from the second output terminal of the acoustic wave filter.

Abstract: A package structure of an air gap type semiconductor device includes a carrier; a semiconductor chip; and a bonding layer disposed between the carrier and the semiconductor chip. A first cavity is formed in the bonding layer and enclosed by the semiconductor chip and the carrier to at least aligned with a portion of an active region of the semiconductor chip. An encapsulation layer and the bonding layer are on a same side of the carrier to encapsulate the semiconductor chip and an exposed region of the bonding layer. At least one portion of the encapsulation layer is formed between the semiconductor chip and the carrier along a direction perpendicular to a lateral surface of the carrier. Interconnection structures formed on a side of the carrier different from a side with the bonding layer. Each interconnection structure is electrically connected to a corresponding input/output electrode of the semiconductor chip.

Abstract: Lateral field excitation acoustic resonators and methods of manufacture are disclosed. In one aspect, an acoustically resonating material such as a piezoelectric film or membrane is spaced from a substrate by electrodes having an air gap therebetween. When current flows through the electrodes, lateral field acoustic waves are excited in the resonating material with relatively good coupling and adequate heat dissipation.

Abstract: A vibrator device includes: an element substrate including a frame portion having a first surface and a second surface, and a vibrator element disposed inside the frame portion; a first substrate having a third surface and a fourth surface, the first substrate being bonded to the first surface of the frame portion at the third surface; a second substrate having a fifth surface and a sixth surface, the second substrate being bonded to the second surface of the frame portion at the fifth surface; and a cavity surrounded by the frame portion, the first substrate, and the second substrate. The second substrate includes a through electrode at a position overlapping the frame portion in the plan view. An outer shape of the through electrode in the sixth surface in the plan view includes a first portion and a second portion. The first portion is located at a position closer to the cavity than is the second portion. A curvature of the first portion is smaller than a curvature of the second portion.

Abstract: An acoustic wave element 1 according to the present disclosure includes a piezoelectric substrate 2 and an IDT electrode 3 on the piezoelectric substrate 2. The IDT electrode 3 includes a multilayer structure of a first layer 35 comprised of Al containing 10% or less of a sub-component and a second layer 37 comprised of a CuAl2 alloy. The second layer 37 enables the acoustic wave element 1 to have excellent electric power resistance.

Abstract: The present invention provides a technique for making a film bulk acoustic resonator with ease, at low cost. A film bulk acoustic resonator, according to one aspect of the present disclosure has: a substrate having a first main surface; an oxide film provided over the first main surface; and a laminated film provided over the oxide film and including a first electrode, a piezoelectric layer, and a second electrode laminated in this order, and, in this film bulk acoustic resonator, a void where the oxide film is removed is provided between the substrate and the first electrode, and the piezoelectric layer has a through-hole that communicates with the void.

Abstract: To achieve an elastic wave element with excellent electrical characteristics. An elastic wave resonator includes a piezoelectric substrate including a piezoelectric body and an IDT electrode, a support substrate, and a first intermediate layer. In the first intermediate layer, an atomic ratio of a metal element is larger than an atomic ratio of a metal element in the piezoelectric body, and an atomic ratio of oxygen is smaller than an atomic ratio of oxygen in the piezoelectric body. A thickness of the piezoelectric body is equal to or less than five times a maximum pitch of electrode fingers of the IDT electrode.

Abstract: An acoustic wave device comprises a substrate including a piezoelectric material, interdigital transducer (IDT) electrodes including interdigitated electrode fingers disposed on a surface of the substrate, and a passivation layer formed on tops of the IDT electrodes and on the piezoelectric material in gaps between adjacent IDT electrodes, the passivation film being thicker on the tops of the IDT electrodes than on the piezoelectric material in the gaps between adjacent IDT electrodes to improve an electromechanical coupling factor of the acoustic wave device.

Abstract: A high-frequency circuit includes a signal wire connecting a pair of signal terminals; and a reference potential wire arranged along and close to the signal wire and connecting a pair of reference potential terminals.

Abstract: A technique is provided herein whereby the size of piezoelectric filters can be reduced. A piezoelectric filter according to one aspect of the present disclosure has: a first substrate having a first main surface; a second substrate having a second main surface facing the first main surface; and a ladder circuit of Nth order, including N piezoelectric resonators, N being an integer of 3 or greater. In this piezoelectric filter, the first-order to Mth-order piezoelectric resonators included in the ladder circuit are formed on the first main surface, M being an integer from 1 to N?1, inclusive, and the (M+1)th-order to Nth-order piezoelectric resonators included in the ladder circuit are formed on the second main surface.

Abstract: Acoustic resonator devices, filters, and methods are disclosed. An acoustic resonator includes a substrate, a lithium niobate plate having front and back surfaces, wherein Euler angles of the lithium niobate plate are [0°, ?, 0° ], where ? is greater than or equal to 0° and less than or equal to 60°, and an acoustic Bragg reflector between the surface of the substrate and the back surface of the lithium niobate plate. An interdigital transducer (IDT) is formed on the front surface of the piezoelectric plate. At least one finger of the IDT is disposed in a groove in the lithium niobate plate.

Abstract: A multiplexer includes a transmit filter including first acoustic wave resonators connected to a first path between a common terminal and a transmit terminal, one or some first acoustic wave resonators of the first acoustic wave resonators being provided on a first substrate, and a remaining first acoustic wave resonator being provided on a second substrate, and a receive filter including second acoustic wave resonators connected to a second path between the common terminal and a receive terminal, one or some second acoustic wave resonators of the second acoustic wave resonators being provided on the first substrate and a remaining second acoustic wave resonator being provided on the second substrate, and a resonator closest to the receive terminal in a plan view among the one or some first and second acoustic wave resonators being a second acoustic wave resonator of the one or some second acoustic wave resonators.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a baseband filter that can be used in a current-mode end-to-end signal path. The current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. In one or more embodiments, a device used in the signal path can comprise a baseband filter that receives an input current and outputs an output current. The baseband filter can comprise a feedback loop component having an active circuit branch and a passive circuit branch coupled in a loop. A mirroring device can be coupled to the feedback loop component and can provide an output of the device. Selectively activating the mirroring device can vary gain, such as of the mirroring device.

Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.

Abstract: Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.

Abstract: Disclosed in the present invention are a low-temperature coefficient ring oscillator, a chip, and a communication terminal. The low-temperature coefficient ring oscillator comprises a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The temperature characteristics of the impedance of a PMOS tube and an NMOS tube in an inverter in the inverter oscillation circuit are tracked and compensated for by means of the impedance, along with temperature change, of a PMOS tube and a NMOS tube connected by a diode.

Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register

Abstract: According to one embodiment, a semiconductor device includes a first transistor, a first circuit, a second circuit, and a third circuit. The first transistor has one end connected to a power supply voltage terminal, the other end connected to a first node, and a gate connected to a first output terminal. The first circuit is configured to control a voltage of the first node based on a voltage of a ground voltage terminal. The second circuit is configured to control a voltage of the first output terminal based on the voltage of the ground voltage terminal and a voltage of an input terminal. The third circuit is configured to control switching between connection and disconnection between the ground voltage terminal and the first circuit.

Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

Abstract: The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.

Abstract: The present invention provides a Miller clamping device for parallel switching transistors and a driver comprising the same. The Miller clamping device includes: a driver chip including an output terminal and a built-in Miller clamping circuit with a Miller clamping terminal, the output terminal of the driver chip being configured to output a pulse width modulation signal; and a plurality of auxiliary Miller clamping circuits, each of the auxiliary Miller clamping circuits being connected between a gate of a corresponding switching transistor and the Miller clamping terminal of the built-in Miller clamping circuit. When the built-in Miller clamping circuit is triggered for Miller clamping, a Miller current generated by the corresponding switching transistor flows to a first direct-current (DC) voltage through a corresponding auxiliary Miller clamping circuit. The Miller clamping device of the present invention can perform Miller clamping on the parallel switching transistors and reduce the circuit cost.

Abstract: A circuit structure for realizing circuit pin multiplexing, comprising an MCU module, a temperature sensing circuit and a functional module circuit. The output end of the temperature sensing circuit is connected with an enable signal interface of the MCU module, the output voltage of the temperature sensing circuit is always higher than the threshold voltage of the enable signal, and the MCU module is connected with the functional module circuit. The circuit structure of the present invention realizes the mutual influence of analog signal output and digital signal transmission by designing a temperature sensing output curve, and achieves multi-function multiplexing of a single pin, so that the output of the analog signal and the input of the digital signal can share the pins, it solves the problem of the limitation of the number of pins, and promotes the transmission of the signal and improves the cost performance of the circuit.

Abstract: Performance of a semiconductor device is enhanced. A loss of a circuit device using a semiconductor device as a switch is reduced. A semiconductor device includes: a first semiconductor chip having a first MOSFET of p-type and a first parasitic diode; and a second semiconductor chip having a second MOSFET of n-type and a second parasitic diode. On front surfaces of the first and second semiconductor chips, a first source electrode and a first gate wiring and a second source electrode and a second gate wiring are formed, respectively. On back surfaces of the first and second semiconductor chips, first and second drain electrodes are formed, respectively. The second back surface and the first front surface face each other such that the second drain electrode and the first source electrode come into contact with each other via a conductive paste.

Abstract: An aspect relates to an apparatus including a first pair of switching devices configured to selectively couple an application processor to a Universal Serial Bus (USB) differential data transmission lines; a USB host port connector coupled to the USB differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively.

Abstract: Provided is an interior article for a conveyance including a touch switch suppressing an unintended misoperation by an occupant. An interior article for a conveyance of the present invention includes a touch switch operating an electrical component provided in a conveyance and a recess portion formed in an interior side surface of the conveyance. The touch switch has a sensor detecting an occupant’s finger. The recess portion has an opening portion,a bottom portion, a standing wall portion formed around the bottom portion, and a curved surface formed to be curved so as to protrude toward the opening portion side in the bottom portion. The sensor is disposed on the curved surface.

Abstract: An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.

Abstract: A pulse detection circuit configured to detect peak pulse values from pulses contained in an input analog signal includes a control circuit to generate a peak control signal based on input from a microcontroller and/or a peak detector, and a peak track/hold circuit to produce an output peak analog signal responsive to the input analog signal and peak control signal. The peak track/hold circuit includes a peak-detect operational amplifier having first and second input terminals to receive the input analog signal and the peak control signal respectively, and a peak-hold capacitor connected to an output terminal of the operational amplifier. The pulse detection circuit includes an analog to digital converter to produce an output peak digital signal from the output peak analog signal. The peak track/hold circuit switches from a tracking mode to a hold mode upon the arrival of the peak control signal generated from the control circuit.

Abstract: One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.

Abstract: Consistent with the present disclosure, low pass filters are provided in the electrical paths connecting digital to analog converter (DAC) circuitry to an optical block package (also referred to as a “gold box”). The low pass filter blocks or substantially attenuates high frequency noise components present in an analog signal output from the DAC, thereby reducing errors that might otherwise be present in the transmitted data.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

Abstract: An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

Abstract: A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a third logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.

Abstract: A method to drive a digital to analog converter (DAC), the method including setting a reference current for the DAC with a reference current source, a base voltage being responsive to changes in a reference voltage at a reference node coupled with the reference current source; sensing a change in the reference voltage; and adaptively steadying the base voltage based on the change in the reference voltage to maintain proportionality between an output current of the DAC and the reference current.

Abstract: A system and method for concurrent encryption and lossless compression of data with an algorithm executing on a computer platform. The lossless compression component of the algorithm consists of preprocessing the data with a Burrows-Wheeler transformation followed by an inversion ranking transformation in advance of employing an entropy coder, such as binary arithmetic coder. The frequency vector of the Inversion Ranking transformation is then encrypted and transmitted along with the compressed data with only the frequency vector encrypted. Since the frequency vector is required for decompression, no further encryption of the compressed data is necessary to secure the compressed file.

Abstract: According to one embodiment, a data decompression device decodes a code included in compressed data into a symbol. The data decompression device includes a first code length generation unit and a second code length generation unit. The first code length generation unit generates a first code length of a first code included in the compressed data by arithmetic calculation. The second code length generation unit generates a second code length of a second code by using a table. The second code is included in the compressed data. The second code is subsequent to the first code. The table indicates at least the first code and the second code length that is associated with the first code.

Abstract: Techniques regarding quantum error correction are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a maximum-likelihood decoder component that executes a maximum-likelihood decoding algorithm to determine an error correction based on a decoding hypergraph that characterizes error-sensitive events associated with a quantum error-correcting code executed on a quantum circuit.

Abstract: Methods, systems, and devices for wireless communications are described. An encoding device (e.g., a base station or user equipment (UE)) may communicate, with a decoding device (e.g., a UE or base station), an indication of a set of encoding symbol identifiers via a control channel. The encoding device may transmit a set of packets associated with a rateless code via a data channel, where each of the set of packets includes an encoding symbol. The decoding device may decode the set of encoding symbols based on the set of encoding symbol identifiers.

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Abstract: A communication apparatus includes a transmission path arranged on a substrate, a signal source connected to an input portion of the transmission path, a metal member configured to function as a ground portion for the transmission path and having a space between the metal member and the transmission path, and a termination circuit configured to terminate the transmission path, wherein the termination circuit is arranged on a surface of the substrate on which the metal member is arranged.

Abstract: Embodiments of the invention include a wakeup receiver (WRX) featuring a charge-domain analog front end (AFE) with parallel radio frequency (RF) rectifier, charge-transfer summation amplifier (CTSA), and successive approximation analog-to-digital converter (SAR ADC) stages. The WRX operates at very low power and exhibits above-average sensitivity, random pulsed interferer rejections, and yield over process.

Abstract: A wireless transmission system includes a first coupler including a plurality of substrates including a signal line and a ground; and a second coupler that transmits a signal with the first coupler. A first substrate is connected to a second substrate by conductors having widths substantially equal to or less than widths of signal lines.

Abstract: In the radio frequency module, a first electronic component and a second electronic component are mounted on a principal surface of a mounting board. A resin layer covers an outer perimeter surface of the first electronic component and an outer perimeter surface of the second electronic component. A conductive layer covers the resin layer and overlaps the first electronic component and the second electronic component in a plan view. The conductive layer includes a first conductive portion and a second conductive portion. The first conductive portion is positioned in between the first RF terminal of the first electronic component and the second RF terminal of the second electronic component in the plan view. The second conductive portion is adjacent to the first conductive portion in the plan view. The resistivity of the first conductive portion is higher than the resistivity of the second conductive portion.

Abstract: A high-frequency module includes a mounting substrate, a first filter, a second filter, and a third filter. The mounting substrate has a first main surface and a second main surface opposite to each other. Simultaneous communication is enabled for the first filter and the second filter, and the third filter is not used in the simultaneous communication using the first filter and the second filter. The first filter, the second filter, and the third filter are mounted on the first main surface of the mounting substrate. A first substrate of the first filter, a second substrate of the second filter, and a third substrate of the third filter are common to each other. The third filter is disposed between the first filter and the second filter in plan view from a thickness direction of the mounting substrate.