Abstract: Placement scenario optimization mechanisms for automatic placement of computing entities onto nodes of a running multi-node computing cluster. A set of failure mode parameters define a high-availability requirement of the multi-node computing cluster. In advance of a failure event, and responsive to a determination that a then-current computing entity placement does not satisfy the high-availability requirement, the cluster is analyzed and a plurality of feasible placement scenarios are generated. Optimization criteria are applied to the feasible placement scenarios such that a best choice from among the feasible placement scenarios is identified and applied to the virtual machine placements over the cluster. A change monitoring and detection facility continually observes the multi-node computing cluster to detect a change of a failure mode parameter or to detect a change to the configuration of the virtual machines.

Abstract: A hardware failure prediction and avoidance system executing on a unified endpoint management platform information handling system comprising a network interface device (NID) to receive failed operational telemetries for client devices including power and software analytics, and event viewer error logs, and an error associated with a hardware type, a processor to execute a classification supervised learning algorithm on the failed operational telemetries to determine that a hardware or software configuration will likely co-occur with a future error of the hardware type, identify the hardware or software configuration as problematic, the processor to identify the problematic system configuration in a current operational telemetry by correlating the current operational telemetry with a portion of the failed operational telemetries, and the NID to transmit a recommendation to the first client device to adjust the problematic system configuration in order to avoid occurrence of the error at the first client devic

Abstract: A processor may identify that an apparatus is to be disposed. The apparatus may be composed of one or more hardware components. The processor may analyze the apparatus. The processor may generate a respective digital twin for each of the one or more hardware components. The processor may analyze the respective digital twin for each of the one or more hardware components. The processor may determine a condition of each of the one or more hardware components based on the respective digital twin for each of the one or more hardware components.

Abstract: A large-scale K8s cluster monitoring method, an apparatus, a computer device, and a readable storage medium. The method includes: performing classification on data sources in a cluster on the basis of a monitoring metric configuration means, and creating a data list on the basis of the data sources and the monitoring metric configuration means corresponding to said data sources; in response to receiving a command to monitor a first monitoring metric set of a first data source, obtaining a monitoring metric configuration means corresponding to the first data source on the basis of the data list; performing configuration on a monitoring metric on the basis of the first monitoring metric set and by means of the obtained monitoring metric configuration means; and obtaining from the first data source a monitoring metric in the first monitoring metric set every preset amount of time, and performing monitoring on the monitoring metric.

Abstract: A usage profile based CO2 optimization system of an information handling system may comprise a processor to determine, using an ensemble machine-learning algorithm, rankings for user-disruptive static system configurations for a plurality of client information handling systems according to a level at which each user-disruptive static system configuration impacts carbon footprints of the client information handling systems, determine the first and second client information handling systems have matching values for a highest ranked user-disruptive static system configuration and mismatching values for an adjustable dynamic system configuration, determine the first client information handling system has a smaller carbon footprint than the second client information handling system, a network interface device to transmit a recommendation to the second client information handling system to adopt the value for the adjustable dynamic system configuration at the first client information handling system to decrease the

Abstract: A method of sparse intent clustering is provided. The method comprises identifying features in a number of electronic user reports created by a user and contained in a database, wherein the features include a title and description. The features of each user report are encoded into a binary vector. The binary vector for each user report is fed into an autoencoder neural network that creates a N-dimensional vector representing the user report. The float vectors representing the user reports are projected into a N-dimensional space. The float vectors are clustered according to cosine similarities, wherein each vector cluster represents an intent of the user in creating the reports. The intent of each vector cluster is then labeled.

Abstract: Aspects of the disclosure relate to preserving enterprise artifacts using digital twin technology and intelligent smart contracts. The computing platform may receive a stream of internal data and a stream of external data. The computing platform may compare the received internal data and the received external data to historic internal data and historic external data, respectively. The computing platform may identify inconsistencies between the received data and the historic data using a plurality of key performance indicators, and may determine a critical value for each key performance indicator. The computing platform may determine whether the key performance indicator threatens the security of the enterprise artifacts. If the computing platform determines that the key performance indicator threatens the security of the enterprise artifacts, then the computing platform may execute at least one enterprise artifact protection protocol to safeguard the enterprise artifacts.

Abstract: An example method for monitoring operations of a business organization electronic computing device includes executing a checklist on a monitoring electronic computing device to obtain an operational status of an application being implemented on the business organization electronic computing device. Data is received from the business organization electronic computing device regarding the operational status of the application being implemented on the business organization electronic computing device. When a determination is made that the data identifies an operational threat for the business organization electronic computing device, an action is proposed or implemented to remediate the operational threat. An implementation of the checklist is adjusted based on an effectiveness of the action to remediate the operational threat.

Abstract: A data archiving method, an electronic device, and a readable storage medium relate to the field of the database technology. The method includes: acquiring monitoring data collected by at least one monitoring subsystem; storing, according to a preset rule, the monitoring data as multiple data objects corresponding to the monitoring subsystem; controlling a first thread corresponding to the monitoring subsystem to read the data objects into a corresponding data queue according to a preset order; and controlling a second thread corresponding to the monitoring subsystem to write the data objects from the data queue into a database in response to the first thread reading the data objects into the data queue each time.

Abstract: The technologies described herein are generally directed to allocating a resource to perform a task based on a predicted capacity of the resource. For example, a method described herein can include identifying a selected capacity associated with completion of tasks of a particular task type. Further, the method can include, evaluating a result of work by a worker resource performing a task of the particular task type. The method can further include, based on the result, predicting that the worker resource has the selected capacity and, based on this prediction, assign the worker resource to perform another task of the particular task type.

Abstract: A computer-implemented method for power capacity planning for a computing system the following steps: a) evaluating an activity of the computing system, wherein the activity comprises the number of program instances executed by the computing system; b) predicting an evolution of the activity based on the evaluated activity by using a first machine learning algorithm configured for activity evolution prediction; c) predicting a power consumption of the computing system as a first power metric; d) predicting an autonomy of one or more uninterruptible power supplies of the computing system as a second power metric; e) predicting a redundancy level of the computing system as a third power metric; and, f) generating output data related to power capacity planning by processing the first, second and third power metrics.

Abstract: Techniques are disclosed relating to retaining a log entry in response to detection of a respective triggering event occurring within a computer network. This triggering event may result in a set of processes being performed. A computer system may determine a trace signature for the log entry. This trace signature may track information related to the set of processes. The computer system may compute, using the trace signature, a log retention value for the log entry. This log retention value may be computed using weight factors for ones of the set of processes. The computer system may retain the log entry within a log file according to a retention period that corresponds to the log retention value.

Abstract: A program analysis apparatus includes a first code block extraction means for extracting a first code block having a specific property from codes included in a binary of a program, a second code block extraction means for extracting a second code block performing a predetermined sensitive operation from the codes included in the binary of the program, a relationship information acquisition means for acquiring relationship information indicating a relationship on a control flow between the first code block and the second code block, a backdoor score calculation means for calculating a backdoor score based on content of the predetermined sensitive operation in the first code block and performing addition and subtraction of the backdoor score with respect to the first code block based on the relationship information, and an output means for outputting the first code block and the backdoor score for the first code block.

Abstract: In an example embodiment, interactions among services in a service proxy are recorded in an interaction log. A service graph manager then parses the interaction log. The service graph manager reads each interaction and then processes the interaction to determine if it violates the rules. If so, the service graph manager reports the violation to the software developer and also recommends an action to remedy the violation. In an example embodiment, this recommendation takes the form of an indication of which files to modify to allow the service interaction (e.g., which rule(s) to modify to ensure that the service interaction is not a violation). The software developer can then approve the proposed action, which can then be automatically implemented to ensure that once the service is sent to a quality assurance environment there will be no rules violation from the corresponding interaction(s).

Abstract: A computer-implemented method for verifying a software component of an automated driving function. The method includes: translating the native program code into a model checker representation of the software component to be verified and analyzing the model checker representation of the software component to be verified using a model checking method. The native program code of the software component to be verified is limited to a set of operations of the programming language used that are defined as permissible. To do this, the native program code is converted into a finite automaton, the states and state transitions of which can be uniquely assigned to the code structure of the native program code. The model checker representation is generated based on the finite automaton such that the code structure of the native program code is substantially retained when the native program code is translated into the model checker representation.

Abstract: A computer-implemented method for verifying a software component of an automated driving function, The method includes: translating the native program code into a model checker representation of the software component to be verified and analyzing the model checker representation of the software component to be verified using a model checking method. The native program code of the software component to be verified is analyzed to identify independent sequences of commands, wherein an independent sequence of commands is a cohesive succession of program commands by which at least two variables are set, and the at least one result of an independent sequence of commands is independent of the order in which its program commands are processed. The variables of the at least one independent sequence of commands of the native program code are then simultaneously set in the model checker representation of the software component to be verified.

Abstract: The invention relates to a computer-implemented method for programming a checkpoint of at least one application executed on a computing infrastructure. The computing infrastructure includes a plurality of resources allocated to the execution of the application. The method includes determining a date of failure of the application as a function of a prediction of an anomaly of at least one resource of the plurality of resources, and programming the checkpoint as a function of the date of failure.

Abstract: A computer-implemented method for verifying at least one software component of an automated driving function. The method includes the following steps: providing an environment model that limits the state space of the software component to be verified by way of predefinable boundary conditions, wherein the environment model is provided in the form of a native environment model program code; translating the native program code of the software component to be verified and the environment model program code, wherein a model checker representation limited by the boundary conditions of the environment model and intended for the software component to be verified is generated; and verifying the model checker representation using a model checking method.

Abstract: A debugging support program causes a computer to execute: a step of extracting, from a module program constituting a sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; a step of creating a verification item for verifying operation of the module program, the verification item including a first setting value set for the first variable and a second setting value set for the second variable; a step of verifying operation of the module program based on the verification item; and a step of outputting a result of verifying operation of the module program.

Abstract: Systems and methods for implementing a verification of core file debugging resources are disclosed. A plurality of mappings are created from a core file comprising a plurality of filenames and a plurality of target build identifiers (IDs). The core file corresponds to a computer program crash event and each one of the plurality of mappings map one of the plurality of filenames to a corresponding one of the plurality of target build IDs. Responsive to creating the plurality of mappings, a first file is located that corresponds to a first filename included in a first mapping from the plurality of mappings. The first comprises a first target build ID. A processing device utilizes the first file to analyze the computer program crash event in response to determining that the first file build ID matches the first target build ID.

Abstract: A method of evaluating a computer-implemented product that is deployed on one or more endpoints. The method includes identifying a first program and a second program of a product deployed on a first endpoint of multiple endpoints. The method includes implementing a diagnostic process at the first endpoint. The diagnostic process includes a first subroutine directed to the first program and a second subroutine directed to a second program. The subroutines each execute installation and functional parameter tests of the programs. Responsive to the first subroutine indicating that the first program is operational, the method includes outputting data that the first subroutine passed. Responsive to the second subroutine returning an unexpected result, the method includes outputting data indicating details of the unexpected result and implementing a remediation that modifies the second program or a condition at the first endpoint to mitigate the unexpected result.

Abstract: A system for testing applications is disclosed. The system includes one or more processors, one or more communications modules coupled to the one or more processors to enable communications between services provided by the system, and at least one memory coupled to the one or more processors. The at least one memory stores computer executable instructions to enable a plurality of virtualized test services, each virtualized test service at least in part emulating dependent server responses to application operations. The instructions enable a load-balancing service for communication with the plurality of virtualized test services, and test an application based on a load, by directing the application to interact with the plurality of virtualized test services that are available, while avoiding communicating with the dependent servers during testing. The load-balancing service balances the testing of the application between the plurality of virtualized test services that are available.

Abstract: A system and method for automated software testing that uses machine learning algorithms to automatically generate and implement software testing based on an automated analysis of the software. In an embodiment, a mobile software application comprising one or more screens is processed through a trained machine learning algorithm to identify screens and objects, understand the operational flow of the application, define priorities and dependencies within the application, define validation tests, and automatically generate one or more testing scenarios for the application. The testing scenarios may then be fed to an automated execution module which installs the application on one or more physical or virtual devices and performs testing on the application installed on those devices according to the testing scenario.

Abstract: Described herein are methods, computer program products, and computer systems for video-based user interface (UI) application testing. The method includes receiving first test video data corresponding to test video images of an application executing on a first UI, generating the test video images on a first display, generating application video images on a second display. Further, the method may include determining that a first frame of the test video images and a second frame of the application video images fail to satisfy a predetermined similarity threshold, generating a third UI comprising the second frame of the second UI on a third display, receiving user inputs at the third UI for a first duration, capturing replacement test video images from the third display for the first duration, and generating second test video images, wherein the first frame of the test video images is replaced by the replacement test video images.

Abstract: A method for the analysis of test procedures of a device and/or function for at least partially autonomous guidance of a motor vehicle, comprising aggregating of the first characteristic value calculated for each of the plurality of test cases to form a second characteristic value representing a meta-test case; and evaluating the second characteristic value using a specified second criterion and the logical linking of the first evaluation results of the plurality of test cases to a second evaluation result of the meta-test case. A system for the analysis of test procedures of a device and/or function for at least partially autonomous guidance of a motor vehicle is also provided.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.

Abstract: A processor stores write data to be written to a storage area. The processor embeds a zone identifier for identifying a zone including consecutive logical addresses, and a sequence number for each logical address in a head or an end of a sector of the write data. The processor issues a zone append command for designating a head logical address of the zone and a size of the write data, instead of designating a logical address corresponding to the storage area to which the write data is written, and requesting writing of the write data to the storage area corresponding to the zone. The processor acquires a logical address corresponding to the storage location to which the write data is written. The processor stores the zone identifier and the sequence number in an expected value table storing expected values of read data corresponding to the zone for each logical address.

Abstract: An arithmetic processing apparatus includes: a memory; and a processor coupled to the memory and configured to: determine whether a critical section is being executed in inter-thread synchronization using read-copy-update, and when determining that the critical section is being executed, perform memory freeing processing or memory reallocation processing, which is executed from a scheduler, by speculative execution.

Abstract: This disclosure provides methods, devices, and systems for memory management. The present implementations more specifically relate to techniques for providing memory services over a CXL fabric. In some aspects, a memory management system may include an orchestration component, one or more host agents, and one or more endpoint controllers. Each host agent manages one or more memory services for a respective host computing device of a CXL system (or subsystem) and each endpoint controller manages one or more memory resources attached to a respective CXL device of the CXL system. The orchestration component coordinates with each host agent and endpoint controller to configure a CXL fabric to support the memory services provided to each host device. The memory management system receives updates associated with the memory services from each host device or CXL device and may dynamically reconfigure the CXL fabric based on the updates.

Abstract: A method and device for storing data are provided. The method includes: selecting at least one block from a plurality of blocks in a storage device as a evicting block or a target block based on an expected expiration time of each of the plurality of blocks in response to a request for garbage collection, wherein the expected expiration time of each block is obtained based on an expected expiration time of valid data of each block; and performing garbage collection based on the selected at least one block.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: In some examples, a computer identifies a plurality of memory servers accessible by the computer to perform remote access over a network of data stored by the plurality of memory servers, sends allocation requests to allocate memory segments to place interleaved data of the computer across the plurality of memory servers, and receives, at the computer in response to the allocation requests, metadata relating to the memory segments at the plurality of memory servers, the metadata comprising addresses of the memory segments at the plurality of memory servers. The computer uses the metadata to access, by the computer, the interleaved data at the plurality of memory servers, the interleaved data comprising blocks of data distributed across the memory segments.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: A technique for operating a device is disclosed. The technique includes recording log data for the device; analyzing the log data to determine one or more performance settings adjustments to apply to the device; and applying the one or more performance settings adjustments to the device.

Abstract: A Logically Composed System (LCS) data provisioning system includes an orchestrator device that includes a cache subsystem and that is coupled to client devices and storage subsystem(s). When the orchestrator device identifies that a first client device has exclusive access to the storage subsystem(s), it activates read data caching for the storage subsystem(s). The orchestrator device then receives a first read request from the first client device that is directed to first data that is stored in the storage subsystem(s) and, in response, retrieves the first data from the cache subsystem and provides the first data to the first client device. When the orchestrator device identifies that the first client device no longer has exclusive access to the storage subsystem(s), it deactivates the read data caching for the storage subsystem(s).

Abstract: A system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. The processor can save a snapshot of a logical-to-physical (L2P) table to a non-volatile memory device and maintain a journal of updates of the L2P. The processor can retrieve a sequence number from system metadata and save the most recent set of updates of the L2P table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number.

Abstract: Example implementations relate to data storage. An example includes a method comprising: receiving a data stream to be stored in a persistent storage of a deduplication storage system; assigning new data units to container indexes; storing the new data units of the data stream in a plurality of intake buffers, where each new data unit is stored in the intake buffer associated with the container index it is assigned to; determining whether a cumulative amount stored in the plurality of intake buffers exceeds a first threshold; in response to a determination that the cumulative amount exceeds the first threshold, determining a least recently updated intake buffer of the plurality of intake buffers; generating a first container entity group object comprising a set of data units stored in the least recently updated intake buffer; and writing the first container entity group object from memory to the persistent storage.

Abstract: A processor with protection of an isolated memory and protection method for the isolated memory accessible only by a trusted core are shown. A processor has a trusted core with a right to access an isolated memory planned on a system memory, a normal core prohibited from accessing the isolated memory, and a last-level cache shared by the trusted core and the normal core. The in-core cache structure of the normal core and the last-level cache are included in a hierarchical cache system. In response to a memory access request issued by the normal core, the hierarchical cache system determines whether the memory access request hits the isolated memory and, if yes, the hierarchical cache system rejects the memory access request.

Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.

Abstract: Circuitry, systems, and methods are provided for an integrated circuit device including a memory storing a data structure, a cache storing a portion of the structure data, and an acceleration function unit providing hardware acceleration for a host device. The acceleration function unit may provide the hardware acceleration by intercepting a request from the host device to access the memory, where the request comprises an address corresponding to a data node of the data structure, identifying a next data node based at least in part on decoding the data node, and loading the next data node into the cache for access by the host device.

Abstract: Circuitry, systems, and methods are provided for an integrated circuit including an acceleration function unit to provide hardware acceleration for a host device. The integrated circuit may also include interface circuitry including a cache coherency bridge/agent including a device cache to resolve coherency with a host cache of the host device. The interface circuitry may also include cacheline state tracker circuitry to track states of cachelines of the device cache and the host cache. The cacheline state tracker circuitry provides insights to expected state changes based on states of the cachelines of the device cache, the host cache, and a type of operation performed.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: In a data processing system comprising a first cache operable to store data for use when performing a data processing operation, and a second cache operable to store data required for fetching data into the first cache from memory, when it is determined that there is no entry for data for a data processing operation in the first cache, an entry in the first cache is allocated for the required data, and information that indicates an entry in the second cache for data required for fetching the required data is stored in the tag portion of the allocated entry. Then, once a request has been sent to a memory system for the required data, the information in the tag portion for the allocated entry in the first cache that indicates an entry in the second cache is replaced with information indicative of an address for the data required for fetching the required data.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

Abstract: In end-to-end efficient encryption with security chaining a data source Information Handling System (IHS) encrypts a data volume, generates and updates metadata in a trailer of the data volume, and generates and updates out-of-band handshake signals indicating an encryption key use slot in the metadata. Data connection segments each include a left-bound interface of one IHS and a right-bound interface of another. Each interface performs synchronous data volume write-encrypt and read-decrypt functions on the data volume in an IHS, perform in-band encryption metadata processing, process out-of-band control signals, and execute an encryption configuration state machine, which uses the metadata and control signals as input to direct write-encrypt and read-decrypt functions on the data volume in the segment.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.

Abstract: A device includes a direct memory access (DMA) controller comprising DMA channels, a bridge circuit configured to couple the DMA channels to memory channels coupled to respective memory modules, and a local memory unit. The DMA controller is configured to transfer tensor data between the local memory unit and the memory modules via the DMA channels and the memory channels using concurrent data transactions, the tensor data is stored and addressed as parts of a single tensor in the local memory unit, and the tensor data is interleaved onto the memory modules and is stored and addressed as sub-tensors in respective memory modules.

Abstract: A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.