Abstract: The present disclosure relates to a kinetic inductance parametric amplifier that comprises an input port arranged to receive a pump tone, a DC bias and input signal; an output port arranged to provide an amplified version of the input signal; a tunable stepped-impedance assembly arranged to attenuate and/or filter predetermined frequency bands; and a high kinetic inductance line. The tunable stepped-impedance assembly is tuned at a frequency that allows for the amplifier to resonate at a predetermined frequency and a pump tone with a frequency higher than the input signal and a DC biasing signal to be transmitted to the high kinetic inductance line.

Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: A method of bidirectional amplification of proprietary TDMA (Time-Division Multiple Access) data modulated signals over CATV infrastructure is described. A method of upstream/downstream switching based on carrier detection/measurement originated from the master and slave modems embodiment is described, along with upstream/downstream direction switching based on the encoded switching command detection, originating from the master modem.

Abstract: A power amplifier includes: a power amplification circuit and a linearity compensation circuit; and herein the linearity compensation circuit is connected between a transistor amplification circuit and a biasing circuit of the power amplification circuit, to linearly compensate a nonlinear distortion of the power amplification circuit.

Abstract: A power amplifier circuit includes a first amplifier that amplifies a first RF signal and outputs a second RF signal, a second amplifier that amplifies the second RF signal and outputs a third RF signal, a bias circuit that supplies a bias current or voltage to the first or second amplifier, and a bias adjustment circuit that adjusts the bias current or voltage on the basis of the first RF signal, the second RF signal, or the third RF signal. The bias adjustment circuit includes a first diode having an anode to which a control signal indicating a signal based on the first, second, or third RF signal is inputted, and a cathode connected to a ground. The bias circuit includes a bias transistor that outputs the bias current or voltage on the basis of a voltage at the anode of the first diode.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A quantum parameter amplifier; the quantum parameter amplifier includes a capacitor module, a first microwave resonant cavity, and an inductance-adjustable superconducting quantum interference apparatus that are connected in sequence to constitute an oscillation amplifier circuit, wherein, the superconducting quantum interference apparatus is grounded; the quantum parameter amplifier further includes a voltage modulating circuit and/or a second microwave resonant cavity; one end of the voltage modulating circuit is connected with an end of the superconducting quantum interference apparatus that is close to the first microwave resonant cavity; and one end of the second microwave resonant cavity is connected with the end of the superconducting quantum interference apparatus that is close to the first microwave resonant cavity.

Abstract: An integrated system for hearing protection and enhancement having earpieces including microphones and receivers to provide for user control of ambience level (mic gain), monitor input, control over limiting of excessive levels, and frequency equalization, all with very wide input dynamic range capability and controlled output dynamic range. The user control comprises a wired or wireless smartphone app. Also, the wide input dynamic range is achieved by placement of limiter circuitry capable of handling the entire input dynamic range prior to the most dynamic range limited circuit blocks: digital EQ block, output amplifier, earpiece receiver, and the users' ears. Switches allow combining left and right signals to be directed to a user's favored ear, if necessary.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A Scalable Finite Impulse Response (“SFIR”) filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.

Abstract: A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the

Abstract: A SAW device manufacturing method includes a piezoelectric ceramic substrate polishing step of polishing a first surface of the piezoelectric ceramic substrate, a support substrate polishing step of polishing a first surface of the support substrate, a bonding step of bonding the first surface of the piezoelectric ceramic substrate to the first surface of the support substrate to thereby form a stacked substrate, a grinding step of grinding a second surface of the piezoelectric ceramic substrate, and a vibration diffusion layer forming step of applying a laser beam to the stacked substrate in the condition where the focal point of the laser beam is positioned inside the piezoelectric ceramic substrate to thereby form a modified layer as a vibration diffusion layer inside the piezoelectric ceramic substrate.

Abstract: Laser-marked packaged surface acoustic wave devices are provided. The laser-marked packaged surface acoustic wave device may include a package structure encapsulating a surface acoustic wave device on a first side of a piezoelectric substrate. The opposite side of the piezoelectric substrate can be directly marked using a laser. The laser may be a deep ultraviolet laser. By directly marking the piezoelectric substrate itself, the use of a separate marking film can be avoided, making the packaged surface acoustic wave device thinner. When the laser has a wavelength readily absorbed by the piezoelectric substrate, a relatively shallow marking may be made in the piezoelectric substrate. The markings can extend less than 1 micrometer into the piezoelectric substrate, so as not to affect the structural integrity of the piezoelectric substrate or the operation of the packaged surface acoustic wave device.

Abstract: This disclosure is directed to filtering in a transceiver of an electronic device. In some instances, active analog filters may be deployed in the transceiver of the electronic device to achieve greater linearity and/or reduce noise in the transceiver. However, as signal bandwidth grows increasingly larger, an active analog filter may consume excessive power. To remedy the excessive power consumption, a passive ladder LC filter may be used. Some LC ladder filters may include a limited quality factor (Q), which may lead to undesirable effects in the transceiver (e.g., voltage droop). To address these undesirable effects, certain components in the LC ladder filter may be relocated from an input port to a feedback chain of an amplifier coupled to the LC ladder filter. The new structure may enable components in the LC ladder filter to be tuned without causing additional voltage droop across the LC ladder filter.

Abstract: An apparatus includes a radio-frequency (RF) apparatus, and a multi-band matching balun coupled to the RF apparatus. The multi-band matching balun including a plurality of capacitors and a plurality of inductors. None of the plurality of capacitors and none of the plurality of inductors is variable or tunable.

Abstract: An acoustic wave filter device is disclosed. The device includes an acoustic wave filter element, and a first resonator and a second resonator coupled to the acoustic wave filter element. The acoustic wave filter element includes interdigited input electrodes and output electrodes located on a top surface of a piezoelectric layer. Each of the first and the second resonators includes a top electrode on the top surface, and a bottom electrode on the bottom surface of the piezoelectric layer. At least one of each of the first and the second resonators' electrodes is electrically connected to the acoustic wave filter element. The first resonator has a first notch in resonator impedance at a first frequency. The second resonator includes a first mass loading layer on the second resonator electrode such that the second resonator has a second notch in resonator impedance at a second frequency different from the first frequency.

Abstract: Aspects of this disclosure relate to an acoustic wave device that includes high velocity layers on opposing sides of a piezoelectric layer. A temperature compensation layer can be positioned between one of the high velocity layers and the piezoelectric layer. The acoustic wave device can be arranged to generate a boundary acoustic wave having a higher velocity than a respective acoustic velocity of each of the high velocity layers.

Abstract: In certain aspects, a chip includes a pad, and a first passivation layer, wherein a first portion of the first passivation layer extends over a first portion of the pad. The chip also includes a first metal layer between the first portion of the pad and the first portion of the first passivation layer. The chip further includes an under bump metallization (UBM) electrically coupled to a second portion of the pad.

Abstract: A surface acoustic wave device includes at least one transducer; two acoustic reflectors disposed on either side of the at least one transducer so as to form a cavity, each acoustic reflector comprising an array of electrodes in the form of lines parallel with each other, each array comprising a subset of electrodes connected to a reference potential denoted mass defining a first connection type, and a subset of electrodes that are not connected to any potential, i.e. that have a floating connection defining a second connection type; at least one switching circuit configured to modify the distribution of the connections of at least one part of the electrodes of each array between the different connection types.

Abstract: A resonance device is provided that includes a resonator including upper electrodes, a lower electrode, and a piezoelectric thin film formed therebetween. An upper cover is provided with a first surface facing the upper electrodes of the resonator. A power supply terminal is provided on a second surface of the upper cover with the power supply terminal electrically connected to the upper electrodes. Another power supply terminal is on the second surface of the upper cover and is electrically connected to the upper electrodes. A ground terminal is provided on the second surface of the upper cover and is electrically connected to the lower electrode. An area of each power supply terminal are different from one other such that a capacitance formed between the first power supply terminal and the ground terminal is approximately equal to a capacitance formed between the second power supply terminal and the ground terminal.

Abstract: Disclosed is a bulk acoustic wave resonator (BAWR). The BAWR includes a bulk acoustic wave resonance unit with a first electrode, a second electrode, and a piezoelectric layer. The piezoelectric layer is disposed between the first electrode and the second electrode. An air edge is formed at a distance from a center of the bulk acoustic wave resonance unit.

Abstract: A vibrator device includes a vibrator element, a container in which the vibrator element is housed, a circuit which is disposed in the container, and which overlaps the vibrator element in a plan view, and an inductor which is disposed in the container, which fails to overlap the vibrator element in the plan view, and which is electrically coupled to the circuit. The container includes at least a first member and a second member, and a bonding area configured to bond the first member and the second member to each other, and the inductor is disposed in the bonding area.

Abstract: A filter device has a first piezoelectric plate spanning a first and second cavity of a substrate. A first and second interdigital transducer (IDT) are on a front surface of the first piezoelectric plate over the first and second cavity. A dielectric layer is formed on the first piezoelectric plate and covers the first IDT and second IDT. A second piezoelectric plate is bonded to a front surface of the dielectric layer over the first cavity and the second cavity. A second dielectric layer is formed on a front surface of the second piezoelectric plate over the first cavity but not over the second cavity. The thickness of the dielectric layer, the first piezoelectric plate and the second piezoelectric plate can be selected to tune a shunt resonator over the first cavity and a series resonator over the second cavity.

Abstract: An improved electro acoustic RF filter (FC) is provided. The RF filter comprises an electro acoustic resonator (EAR) connected between an input port and an output port, an impedance element and a damping and/or dissipation element (DE) in mechanical contact to the impedance element. The damping and/or dissipation element is provided and configured to remove acoustic energy from the impedance element which has a similar construction as the resonator on the same substrate. With such a construction an acoustically inactive impedance element (AIIE) is obtained.

Abstract: Provided is a gate driving apparatus, including: a gate driving unit for driving a gate of a switching device; a switching unit for switching a gate current of the switching device during, within a turn-on period of the switching device, at least a part of the period, which is after timing when a current starts to flow in the switching device, to a smaller current when compared to the gate current before at least a part of the period.

Abstract: The invention relates to a device for controlling a plurality of semiconductor circuit breakers by means of driver voltages for the synchronous operation of a plurality of loads in the high-voltage range, where the driver voltages can be provided by a transformer. According to the invention, the driver voltages for the semiconductor circuit breakers are tapped from a single secondary winding of the transformer, where electronic voltage level converter circuits are provided to obtain the driver voltages from the secondary winding of the transformer at the required magnitude.

Abstract: According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.

Abstract: Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.

Abstract: A method for detecting contact with a manually activated steering or control device, in particular a vehicle steering wheel, comprises the following steps: applying an alternating voltage to at least one conductor arrangement (10) which is arranged on the steering or control device, and has at least one conductor line with a significant ohmic resistance; determining the current profile in the conductor arrangement (10); determining the real component and the virtual component of the instantaneous alternating current resistance of the conductor arrangement (10); determining the capacitance or the change in capacitance of the conductor arrangement (10); determining the phase shift; and evaluating the determined values.

Abstract: A circuit including: a transistor, a base of the transistor being switchably connectable to a signal source; and a first diode connected between the base and a reference voltage. The circuit is arranged such that when the signal source is not connected to the base of the transistor, a voltage applied at an emitter of the transistor causes a current flow through the base of the transistor and through the first diode such that the transistor is in an ON state, and when the signal source is connected to the base of the transistor, current flow through the base reduces such that the transistor switches to an OFF state. The circuit includes a second diode, and the signal source is connectable to the base of the transistor through the second diode.

Abstract: A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.

Abstract: Rapid-data-transfer sensor arrays include a controller and a plurality of sensor integrated circuits (ICs) connected in series and configured to periodically take measurements and provide measurement data to the controller as serial data. A sensor IC includes a transducer, a shift register, a serial-data-in (SDI) pin, a serial-data-out (SDO) pin, a clock pin, and a bi-directional start/done (ST/DN) pin. The sensor IC includes a power regulation circuit configured to selectively supply power for a sleep mode and an active mode for recording data and an internal shift register. When finished with the measurement, the sensor IC is configured to provide measurement data to the shift register for transfer to the controller. The controller is configured to initiate serial transfer of data from each of the shift registers of the first plurality of sensor ICs to the controller. Examples include a 2D array.

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: The present invention provides a Schmitt trigger circuit in which chattering does not occur in the output of the Schmitt trigger circuit even when it is connected to a communication bus without impedance matching and reflected noise is superimposed on the input signal. The Schmitt trigger circuit includes: a first signal detection circuit; a second signal detection circuit; a latch circuit; a selection signal generation circuit; a first input port; and a first output port. The first signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The second signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The latch circuit is connected to the selection signal generation circuit and the output port. The selection signal generation circuit includes a delay circuit.

Abstract: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.

Abstract: A signal generation apparatus is used in a ToF camera system especially adopting the indirect system and suppresses occurrence of a cyclic error. The signal generation apparatus includes a first pulse generator configured to generate a pulse to be supplied to a light source that irradiates light upon a distance measurement target, a second pulse generator configured to generate a pulse to be supplied to a pixel that receives the light reflected by the distance measurement target, and a signal selection section configured to select and output a duty cycle of a signal to be outputted from the first pulse generator from between a first duty cycle and a second duty cycle different from the first duty cycle.

Abstract: Provided is a thermostatic type crystal oscillator with short operation stabilization time and low power consumption. A thermostatic type crystal oscillator according to the present invention includes a crystal resonator including an IT-cut crystal blank, a vibration control circuit configured to control a vibration frequency of the crystal resonator, a temperature regulator configured to regulate a temperature of the crystal resonator within a set temperature range by repeating heating and cooling to the crystal resonator, a heat conducting plate configured to function as a heat absorbing plate and a heat dissipating plate for the temperature regulator, a temperature control circuit configured to control a temperature of the temperature regulator, and a housing that accommodates the crystal resonator. The housing defines a resonator accommodating space in which the crystal resonator is accommodated inside the housing.

Abstract: Provided are a differential signal skew calibration circuit and a semiconductor memory. The differential signal skew calibration circuit may acquire a phase relationship of a differential signals through a phase detection circuit. A phase adjustment control circuit may generate a phase calibration control instruction according to the phase relationship of the differential signals to control a phase calibration circuit to calibrate a phase skew of the input differential signals.

Abstract: An optical lattice clock includes a clock transition space having disposed therein an atom group trapped in an optical lattice, and a triaxial magnetic field correction coil for correcting the magnetic field of the clock transition space. Additionally, in a correction space that includes the clock transition space and is larger than the clock transition space, a photoreceiver promotes the clock transition of the atom group trapped in the optical lattice and acquires a clock transition frequency distribution for the correction space. Further, a corrector corrects the magnetic field of the triaxial magnetic field correction coil on the basis of the frequency distribution measured by the photo receiver.

Abstract: Techniques for facilitating analog-to-digital converter calibrations are provided. In one example, a method includes, for each of a plurality of time instances, generating a first ramp signal started at the time instance relative to a respective start of a first counter signal and generating a respective comparator output signal based on the first ramp signal and a first threshold signal. The method further includes capturing a respective first value of the first ramp signal in response to a transition of the respective comparator output signal. The method further includes determining a respective second counter value of a second counter signal based on the respective first value. The method further includes determining a scaling factor based on the second counter values and the time instances. Each of the first values is associated with the same counter value of the first counter signal. Related devices and systems are also provided.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

Abstract: An amplifier performs analog amplification on a signal I_A with a gain corresponding to a state GS and outputs the amplified signal as a signal M_A. An ADC converts the signal M_A to a digital signal and outputs the digital signal as a signal M_D. Analog comparators and a down-determination unit detect that the signal M_A exceeds a first level, and cause the state GS to transition to a state of gain of the next lower stage. Digital comparators and an up-determination unit detect that the signal M_D has been continuously lower than a second level for a predetermined period, and cause the state GS to transition to a state of gain of the next higher stage. The restoration circuit performs digital amplification on the signal M_D with a gain corresponding to the gain of the amplifier and outputs the amplified signal as a signal O_D.

Abstract: A team polar decoder (TPD) includes polar decoders (PPDs) connected to a channel, and a team decision maker (TDM) connected to the PPDs and a destination. Component polar decoders (CPDs) decode a polar code in accordance with a polar code. Each CPD receives a noisy code block (NCB) from the channel, and decodes the NCB in consecutive steps to obtain a decoded transform input block (DTIB). Each CPD is generates, at an end of the decoding step, a candidate decoded data block from the DTIB by a data-demapping operation that is an inverse of a data-mapping operation applied at a polar encoder, then sends the CDDB to the TDM, which receives the CDDBs from the PPDs, generates a decoded data block (DDB), and sends the DDB to the destination.

Abstract: Methods, systems and apparatus for correcting a result of a quantum computation.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: The disclosure relates to generating a polar code and also to encoding and decoding data using a polar code. A method of generating a polar code includes obtaining a first matrix as an m-fold Kronecker product of a 2×2 binary lower triangular matrix where m=log 2(M/2), M<N, and N is the length of a polar code to be generated. A second matrix may be obtained, where the inverse of the second matrix is a lower triangular band matrix. A transformation matrix may be generated for the polar code by calculating a Kronecker product of the second matrix with the first matrix. An information set I identifying reliable bit channels for the polar code may be determined. A polar codeword of length N may be obtained using the polar code that is decodable by iteratively applying a sliding decoding window of length M to the polar codeword.