Patents Issued in February 20, 2024
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Patent number: 11907526Abstract: A touch region adjustment method includes: determining a region on a touch display of a terminal device and in which a sensing parameter changes to determine a grasping gesture of a user for the terminal device; and adjusting a location of a touch response region on the touch display based on the grasping gesture of the user for the electronic device to avoid an accidental touch caused by the grasping gesture of the user for the screen of the terminal device.Type: GrantFiled: December 4, 2020Date of Patent: February 20, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Hang Li, Weigang Cai, Junyong Zhang
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Patent number: 11907527Abstract: The present disclosure is directed to positioning animated images within a dynamic keyboard interface. In particular, the methods and systems of the present disclosure can: receive, from a user device on which an application is executed, data indicating a context of: the application, and/or a dynamic keyboard interface provided in association with the application; identify, based at least in part on the data indicating the context, a plurality of different animated images, including an animated image comprising an advertisement, for presentation by the dynamic keyboard interface; communicate, to the user device, data indicating the plurality of different animated images; receive, from the user device, data indicating a selection of the animated image comprising the advertisement; and determine, based at least in part on the data indicating the selection and the data indicating the context, a position within the dynamic keyboard interface for presenting the animated image comprising the advertisement.Type: GrantFiled: March 24, 2023Date of Patent: February 20, 2024Assignee: GOOGLE LLCInventors: David McIntosh, Peter Chi Hao Huang, Erick Hachenburg, David Lindsay Bowen, Joseph Lieu, Kira Lee Psomas, Jason R. Krebs, Kumar Garapaty, Samantha Janelle Jiwei Lau
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Patent number: 11907528Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.Type: GrantFiled: July 20, 2021Date of Patent: February 20, 2024Assignee: Texas Instruments IncorporatedInventors: Kai Chirca, Daniel Wu, Matthew David Pierson
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Patent number: 11907529Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.Type: GrantFiled: February 15, 2022Date of Patent: February 20, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Sheng-Min Huang, Kuo-Hwa Ho, Shih-Ying Song
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Patent number: 11907530Abstract: Centralized quality-of-service (QoS) policies administration in a storage area network (SAN) is a problem without meaningful solutions. Current implementations require explicit administration of end points, which is error-prone and not scalable. Zoning for NVMe-oF is defined as a method to specify connectivity access control information on the Discovery Controller (DC) of an NVMe-oF fabric, not as a way to specify QoS policies. Embodiments comprise centrally specifying one or more QoS parameters as part of NVMe-oF zoning definitions maintained at an NVMe-oF DC to centrally controlled QoS parameters. Accordingly, embodiments provide mechanisms to specify QoS parameters in a centralized manner to eliminate requiring a system administrator having to perform per-connection QoS provisioning.Type: GrantFiled: March 25, 2022Date of Patent: February 20, 2024Assignee: DELL PRODUCTS L.P.Inventors: Claudio Desanti, Erik Smith
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Patent number: 11907531Abstract: Some techniques described herein relate to determining how to optimally store datasets in a multi-tiered storage device with compression. In one example, a method includes assigning, to a data partition of a dataset, a priority based on access patterns of the data partition. Compression data is accessed describing results of compressing a data sample associated with the data partition using multiple compression schemes. Based both on the priority of the data partition and the compression data, a storage tier is determined for storing the data partition in the multi-tiered storage device. Further, based both on the priority of the data partition and the compression data, a compression scheme is determined for compressing the data partition for storage in the multi-tiered storage device. The data partition is compressed using the compression scheme to produce a compressed data partition, and the compressed data partition is stored in the storage tier.Type: GrantFiled: June 28, 2022Date of Patent: February 20, 2024Assignee: Adobe Inc.Inventors: Raunak Shah, Koyel Mukherjee, Khushi, Kavya Barnwal, Karanpreet Singh, Harsh Kesarwani, Ayush Chauhan
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Patent number: 11907532Abstract: An initial drive cluster of G drives with G subdivisions is represented by a G*G drive matrix, where G equals the number of data and parity members in the RAID level implemented on the drive cluster. A corresponding G×G overlay matrix is created in which a value at row R, column C equals a remainder of (R+C?2) divided by G, such that there are G distinct values in a range of 0 to G?1. Responsive to addition of N new drives to the drive cluster, the N new drives are added to the drive matrix and the overlay matrix is used to select and relocate RAID members within the drive matrix so that new RAID groups can be created.Type: GrantFiled: November 10, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventor: Kuolin Hua
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Patent number: 11907533Abstract: An archiving apparatus that realizes high-speed seek processes and the like by setting a logical object table for each container file with a predetermined size, and closing the container file under a predetermined condition is provided. A data processing section that executes control of access to a recording medium generates a logical object table for managing a container file including logical objects which are recorded data units, and records the logical object table on a memory. In a case where a prescribed condition is satisfied, for example, the container file size has become equal to or larger than a prescribed end reference value, and so on, while a process on the container file is being executed, the logical object table is read out from the memory, and recorded on the recording medium, and the container file is closed.Type: GrantFiled: November 21, 2019Date of Patent: February 20, 2024Assignee: SONY GROUP CORPORATIONInventors: Hisao Tanaka, Tomotaka Kuraoka
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Patent number: 11907534Abstract: A storage device projected temperature environment configuration system includes storage devices with the same physical hardware configuration, and a computing device manufacturing system that manufactures computing devices.Type: GrantFiled: August 31, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Anthony Gerard Ginty, Gregory Martin Allen
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Patent number: 11907535Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured to optimize these different usage types upon detecting these proof of space blockchain activities. These optimizations can include suspending one or more background or other garbage collection activities. Additional optimizations can further include configuring partitions or namespaces to comprise single-level-cell majority or single-level-cell only memory devices to increase writing speeds. Further optimizations can include interleaving or extending the length of error correction codes.Type: GrantFiled: January 25, 2022Date of Patent: February 20, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, David Avraham, Alexander Bazarsky
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Patent number: 11907536Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.Type: GrantFiled: January 4, 2023Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
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Patent number: 11907537Abstract: First and second target controllers implemented in a storage system are associated with respective first and second storage pools having respective first and second service level objectives. Input-output (IO) operations are received from one or more host devices and processed in the storage system, with different ones of the IO operations being directed from one or more initiators of the one or more host devices to different ones of the first and second target controllers. Separate feedback information is provided from the storage system to the one or more host devices for respective ones of the first and second target controllers, so as to permit different amounts of throttling of additional IO operations in the one or more host devices based at least in part on whether those additional IO operations are to be directed to the first target controller or the second target controller.Type: GrantFiled: April 6, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Igor Achkinazi, Tal Abir
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Patent number: 11907538Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.Type: GrantFiled: October 7, 2022Date of Patent: February 20, 2024Assignee: Memory Technologies LLCInventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
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Patent number: 11907539Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.Type: GrantFiled: December 11, 2020Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jingpei Yang, Jing Yang, Rekha Pitchumani, YangSeok Ki
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Patent number: 11907541Abstract: Techniques for providing an adaptive approach to prefetching data for sequential read streams in a storage system. The techniques can include performing prefetch operations for a sequential read stream in accordance with a prefetch distance and a prefetch size, counting or otherwise keeping track of occurrences of failure scenarios in the prefetch operations while servicing the sequential read stream, and modifying or adjusting one of the prefetch distance and the prefetch size based on the occurrences of the respective failure scenarios. In this way, host input/output (IO) latency can be reduced, and IO bandwidth can be increased, in the servicing of sequential read streams by the storage system.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Andrew Feld, Philippe Armangau, Christopher A. Seibel, Christopher Jones
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Patent number: 11907542Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.Type: GrantFiled: December 9, 2022Date of Patent: February 20, 2024Assignee: MIPS Tech, LLCInventors: Sanjay Patel, Ranjit J. Rozario
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Patent number: 11907543Abstract: Provided are a computer program product, system, and method for managing swappable data structures in a plurality of memory devices based on access counts of the data structures. Data structures indicated as swappable are updated less frequently than most frequently updated data structures. Data structures not indicated as swappable are maintained in a first level memory device and not moved to a second level memory device. The first level memory device has lower latency than the second level memory device. Access counts are maintained for the data structures stored in the first level memory device that are indicated as swappable. Data structures are selected in the first level memory device having lowest access counts. The selected data structures are removed from the first level memory device and retained in the second level memory device.Type: GrantFiled: January 7, 2020Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew G. Borlick, Matthew Richard Craig
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Patent number: 11907544Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.Type: GrantFiled: August 27, 2021Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Hyun Yoo Lee, Kang-Yong Kim
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Patent number: 11907545Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: April 28, 2022Date of Patent: February 20, 2024Assignee: SanDisk Technologies LLCInventors: YenLung Li, Siddarth Naga Murty Bassa, Chen Chen, Hua-Ling Cynthia Hsu
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Patent number: 11907546Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.Type: GrantFiled: August 24, 2022Date of Patent: February 20, 2024Inventor: Dean D. Gans
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Patent number: 11907547Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.Type: GrantFiled: April 26, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Liang Yu, Jonathan S. Parry, Xiaojiang Guo
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Patent number: 11907548Abstract: A memory sub-system can allocate a first portion of blocks of a memory device for storage of file system metadata based on a file system and a capacity of the memory device, write video data received from a host within a second portion of the blocks at a first data density, and write file system metadata within the first portion of the blocks at a second data density lesser than the first data density.Type: GrantFiled: July 17, 2020Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventor: Minjian Wu
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Patent number: 11907549Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.Type: GrantFiled: June 24, 2021Date of Patent: February 20, 2024Assignee: QUALCOMM IncorporatedInventors: Muthu Manikandan Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
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Patent number: 11907550Abstract: A method for dynamically assigning memory bandwidth to multiple processor units, which are connected via a data connection to a shared memory unit. In an initialization phase, each of the multiple processor units are assigned an initial value of a usable memory bandwidth, and a permissible range for a mean usage of the memory bandwidth is determined. Subsequently, the assigned memory bandwidths are checked repeatedly and adjusted if needed, a present value of a mean usage of the memory bandwidth by the multiple processor units being determined, and, if this present value is outside the permissible range, the values of the usable memory bandwidth are adjusted for at least a part of the multiple processor units.Type: GrantFiled: November 22, 2021Date of Patent: February 20, 2024Assignee: ROBERT BOSCH GMBHInventors: Ahsan Saeed, Dakshina Narahari Dasari, Falk Rehm, Michael Pressler
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Patent number: 11907551Abstract: Storage volumes are pre-provisioned in the operating system of a storage system before they are required to be assigned to an emulation on the storage system. Details of the previously created storage volumes are stored in a management database. If a storage volume is required, the process that needs the storage volume obtains details about a pre-provisioned storage volume from the management database, and instructs the storage system operating system to add the storage volume to a storage group for the process. By pre-provisioning storage volumes in the operating system, it is possible to greatly reduce the amount of time it takes to add storage volumes to processes. The number of storage volumes to be pre-created can be determined based on a regression between the previous storage volume usage and time, and a deterministically obtained value of a number of filesystems that will be created in an upcoming time interval.Type: GrantFiled: July 1, 2022Date of Patent: February 20, 2024Assignee: Dell Products, L.P.Inventors: Maneesh Singhal, Venu Madhava Gunda
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Patent number: 11907552Abstract: Techniques for extending a storage system having a first pool involve adding, in response to a request, second storage devices, wherein the first pool is generated using first storage devices and based on a first standard. The first pool includes first stripes created using the first standard, and the number of the second storage devices equals a first stripe width associated with the first standard. Such techniques further involve creating a second pool using the second storage devices and based on a second standard, wherein a second stripe width associated with the second standard equals the first stripe width. Such techniques further involve creating second stripes in the second pool using the second storage devices and based on the second standard. Such techniques further involve storing data of at least one of the first stripes to a corresponding stripe of the second stripes according to a data shuffle rule.Type: GrantFiled: August 18, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Sheng Wang, Dapeng Chi, Wen Jiang, Yang Song, Yi Wang
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Patent number: 11907553Abstract: In an embodiment, a storage device is provided. A device controller with a memory is coupled with the storage device. The memory stores an application with instructions that direct the controller to receive a storage device policy. The instructions further direct the controller to store content from a storage request in accordance with the storage device policy, and record storage information, including at least a content identifier, to the memory. Subsequent to storing the content, the instructions further direct the controller to retrieve the content according to the storage information received in a storage request. According to an implementation, the instructions further provide instruction to refuse a delete request in accordance with the storage information. According to an implementation, the instructions provide direction to store the storage information at a remote location.Type: GrantFiled: April 8, 2022Date of Patent: February 20, 2024Assignee: Gaea LLCInventors: Joshua Johnson, Curt Bruner, Jeffrey Reh, Christopher Squires, Brian Wilson
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Patent number: 11907554Abstract: A method and apparatus for controlling startup of a hard disk drive system, and a storage device. The hard disk drive system includes two or more hard disk drives. The method for controlling startup of a hard disk drive system includes: latching the initialization states of all the hard disk drives after all hard disk drives are powered on; dividing all hard disk drives into two or more hard drive groups, each hard drive group includes more than one hard disk drive; sequentially perform link initialization negotiation on each hard drive group by using a port protocol; and in an OOB negotiation process of the link initialization negotiation, by setting the state of an SCSI application layer power state machine, control a motor of each hard disk drive in the hard drive group to enter a spinning state.Type: GrantFiled: February 23, 2021Date of Patent: February 20, 2024Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Yunwu Peng, Yu Zou, Xuezong Yang, Hui Tian
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Patent number: 11907555Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: November 18, 2022Date of Patent: February 20, 2024Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 11907556Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: GrantFiled: January 20, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Patent number: 11907557Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.Type: GrantFiled: February 25, 2022Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Susanne M. Balle, Francesc Guim Bernat, Slawomir Putyrski, Joe Grecco, Henry Mitchel, Evan Custodio, Rahul Khanna, Sujoy Sen
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Patent number: 11907558Abstract: A method comprises receiving an input specifying one or more rules in connection with archiving one or more of a plurality of files from a source storage location to a target storage location. The one or more rules specify one or more constraints for retention of the one or more of the plurality of the files. In the method, the one or more of the plurality of files are retrieved from the source storage location for migration to the target storage location. A request is sent to the target storage location that the target storage location invoke the one or more rules to retain the one or more of the plurality of files in the target storage location. The target storage location comprises a cloud storage platform.Type: GrantFiled: July 8, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Rabi Shankar Shaw, Anurag Bhatnagar, Akash Gosain
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Patent number: 11907559Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Itay Admon, Uri Kaluzhny, Nir Tasher
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Patent number: 11907560Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.Type: GrantFiled: October 26, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventor: Joseph Thomas Pawlowski
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Patent number: 11907561Abstract: This application provides a data backup method. The method includes: obtaining, by a first node, an identifier of a backup execution node from a storage device; and backing up data of the first node in the storage device responsive to determining that an ID of the first node is the same as the ID of the backup execution node. The embodiments of this application can improve reliability of the data stored by the first node, and prevent a plurality of nodes from redundantly backing up duplicate data in the storage device. The techniques disclosed herein reduce resource consumption.Type: GrantFiled: July 14, 2020Date of Patent: February 20, 2024Assignee: Huawei Cloud Computing Technologies Co., Ltd.Inventors: Xionghui He, Chen Ding, Di Yao
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Patent number: 11907562Abstract: In one embodiment, a method comprises maintaining state information regarding a data replication status for a storage object of the storage node of a primary storage cluster with the storage object being replicated to a replicated storage object of a secondary storage cluster, temporarily disallowing input/output (I/O) operations when the storage object has a connection loss or failure. The method further includes initiating a resynchronization between the storage object and the replicated storage object including initiating asynchronous persistent inflight tracking and replay of any missing I/O operations that are missing from one of a first Op log of the primary storage cluster and a second Op log of the secondary storage cluster, and allowing new I/O operations to be handled with the storage object of the primary storage cluster without waiting for completion of the asynchronous persistent inflight tracking and replay at the secondary storage cluster.Type: GrantFiled: July 11, 2022Date of Patent: February 20, 2024Assignee: NetApp, Inc.Inventors: Krishna Murthy Chandraiah Setty Narasingarayanapeta, Akhil Kaushik
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Patent number: 11907563Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.Type: GrantFiled: September 8, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Yueh-Hung Chen, Chih-Kuo Kao, Ying Yu Tai, Jiangli Zhu
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Patent number: 11907564Abstract: A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.Type: GrantFiled: August 3, 2021Date of Patent: February 20, 2024Assignee: YADRO INTERNATIONAL LTD.Inventor: Viacheslav Dubeyko
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Patent number: 11907565Abstract: A method, computer system, and a computer program product for storing a write data in a storage system that operates using a log-structured filing system is provided. The present invention may include compressing a write data. The present invention may also include identifying a region of a storage system based on a first size of the compressed write data. The present invention may further include the storage system operating using a log-structured filing system. The present invention may also include a different region of the storage system having a different compression ratio. The present invention may further include writing the compressed write data in the identified region of the storage system.Type: GrantFiled: April 14, 2020Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gareth Paul Jones, Ben Sasson, Lee Jason Sanders, Gordon Douglas Hutchison
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Patent number: 11907566Abstract: Methods for use in a dispersed storage network (DSN) to coordinate execution of tasks by storage units of the DSN. In an embodiment, a computing device of the DSN receives a task (e.g., a maintenance task) to be performed by at least one storage unit of a plurality of storage units. The computing device determines the availability of processing resources of the storage units for execution of the received task. The computing device further compares the respective availability of the processing resources of the storage units of the plurality of storage units to identify a storage unit for execution of the received task, and allocates the received task to the identified storage. In various embodiments, comparing the respective availability of the processing resources includes predicting an impact, with respect to other storage units of the DSN, of performing the received task on the identified storage unit.Type: GrantFiled: August 31, 2020Date of Patent: February 20, 2024Assignee: PURE STORAGE, INC.Inventor: Patrick A. Tamborski
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Patent number: 11907567Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory. The controller is configured to specify a partition format of a predetermined partition included in the non-volatile memory based on master boot record information stored in the non-volatile memory. The controller is configured to specify a file system that manages the predetermined partition. The controller is configured to specify logically erased first data and physically erase the first data when logical erasure of data in the predetermined partition is detected by a method consistent with the specified file system.Type: GrantFiled: September 13, 2021Date of Patent: February 20, 2024Assignee: Kioxia CorporationInventor: Tadashi Nagahara
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Patent number: 11907568Abstract: An operation method of a storage device includes receiving a first write request; adding the first write request to a first fragment; selecting at least “n” (e.g., at least two) streams among a plurality of pre-allocated streams when a size of the first fragment, when a size of the first fragment is >=a reference value, based on a cosine similarity between the first fragment and each of the pre-allocated streams; applying input information to a machine learning model to detect a first sequential stream associated with the first fragment from among the at least “n” streams; allocating a stream identifier of the first sequential stream to the first fragment; and storing write data included in the first fragment based on the stream identifier of the first sequential stream. The input information includes statistical information of at least one of the “n” streams and the first fragment.Type: GrantFiled: October 14, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kibeen Jung, Seungjun Yang, Byeonghui Kim, Jungmin Seo, Jaewoong Kim, Hyeongyu Min
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Patent number: 11907569Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.Type: GrantFiled: September 19, 2022Date of Patent: February 20, 2024Assignee: Radian Memory Systems, Inc.Inventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
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Patent number: 11907570Abstract: Methods, systems, and devices for predictive media management for read disturb are described. A read disturbance manager can monitor a bit error rate for a block of a memory die. The read disturbance manager can detect that a degradation of the bit error rate satisfies a degradation threshold specific to the memory die. In some cases, the read disturbance manager can perform a write operation to write data from the block of the memory die to a second block of the memory die based on detecting that the degradation of the bit error rate satisfies the degradation threshold.Type: GrantFiled: February 25, 2020Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventor: Daniel James Gunderson
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Patent number: 11907571Abstract: A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for decoded data of each read operation, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.Type: GrantFiled: July 13, 2020Date of Patent: February 20, 2024Assignee: SK hynix Inc.Inventors: Fan Zhang, Aman Bhatia, Haobo Wang
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Patent number: 11907572Abstract: An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.Type: GrantFiled: July 14, 2020Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventor: Yue Chan
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Patent number: 11907573Abstract: A SD Card including, in one implementation, a memory array, a controller coupled to the memory array, and a bus for transferring data between the memory array and a host device in communication with the SD Card. The controller is configured to perform background maintenance operations on the memory array during execution of a read command received from the host device.Type: GrantFiled: June 21, 2021Date of Patent: February 20, 2024Assignee: Western Digital Technologies, Inc.Inventors: Pradeep Sreedhar, Deepak Naik, Bala Siva Kumar Narala, Abhishek Shetty
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Patent number: 11907574Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.Type: GrantFiled: July 22, 2021Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Umberto Siciliani, Floriano Montemurro
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Patent number: 11907575Abstract: A memory controller includes: a first buffer configured to receive a memory request from a host and store therein the received memory request; a command generator configured to generate a first command corresponding to the memory request, and set a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory; a second buffer configured to store therein a plurality of commands comprising the first command; and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.Type: GrantFiled: September 23, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hosang Yoon, Seungwon Lee
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Patent number: 11907576Abstract: A method for communicating with at least one field device via an interface device, wherein each field device is connected to a channel of the interface device, where the method includes receiving a first command associated with a first field device, from an industrial device, communicating with the first field device over a first communication channel for executing the received first command, receiving at least one command associated with the at least one field device, from the industrial device, the at least one commands including at least one command associated with a second field device from the at least one field device, and caching the at least one command in a memory module prior to the execution of the first command.Type: GrantFiled: November 16, 2021Date of Patent: February 20, 2024Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Eric Chemisky, Siva Prasad Katru, Huai Shen Chen, Vishal S