Patents Issued in February 20, 2024
  • Patent number: 11910712
    Abstract: The present application relates to a compound represented by Chemical Formula 1, an organic optoelectronic diode and a display device.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 20, 2024
    Assignee: LT MATERIALS CO., LTD.
    Inventors: Hye-Su Ji, Seong-Jong Park, Won-Jang Jeong
  • Patent number: 11910713
    Abstract: The present disclosure provides a thermoelectric conversion material having a composition represented by a chemical formula of Li2?a+bMg1?bSi. In this thermoelectric conversion material, either requirement (i) in which 0?a?0.0001 and 0.0001?b?0.25-a or requirement (ii) in which 0.0001?a?0.25 and 0?b?0.25-a is satisfied. The thermoelectric conversion material has an Li8Al3Si5 type crystalline structure.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: February 20, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiromasa Tamaki, Yuriko Kaneko, Hiroki Sato, Tsutomu Kanno, HyunJeong Nam
  • Patent number: 11910714
    Abstract: A thermoelectric conversion material contains a matrix composed of a semiconductor and nanoparticles disposed in the matrix, and the nanoparticles have a lattice constant distribution ?d/d of 0.0055 or more.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 20, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro Adachi, Makoto Kiyama, Yoshiyuki Yamamoto, Ryo Toyoshima
  • Patent number: 11910715
    Abstract: A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has multiple grounding electrodes, grounding pads located at its edges, and a polymer thin film including multiple areas each covering only one grounding electrode. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a shadow mask below the poling source, and a Z-elevator to raise the workpiece carrier toward the shadow mask and poling source. When the workpiece in the workpiece carrier is raised to contact the underside of the shadow mask, multiple openings of the shadow mask expose only the corresponding multiple thin film areas of the workpiece to the plasma; meanwhile, conductive grounding terminals on the underside of the shadow mask electrically connect the grounding pads of the workpiece with carrier electrodes on the workpiece carrier, to ground the workpiece.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 20, 2024
    Assignee: CREESENSE MICROSYSTEMS INC.
    Inventors: Albert Ting, Hongwei Lu, Kai-An Wang
  • Patent number: 11910716
    Abstract: An apparatus includes an ultrasonic sensor stack, a foldable display stack that includes a display stiffener, and an additional stiffener between the ultrasonic sensor stack and the foldable display stack. The additional stiffener forms an acoustic resonator with the display stiffener and an adhesive layer between the display stiffener and the additional stiffener in order to amplify transmission of ultrasonic waves transmitted by the ultrasonic sensor stack. The additional stiffener includes a material having a high modulus of elasticity, low density, and high acoustic impedance value. In some cases, the additional stiffener includes a metal, a ceramic, a glass, or a glass ceramic. The additional stiffener increases an overall stiffness and mechanical integrity of the apparatus so that a foam backer may be omitted from the ultrasonic sensor stack.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: February 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Jen Tseng, Jessica Liu Strohmann, Ila Badge, Shiang-Chi Lin, Min-Lun Yang, Hrishikesh Vijaykumar Panchawagh
  • Patent number: 11910717
    Abstract: A piezoelectric actuator includes an electrode layer including a trunk portion and a plurality of branch portions branched from the trunk portion. The trunk portion includes a plurality of junction points from each of which a corresponding branch portion of the plurality of branch portions are branched, an end spaced from the plurality of junction points, and a second through hole positioned between the plurality of junction points and the end of the trunk portion. A plurality of first through holes are grouped into a first group and a second group. The first group overlaps, in a first direction, a particular area defined between the end of the trunk portion and the second through hole and the second group overlaps, in the first direction, another particular area defined between the second through hole and the plurality of junction points.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 20, 2024
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Keiji Kura, Takashi Aiba
  • Patent number: 11910718
    Abstract: A piezoelectric thin film element having a first electrode, a second electrode and a piezoelectric thin film between the electrodes, wherein the thin film comprises a laminate having two or more piezoelectric thin film layers and wherein a first thin film layer is doped by one or more dopants and a second film layer is doped by one or more dopants and wherein at least one dopant of the second thin film layer is different from the dopant or dopants of the first thin film layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: February 20, 2024
    Assignee: Xaar Technology Limited
    Inventors: Peter Mardilovich, Susan Trolier-McKinstry
  • Patent number: 11910719
    Abstract: Provided is a piezoelectric film capable of realizing a piezoelectric speaker in which a high sound pressure is obtained, a sufficient sound pressure characteristic is obtained in a wide frequency band, and generation of a chattering sound particularly in a low sound can be suppressed. The piezoelectric film is a piezoelectric film including a polymer-based piezoelectric composite material which contains piezoelectric particles in a matrix containing a polymer material, and electrode layers which are laminated on both surfaces of the polymer-based piezoelectric composite material, in which a variation coefficient of a destructive force of a laminate having the polymer-based piezoelectric composite material and the electrode layers in a plane direction is 0.25 or less.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: February 20, 2024
    Assignee: FUJIFILM Corporation
    Inventor: Shingo Fujikata
  • Patent number: 11910720
    Abstract: Provided is a piezoelectric device and an MEMS device whose size can be reduced. The piezoelectric device includes: a first substrate that includes a first surface on which a piezoelectric element and a first electrode coupled to the piezoelectric element are disposed; a second substrate that includes a second surface on which a second electrode configured to be coupled to a control circuit is disposed; and a third substrate that is disposed between the first substrate and the second substrate, and includes a third surface bonded to the first surface and a fourth surface facing the second surface, in which the third substrate has a through hole passing through from the third surface to the fourth surface, and a third electrode provided in the through hole and coupled to the first electrode, and the second electrode is coupled to the third electrode and is electrically coupled to the first electrode via the third electrode.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 20, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Eiji Osawa, Hikaru Iwai
  • Patent number: 11910721
    Abstract: The invention comprises a method of forming a novel magnetic pinning structure having a (100) textured or cube-textured reference layer through a non-epitaxial texturing approach so that an excellent coherent tunneling effect is achieved in a pMTJ element due to its texture structure of CoFe BCC (100)/MgO rocksalt (100)/CoFe BCC (100). Correspondingly, a high MR ratio and a high pinning strength on the reference layer can be achieved for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 20, 2024
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11910722
    Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Chih-Chao Yang
  • Patent number: 11910723
    Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ku-Feng Lin
  • Patent number: 11910724
    Abstract: A substantially anhydrous thickener system in the form of a gel for use in oral care compositions comprising: carboxymethyl cellulose or its salts thereof, a chelating agent, and hydroxyethyl cellulose, in a solvent system, wherein the thickener system is heated to a temperature ranging from about 70° C. to about 120° C. to form the gel. A method of preparing the thickener system for use in oral care compositions comprises the steps of: a) charging a mixture of hydroxyethyl cellulose and carboxymethyl cellulose into a reaction container, b) dissolving the mixture of a) in a solvent system, c) charging a chelating agent into b), and d) heating the resultant of c) to a temperature of 70°-120° C. for at least about 10 minutes.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: February 20, 2024
    Assignee: ISP INVESTMENTS LLC
    Inventors: Philip John Oths, Shafiq Sahar Wahidi, Petros Gebreselassie, Hani M. Fares
  • Patent number: 11910725
    Abstract: The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO3 (STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 20, 2024
    Assignees: IMEC VZW, Katholieke Universiteit Leuven
    Inventors: Bart Vermeulen, Mihaela Ioana Popovici, Koen Martens, Gouri Sankar Kar
  • Patent number: 11910726
    Abstract: A vapor deposition reactor apparatus, systems and methods for deposition of thin films, particularly high-temperature superconducting (HTS) coated conductors, utilize multi-sided susceptors and susceptor pairs for increased production throughput. The reactors may also be configured in multi-stack arrangements of the susceptors within a single reactor chamber for additional throughput gains.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: February 20, 2024
    Assignee: MetOx International, Inc.
    Inventors: Shahab Khandan, Nagaraja Shashidhar, Mikhail Novozhilov
  • Patent number: 11910727
    Abstract: An ultra-thin film superconducting tape and method for fabricating same is disclosed. Embodiments are directed to a superconducting tape being fabricated by processes which include removing a portion of the superconducting tape's substrate subsequent the substrate's initial formation, whereby a thickness of the superconducting tape is reduced to 15-80 ?m.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 20, 2024
    Assignee: University of Houston System
    Inventor: Venkat Selvamanickam
  • Patent number: 11910728
    Abstract: Methods, devices, and systems are described for performing quantum operations. An example device at least one magnetic field source configured to supply an inhomogeneous magnetic field, at least one semiconducting layer, and one or more conducting layers configured to: define at least two quantum states in the at least one semiconducting layer, and cause, based on an oscillating electrical signal supplied by the one or more conducting layers, an electron to move back and forth between the at least two quantum states in the presence of the inhomogeneous magnetic field. The movement of the electron between the at least two quantum states may generate an oscillating magnetic field to drive a quantum transition between a spin-up state and spin-down state of the electron thereby implementing a qubit gate on a spin state of the electron.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 20, 2024
    Assignee: The Trustees of Princeton University
    Inventors: Jason Petta, Stefan Putz, Xiao Mi
  • Patent number: 11910729
    Abstract: A superconducting current limiter having at least one superconducting conductor (3) wound so as to form a coil (2) extending in a single plane and connecting a first electrical connection terminal to a second electrical connection terminal, an electrically insulating spacer (8) being arranged between two turns of the coil. The superconducting conductor (3) consists of at least two separate superconducting cables (5) wound in parallel and whose ends are electrically connected by the first electrical connection terminal and by the second electrical connection terminal, respectively. An electrically conductive spacer (12) is arranged between two of said separate superconducting cables (5), this electrically conductive spacer (12) being able to be traversed by a cooling fluid.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 20, 2024
    Assignees: Supergrid Institute, Institut Polytechnique De Grenoble
    Inventors: Pierre Legendre, Pascal Tixador
  • Patent number: 11910730
    Abstract: A superconducting circuit having a Josephson junction includes a first electrode layer for signal transmission; a second electrode layer for signal transmission; and an insulating layer arranged between the first electrode layer and the second electrode layer to form a Josephson junction, wherein, the first electrode layer and the second electrode layer are composed of a preset material, the insulating layer is composed of a compound corresponding to the preset material, and the preset material includes a non-aluminum superconducting material to prolong a coherence time of superconducting qubits.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Xiaohang Zhang, Wenlong Yu, Hsiang-Sheng Ku, Jingwei Zhou
  • Patent number: 11910731
    Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Philip Joseph Oldiges, Robert L. Bruce, Ching-Tzu Chen
  • Patent number: 11910732
    Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 11910733
    Abstract: A method includes forming a bottom electrode, forming a dielectric layer, forming a Phase-Change Random Access Memory (PCRAM) region in contact with the dielectric layer, and forming a top electrode. The dielectric layer and the PCRAM region are between the bottom electrode and the top electrode. A filament is formed in the dielectric layer. The filament is in contact with the dielectric layer.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sheng-Chih Lai
  • Patent number: 11910734
    Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari