Abstract: A data center cabinet has a base frame with a pair of front vertical posts, first bottom and top side-to-side beams connected to the front vertical posts, a pair of back vertical posts, second bottom and top side-to-side beams connected to the back vertical posts, and front-to-back beams connecting the front vertical posts and back vertical posts. The first and second bottom side-to-side beams each comprise an opening configured to allow a removable transport caster to pass through the opening, a first set of keyholes configured to receive and retain a set of mounting buttons of a first removable transport caster, and a second set of keyholes configured to receive and retain a set of mounting buttons of a second removable transport caster.

Abstract: A crossbar is provided that is operable to be removably installed in a sled for a modular server and/or information handling system, for example a network equipment building system. The crossbar includes a frame, a keystone portion of the frame forming a keystone air duct, and a riser guide extending from the frame. The keystone portion is operable to direct air flow through the keystone air duct towards a heat sink and/or a CPU. The riser guide is operable to align a riser to be plugged into a motherboard installed in the sled. The frame is operable to be a structural component that is substantially coupled to the sled chassis.

Abstract: Aspects of the present disclosure relate to a cooled wireless mobile device charger. As an example, a cooling enclosure is provided, comprising a cooling surface. The cooling enclosure may shield a mobile device therein from direct sunlight or other adverse conditions, thereby reducing the heat exposure of the device. The cooling surface may comprise a thermoelectric cooling element or any of a variety of other cooling means. Additionally, the cooling surface may be angled about a lateral axis to enable a user to more easily view at least a part of the mobile device (e.g., in a landscape or portrait orientation) while the device is in the cooling enclosure. In some instances, a detachable visor is provided that further shields the mobile device from sunlight. As another example, the visor may retract within the cooling enclosure.

Abstract: A cooling plate includes a fluid inlet port, a cooling enclosure, and an inlet channel coupled between the fluid inlet port and the cooling enclosure to channel a two-phase fluid entering from the inlet port to the cooling enclosure. The cooling enclosure includes a number of heat spreading structures coupled to an inner surface of the cooling enclosure to form spacings, where the two-phase fluid in contact with the heat spreading structures causes portions of the two-phase fluid to change into a vapor phase. The cooling plate includes an extended vapor channel coupled to the cooling enclosure to collect the two-phase fluid in vapor phase. The cooling plate includes a vapor outlet port coupled to the extended vapor channel for the two-phase fluid in vapor phase to exit the vapor outlet port, where the cooling plate is submersible in an immersion tank containing a single-phase immersion fluid.

Abstract: A computing device comprises a housing, a heat-generating electronic component, at least one additional electronic component, and a liquid cooling module. The heat-generating component, the at least one additional electronic component, and the liquid cooling module are all positioned inside the housing. The liquid cooling module is configured to cool the heat-generating electronic component, and includes at least one movable radiator. The at least one movable radiator is configured to move between a first position and a second position. When the at least one movable radiator is in the first position, the at least one movable radiator blocks access to the at least one additional electronic component within the housing. When the at least one movable radiator is in the second position, the at least one movable radiator allows access to the at least one additional electronic component within the housing.

Abstract: A liquid cooling device includes a thermally conductive base, a cover, and a metallic partition. The thermally conductive base has a fluid chamber and a plurality of fins. The fins are located in the fluid chamber and protrudes from an inner surface of the thermally conductive base facing the fluid chamber. Every two of the fins located adjacent to each other define a channel therebetween. Distal ends of at least part of the fins located away from the inner surface together form a covering structure partially coving the channels. The metallic partition is located between and welded to the covering structure and the cover.

Abstract: A cooling liquid flow control device includes a heat dissipation bottom plate, a fixing holder, a cooling module, and a temperature control element. The heat dissipation bottom plate has a bottom surface configured to be in contact with a heating element on a substrate. The fixing holder is connected to the heat dissipation bottom plate and configured to be fixed with the substrate. The cooling module is connected to a top surface of the heat dissipation bottom plate to form a cavity. The cavity is configured to circulate a cooling liquid. The temperature control element is connected to the cooling module and includes a valve. The valve is configured to rotate based on a temperature of the heating element, thereby adjusting a flow rate of the cooling liquid in and out of the cavity.

Abstract: A commonly designed processor heat exchanger decouples the mounting hardware used to mount the heat exchanger to a processor from the heat exchanger itself. This allows a single heat exchanger design to be mounted to various different types of processors using processor customized mounting brackets that engage with flanges extending out from a body of the heat exchanger.

Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.

Abstract: In one or more embodiments, an apparatus includes a substrate and die package, a thermal transfer plate positioned adjacent to the substrate and die package for cooling the substrate and die package, wherein at least one electrical path extends through the thermal transfer plate for transmitting power from a power module to the substrate and die package, and a microelectromechanical system (MEMS) module comprising a plurality of air movement cells for dissipating heat from the thermal transfer plate.

Abstract: A heat sink is provided. The heat sink includes a cylindrical body and a plurality of fins. The fins are connected to and protruding from the cylindrical body. At least a part of the plurality of fins each include a first protrusion portion and a second protrusion portion, a distal edge of the first protrusion portion is located farther away from a central axis of the cylindrical body than a distal edge of the second protrusion portion. In addition, the disclosure also provides a heat dissipation device having the heat sink.

Abstract: A heat sink structure that is used for audio equipment includes a base and a plurality of heat dissipation fins. The heat dissipation fins extend from a predetermined surface of the base in a first direction orthogonal to the predetermined surface. The heat dissipation fins are arranged side by side in a second direction orthogonal to the first direction. In a cross-section in a plane parallel to the first and second directions, (i) each of the heat dissipation fins has a first side surface and a second side surface, the first and second surfaces facing oppositely from each other in the second direction, and (ii) inclinations, relative to the predetermined surface, of the first and second side surfaces of adjacent ones of the heat dissipation fins are different from each other.

Abstract: The present invention relates to a housing part, a housing and an electronic device. The housing part according to this invention comprises a first layer, said first layer being molded from a first composition comprising a1) 50-90 wt. % of a first amorphous polymer and b1) 10-50 wt. % of a first thermally conductive filler, the first composition having a thermal conductivity (TC1) of 4-40 W/(m*K), a second layer, said second layer being molded from a second composition comprising a2) 50-90 wt. % of a second amorphous polymer and b2) 10-50 wt. % of a second thermally conductive filler, the second composition having a thermal conductivity (TC2) of 0.

Abstract: A thermal management system for use in a sealed communications module and associated systems and methods are disclosed herein. In some embodiments, the communications model includes a sealed housing and a circuit board assembly having one or more heat-generating electronic components positioned within the housing. The thermal management system is coupled to the circuit board assembly and positioned to disperse heat from the one or more electronic components. The thermal management system includes a first thermal pathway, a second thermal pathway, and a third thermal pathway. The first thermal pathway has a first end attached to the circuit board assembly and a second end positioned near the side wall of the housing. The second thermal pathway is coupled to the second end of the first thermal pathway. The third thermal pathway is coupled to the second end of the first thermal pathway.

Abstract: A mechanical device for cooling an electronic component may include a surface including an aperture, and a first support protruding from the surface and a second support protruding from the surface. In some embodiments, the device may include disposed within the aperture a thermal interface material (TIM).

Abstract: A heat dissipation unit includes a main body having a first and a second plate member, which are closed to each other to together define an airtight chamber in between them. A working fluid is filled in the airtight chamber. A first wick structure layer and a holding-down member are provided between the first and the second plate member and received in the airtight chamber. The holding-down member is located above the first wick structure layer, such that the first wick structure layer is held down by the holding-down member to be closely and flatly attached to the second plate member without warping.

Abstract: A source module includes a server fluid distribution unit and a busbar unit, as well as connectors. In an embodiment, a server fluid distribution unit to be coupled to a rack fluid distribution unit and the one or more server blades for deploying one or more servers. In an embodiment, a busbar unit to be coupled with an alternating current (AC) power distribution unit and the one or more server blades. In an embodiment, the source module is to be coupled to the rack fluid distribution unit to distribute cooling fluid received from a cooling fluid source to the one or more server blades of corresponding server chassis and to extract heat from the one or more servers.

Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, an absorption chiller includes a generator vessel to enable removal of heat from fluid returned from at least one computing component of the datacenter.

Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a hybrid coolant distribution unit (HCDU) provides first stage cooling of secondary coolant returning from at least one cold plate in a liquid to air heat exchanger (L2AHE) and provides second stage cooling in a liquid to liquid heat exchanger (L2LHE) for secondary coolant exiting an L2AHE using varying flow rates of a primary coolant based in part on a residual temperature that is determined for such secondary coolant exiting an L2AHE.

Abstract: One general aspect includes a hybrid thermal management system for vehicle electronics. The hybrid thermal management system also includes a bottom piece being injection molded and may include of polymer, the bottom piece may include a plurality of coolant channels, an input port and an output port. The hybrid thermal management system also includes a thermal plate covering the bottom piece and the plurality of coolant channels and configured to dissipate thermal energy from a vehicle high performance computing (HPC) to a coolant within the plurality of coolant channels. The hybrid thermal management system also includes the input port configured to supply the coolant to the plurality of coolant channels. The hybrid thermal management system also includes the output port configured to collect coolant from the plurality of coolant channels and convey thermal energy away from the system.

Abstract: A conversion device converts an input power into an output power, and gives rise to a power loss. The conversion device is cooled by a coolant circuit in which a coolant flows. A monitoring device determines, using operating data of the conversion device and/or of the coolant circuit, a flow velocity of the coolant and compares the flow velocity with a limit velocity. If the flow velocity reaches or exceeds the limit velocity, the monitoring device resorts to a special reaction. As long as the flow velocity does not reach the limit velocity, the monitoring device resorts either to no reaction or to a normal reaction that is not the same as the special reaction. The monitoring device determines the flow velocity by using a quantity of heat that is to be removed by the coolant per unit time, a local temperature of the conversion device, and an inflow temperature.

Abstract: A power conversion device includes: a housing; and a cover coupled to the housing, the cover includes a plate portion, a heat conduction portion coupled to the plate portion, and a refrigerant pipe, the plate portion includes a first groove in which the refrigerant pipe is disposed, and the depth of one end of the first groove is smaller than that of the other end.

Abstract: A display device includes a display panel including a first non-folding region, a folding region, and a second non-folding region sequentially arranged along a first direction, a first plate disposed under the display panel, a heat dissipation layer disposed under the first plate, and a first adhesive layer disposed between the first plate and the heat dissipation layer. The first adhesive layer includes a first sub adhesive layer overlapping the first non-folding region, and a second sub adhesive layer overlapping the second non-folding region, the first sub adhesive layer and the second sub adhesive layer are spaced apart from each other in the first direction, and a width of a first gap by which the first sub adhesive layer and the second sub adhesive layer are spaced apart is in a range of about 9 millimeters (mm) to about 12 mm.

Abstract: An outdoor display apparatus comprises a case including an inlet and an outlet, a display module disposed inside the case and including a display panel on which an image seen through at least a portion of the case is displayed, and a heat exchanger. The heat exchanger comprises a first portion located on a first flow path formed to circulate air to the display module, a second portion to receive heat from the first portion, and located on a second flow path on which outside air is heat-exchanged with air, and a phase change material provided to circulate between the first and second portions, and provided to change a phase from a fluid to a gas. The case comprises a partition wall provided to isolate the first flow path and the second flow path from each other, and the first portion and the second portion are disposed obliquely.

Abstract: An electromagnetic wave absorption structure includes at least one electromagnetic wave composite absorbing layer. The electromagnetic wave composite absorbing layer includes a conductive composite layer and an insulating layer. The insulating layer is stacked and overlapped with the conductive composite layer. The electromagnetic wave absorption structure can provide good electromagnetic wave absorption function, and have the features of light and thin, so it is particularly suitable for satisfying the electromagnetic wave absorption or shielding requirements of thin electronic products.

Abstract: The present application relates to a composite material. The present application can provide a composite material having high magnetic permeability and also having excellent mechanical properties such as flexibility. The composite material may be used in various applications, and for example, may be used as an electromagnetic-wave shielding material and the like.

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

Abstract: An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells.

Abstract: A capacitor may include a lower electrode, a dielectric layer structure on the lower electrode, and an upper electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers. The insert layer structure may include a plurality of zirconium oxide layers and at least one insert layer. The insert layer may be between ones of the plurality of zirconium oxide layers. The capacitor may have a high capacitance and low leakage currents.

Abstract: A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Abstract: A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer.

Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

Abstract: Provided herein are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an etch stop pattern having a top surface and a sidewall disposed over a gate stack having interlayer insulating layers alternately stacked with conductive patterns. The semiconductor device also includes a plurality of channel structures passing through the etch stop pattern and the gate stack. The semiconductor device further includes an insulating layer extending to cover the top surface and the sidewall of the etch stop pattern, wherein a depression is included in a sidewall of the insulating layer. The semiconductor device additionally includes a contact plug passing through the insulating layer so that the contact plug is coupled to a channel structure of the plurality of channel structures.

Abstract: A semiconductor storage includes a stack, columns, and first, second, third, fourth, and fifth insulators. The stack includes first conductive layers, and second and third conductive layers below and above the first conductive layers, respectively. The columns penetrate the stack in a first direction. The first and second insulators penetrate the stack and are separated from each other in a second direction. The third insulator is between the first and second insulators in a third direction. The third insulator includes first and second portions apart from each other in the second direction. The fourth insulator is between the first and second portions. The fifth insulator is between the first and second portions above the fourth insulator. The second conductive layer includes two electrically-separated regions, between which the third and fourth insulators are provided. The third conductive layer includes two electrically-separated regions between which the third and fifth insulators are provided.

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.