Patents Issued in March 12, 2024
  • Patent number: 11927593
    Abstract: The present invention is methods and assays for identifying single proteins from a sample, without the use of affinity reagents. The methods and assays combine endopeptidase-based component of conventional peptide mapping with single molecule labeling and a microreactor array platform. The invention also includes kits for performing the methods and assays.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 12, 2024
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventor: Peter A. Sims
  • Patent number: 11927594
    Abstract: The present disclosure describes a method of quantifying amounts of phosphopeptides using isotopically-enriched peptides as internal standards. A kit comprising at least one isotopically-enriched phosphorylated peptide can be used to quantify changes in amounts of phosphopeptides using parallel reaction monitoring mass spectrometry techniques. The invention can be used to indicate the pathologic mechanism, severity of the disease, and treatment response of a subject. The invention can also be used to identify subjects who require more aggressive therapeutic interventions or alternative treatments.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 12, 2024
    Assignee: RENSSELAER CENTER FOR TRANSLATIONAL RESEARCH, INC.
    Inventor: Lawrence S. Zisman
  • Patent number: 11927595
    Abstract: Disclosed is the invention to conduct immuno-adsorption of free 25(OH) vitamin D from blood or blood components, notably serum or plasma, after which the absorbed material is measured. A fluoro-alkyl surfactant is used to enhance the solubility of Vitamin D and allow the measurement of free Vitamin D2. The invention thus employs a binding protein to absorb the free 25(OH) vitamin D. Thereafter the binding protein comprising the 25-OH vitamin D is subjected to a competitive binding assay with a labeled vitamin D compound, preferably radiolabeled, fluorescent labeled, luminescent labeled, biotin labeled, gold labeled or enzyme labeled. Alternatively the immunocaptured 25-OH vitamin D can be quantitated by mass spectrometry.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: March 12, 2024
    Assignee: FUTURE DIAGNOSTICS B.V.
    Inventors: Michaƫl Franciscus Wilhelmus Cornelis Martens, George Henry Parsons, Franciscus Maria Anna Rosmalen, Leon Maria Jacobus Wilhelmus Swinkels
  • Patent number: 11927596
    Abstract: Methods and kits for detecting antibodies (e.g., anti-drug antibodies). Such methods and kits permit the detection of, for example, anti-drug antibodies in human body fluids, such as blood, plasma and serum.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 12, 2024
    Assignee: GENZYME CORPORATION
    Inventors: Ryan Grabert, Susan Richards, Valerie Theobald, Yuanxin Xu, Jad Zoghbi
  • Patent number: 11927597
    Abstract: A laboratory sample vessel distribution system is presented. The system comprises a cabinet, sample vessel carriers for receiving sample vessels, and a cabinet drawer for receiving a sample vessel carrier. The drawer is locatable in different positions: closed, opened, and fully opened. An actuator moves the sample vessels and the sample vessel carriers between different locations. An actuator driver drives the actuator and applies a first mode of operation with a first speed and a second mode of operation with a second reduced speed compared to the first speed. A sensor device detects between opened and closed positions and provides position signals. A control device is connected to the actuator driver and the sensor device. The control device provides control signals to the actuator driver instructing the actuator driver to apply either the first mode, if in the closed position, or the second mode, if in the opened position.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Roche Diagnostics Operations, Inc.
    Inventors: Andreas Schesny, Vladimirs Leontjevs
  • Patent number: 11927598
    Abstract: An analyzer system for in vitro diagnostics includes a sample handler module having a robot arm that delivers samples from drawers into carriers on a linear synchronous motor automation track. Samples are delivered via the automation track to individual track sections associated with individual analyzer modules. Analyzer modules aspirate sample portions directly from the sample carriers and perform analysis thereon.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: March 12, 2024
    Assignee: Siemens Healthcare Diagnostics Inc.
    Inventors: David Stein, Roy Barr, Mark Edwards, Colin Mellars, Thomas J. Bao, Charles V. Cammarata, Benjamin S. Pollack, Baris Yagci, Beri Cohen
  • Patent number: 11927599
    Abstract: Included are: a main body including an installation part in which a cartridge housing a liquid for treating a test substance contained in a specimen is installed and a detector configured to detect the test substance treated with the liquid within the cartridge installed in the installation part; a lid part arranged rotatably on the main body about a shaft so as to open and close the installation part; a biasing part biasing the lid part in an opening direction; and a plurality of regulators each generating resistance against a biasing force in the opening direction at different timing during an opening motion of the lid part.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 12, 2024
    Assignees: JVCKENWOOD Corporation, SYSMEX CORPORATION
    Inventors: Masahiro Yamamoto, Shigeru Yokota, Hideki Samata, Tomoyuki Nose, Sayuri Tomoda
  • Patent number: 11927600
    Abstract: A fluidic bridge device for transport of a fluid sample between a first sample processing device and a second sample processing device. The fluidic bridge may include one or more fluid channels extending between fluid-tight couplings attachable to transfer ports of the first and second sample processing device. In one aspect the first device is a sample preparation device and the second device is an assay device. The fluidic bridge can include at least two fluid conduits, at least one for transport of the prepared sample, and at least one other to facilitate displacement of air to allow flow of the prepared sample through the other fluid conduit. The fluid channels can include one or more of an amplification chamber, a processing chamber, a gas-permeable vent, a bubble trap, a filter, and an external port. Methods of preparing and transporting a fluid sample between devices are provided herein.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 12, 2024
    Assignee: Cepheid
    Inventor: Douglas B. Dority
  • Patent number: 11927601
    Abstract: A method for energy-efficient state change detection and classification of streaming sequential data includes receiving via a first prediction model, sequential data from a sensor. The first prediction model determines a change in an activity state based on the sequential data. An indication that the activity state has changed is transmitted to a second prediction. The second prediction model determines an updated activity state based on the sequential data. The updated activity state is sent to the first prediction model, after which the second prediction enters an inactive state.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Diyan Teng, Junsheng Han, Raehan Ahmed Syed, Rashmi Kulkarni
  • Patent number: 11927602
    Abstract: The present disclosure provides a radio frequency thimble for production testing, in engagement connection with a test socket. The radio frequency thimble comprises: a housing, a probe, a light transmission member, and a color recognition sensor. The probe is located in a cavity of the housing. An accommodation hole is provided in the probe. The light transmission member is installed in the accommodation hole. A first end of the light transmission member is exposed at an end portion of the probe. A second end of the light transmission member is connected to the color recognition sensor. The light transmission member is used to transmit, to the color recognition sensor, light reflected by a reflective surface near the end portion of the probe. The color recognition sensor is used to recognize the color of the reflected light and determine whether the end portion of the probe is aligned with a terminal.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 12, 2024
    Assignee: SPREADTRUM COMMUNICATIONS (SHENZHEN) CO., LTD.
    Inventor: Chuan He
  • Patent number: 11927603
    Abstract: Probes that define retroreflectors, probe systems that include the probes, and methods of utilizing the probes. The probes include the retroreflector, which is defined by a retroreflector body. The retroreflector body includes a first side, an opposed second side, a tapered region that extends from the first side, and a light-receiving region that is defined on the second side. The probes also include a probe tip, which is configured to provide a test signal to a device under test (DUT) and/or to receive a resultant signal from the DUT. The retroreflector is configured to receive light, via the light-receiving region, at a light angle of incidence. The retroreflector also is configured to emit at least an emitted fraction of the light, from the retroreflector body and via the light-receiving region, at a light angle of emission that is at least substantially equal to the light angle of incidence.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: March 12, 2024
    Assignee: FormFactor, Inc.
    Inventors: Quan Yuan, Joseph George Frankel
  • Patent number: 11927604
    Abstract: A wafer probe test system having a probe card with a probe head, a rotary magnet, a magnetic sensor positioned to sense the magnetic field of the rotary magnet and a controller coupled to the probe card, where the probe head has probe needles to engage features of test sites of a wafer in a wafer plane of orthogonal first and second directions, and the rotary magnet is rotatable around an axis of a third direction to provide a magnetic field to the wafer, in which the controller includes a model of magnetic flux density in the first, second and third directions at the respective test sites of the wafer as a function of a rotational angle of the rotary magnet, a probe needle height along the third direction and a measured magnetic flux density of the magnetic sensor.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xinkun Huang, Dok Won Lee, Christopher Michael Ledbetter, Bret Alan Dahl, Roy Deidrick Solomon
  • Patent number: 11927605
    Abstract: A test and measurement instrument switch matrix including a first cable including a center conductor and a guard connected to a first output of the test and measurement instrument; a second cable including a center conductor and a guard connected to a second output of the test and measurement instrument; a third cable including a center conductor and a guard connected to the device under test; and a fourth cable including a center conductor connected to the device under test and a guard connected to the device under test.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 12, 2024
    Assignee: Keithley Instruments, LLC
    Inventor: Gregory Sobolewski
  • Patent number: 11927606
    Abstract: A sensor device includes a silicon substrate having an active surface; a first sensing area disposed near a first edge of the active surface of the silicon substrate such that the first sensing area has at least one first magnetic sensing element is made of a first compound semiconductor material and contact pads; and a second sensing area disposed near a second edge of the active surface of the silicon substrate, such that the second edge is substantially opposite to the first edge, such that the second sensing area has at least one second magnetic sensing element made of a second compound semiconductor material and contact pads. A processing circuit is disposed of in the silicon substrate and is electrically connected via wire bonds and/or a redistribution layer with the contact pads of the first and second sensing areas.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: March 12, 2024
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Lucian Barbut, Francis Monchal, Simon Houis, Lionel Tombez
  • Patent number: 11927607
    Abstract: A rate of change of current sensor includes two measurement coils, arranged on a substrate or printed circuit board. The coils form loops and progress substantially around a target measurement conductor. This ensures that the two measurement coils both receive the same electrostatic coupling from external conductors which are not the target of the measurement operation. Further, the two measurement coils are arranged such that the first coil and the second coil are, on average, the same distance to the current-carrying conductor of interest.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 12, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Brent William Hoffman, Jonathan Ephraim David Hurwitz
  • Patent number: 11927608
    Abstract: The present disclosure relates to an AC/DC closed-loop current sensor, including a magnetism gathering iron core, a TMR chip, a signal processing circuit, a signal generator, and a feedback coil. The TMR chip is arranged at an air gap of the magnetism gathering iron core and connected to the signal processing circuit. The signal processing circuit is connected to the signal generator. The feedback coil is wound around the magnetism gathering iron core and connected to the signal generator. The signal processing circuit is configured to select from the induced signal of the TMR chip and make an amplification to obtain a current signal component and send the current signal component to the signal generator. The signal generator is configured to adjust a current output to the feedback coil based on the current signal component, and output a measurement result of the selected current signal component.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: March 12, 2024
    Assignee: DIGITAL GRID RES. INST., CHINA SOUTHERN PWR. GRID
    Inventors: Peng Li, Qiancheng Lv, Bing Tian, Xiaopeng Fan, Zhong Liu, Zhiming Wang, Renze Chen, Jie Wei, Xu Yin, Zejie Tan, Zhenheng Xu, Senjing Yao, Licheng Li, Yuehuan Lin, Shengrong Liu, Bofeng Luo, Jiaming Zhang
  • Patent number: 11927609
    Abstract: Disclosed are various embodiments for an anomaly detection system for detecting and identifying anomalies in electrical devices based on an energy profile associated with the electrical devices. Energy profile data associated with electrical devices or components in a power network can be obtained using an energy meter. The energy profile data can be analyzed to determine one or more conditions of the electrical devices. An anomaly of the electrical devices can be determined based on the energy profile data and conditions. Further, a root cause of the anomaly can be determined.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 12, 2024
    Assignee: UNIVERSITY OF GEORGIA RESEARCH FOUNDATION, INC.
    Inventors: WenZhan Song, Yang Shi, Fangyu Li, Jin Ye
  • Patent number: 11927610
    Abstract: A system includes a processor operatively coupled to memory. The processor performs operations that include obtaining electrical measurements of a power system. The processor determines a scaled energy value of a first set of the electrical measurements that are scaled with respect to a second set of electrical measurements. The processor determines that a potential ringdown event occurred by comparing the scaled energy value to a threshold energy value. The processor determines that the potential ringdown event is a confirmed ringdown event by comparing a scaled error value to a threshold error value. The processor generates one or more mode estimates from the confirmed ringdown event.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Md Arif Khan, Riley Grant Huddleston, Gregary C. Zweigle
  • Patent number: 11927611
    Abstract: A system includes a sensor configured at a first position to sense an orientation of an electricity meter. The electricity meter can be configured at a second position. The electricity meter can be configured at a normal orientation to measure delivered energy sent to one or more locations and received energy received from the one or more locations. The electricity meter can be configured at an inverted orientation to identify and measure the delivered energy sent to the one or more locations and the received energy received from the one or more locations. The sensor is configured to identify when the electricity meter is in the normal orientation, and when the electricity meter is in the inverted orientation. A display is configured within the electricity meter.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 12, 2024
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Mark Alan Ranta, Dacon Thomas Chow, Michael Anthony Murphy, William Egolf
  • Patent number: 11927612
    Abstract: A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: March 12, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ernest Knoll, Omer Yassur
  • Patent number: 11927613
    Abstract: A sheet electrical resistance measuring device includes: a housing having a gap for receiving a sheet therein; a sheet pulling member comprising a first and second rotating rollers that are disposed in the housing and pulls the sheet inserted into the gap; a stopper that is disposed in the housing and causes the sheet pulling member to stop pulling the sheet; and a pair of electrodes that is disposed in the housing and measures electrical resistance of the sheet which is stopped and brought into contact with the pair of electrodes. The sheet electrical resistance measuring is capable of reducing the likelihood of wrinkles to be occurred when inserting the sheet, thereby increasing measurement accuracy of the sheet electrical resistance measuring device.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 12, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Kouhei Yukawa, Kenta Ogata
  • Patent number: 11927614
    Abstract: According to various embodiments of the disclosure, disclosed is an antenna chamber which includes a mounting part to receive an external electronic device including an antenna module including a plurality of radiators to radiate a millimeter wave signal, a lens spaced apart from the mounting part to refract the millimeter wave signal radiated from the antenna module, an antenna spaced apart from the lens in a direction opposite to a direction of the mounting part to receive the millimeter wave signal refracted from the lens, and a lens driving unit to move the lens based at least on a first direction, which is set, such that the millimeter wave signal set to be radiated in the first direction from an external electronic device is refracted toward the antenna. Moreover, various embodiments found through the disclosure are possible.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Youngmin Lee, Jooseung Kim, Yongjun An
  • Patent number: 11927615
    Abstract: A measuring device 1 includes a DUT scanning mechanism 56 that is provided in the OTA chamber 50, includes a biaxial positioner which can be rotationally driven by drive motors 56f and 56g, and rotates a DUT 100 to sequentially face all preset directions of a spherical coordinate system; an integrated control device 10 that measures the DUT 100 at each measurement position corresponding to each of the all directions; and a rotation speed management control unit 18b that controls a rotation speed of the drive motors 56f and 56g at a rotation speed which shortens a time required for the movement in a case where the biaxial positioner is moved at a unit step angle from a measurement position where the measurement is completed to a measurement position where next measurement is performed during the DUT 100 is measured.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 12, 2024
    Assignee: ANRITSU CORPORATION
    Inventors: Hideyuki Endo, Hironori Watanabe, Takumi Nakamura, Yui Yoshida
  • Patent number: 11927616
    Abstract: A method for measuring alpha particle emissions may include obtaining a wafer emission rate, wherein the wafer emission rate is measured with a counter. The method may further include covering the wafer with a metal mesh grounded to a cathode of the counter wherein the metal mesh is grounded to the cathode outboard of the wafer and obtaining a mesh and wafer emission rate, wherein the mesh and wafer emission rate is measured with the counter. The method may further include replacing the wafer with a wafer carcass, obtaining a wafer carcass and mesh emission rate, and calculating a wafer carcass emissivity.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Gordon, Kenneth P. Rodbell, Conal Murray
  • Patent number: 11927617
    Abstract: There is provided an apparatus (20) for monitoring a condition of an electrical power transmission medium (22), the apparatus (20) comprising: a signal source (24) for transmitting a signal (30) to travel along the electrical power transmission medium (22); and a monitoring device (26) configured to detect one or more reflected signals (34) in the electrical power transmission medium (22), wherein the monitoring device (24) is configured to use the or each detected reflected signal (34) to determine a change in capacitance of the electrical power transmission medium (22).
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 12, 2024
    Assignee: General Electric Technology GMBH
    Inventors: Robert Stephen Whitehouse, Rosemary King
  • Patent number: 11927618
    Abstract: A method of predicting a lifetime of a gas filling of an electrical switchgear is disclosed, wherein pressure values p1, p2 in a system of the electrical switchgear containing the gas filling at a predefined temperature Tp at different points in time t1, t2 are measured. Based on the pressure difference ?p between the pressure values p1, p2 the lifetime of the gas filling is calculated. Alternatively, the pressure values p1, p2 can be taken at temperatures T1, T2 within a predefined temperature range at different points in time t1, t2.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: March 12, 2024
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Elise Morskieft, Marcel Van Dijk, Vijay Kumar, Yogesh Rajwade
  • Patent number: 11927619
    Abstract: Power semi-conductor module (1) comprising: —at least one IGBT with a Gate G forming a first electrode (11) and an Emitter E forming a second electrode (12), or —at least one MOSFET with a Gate G forming a first electrode (11) and a Source S forming a second electrode (12). The first electrode (11) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (13). The monitoring portion (13) is in electrical contact with the second electrode (12) such that a leakage current flows between the first electrode (11) and the second electrode (12) in an operational state of the module (1). The monitoring portion (13) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module (1).
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 12, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Nicolas Degrenne
  • Patent number: 11927620
    Abstract: Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Hongxiang Li, Shih-Shin Wang
  • Patent number: 11927621
    Abstract: Cryogenic testing systems for testing electronic components such as wafers under cryogenic conditions are provided. The novel designs enable fast throughput by use of a cryogenically maintained test surface to which wafers may be rapidly introduced, cooled, and manipulated to contact testing elements while maintaining high quality cryogenic conditions. Thermal shielding is achieved by floating shields and/or flexible bellows that provide effective thermal shielding of the test environment while enabling manipulation of wafers with a wide range of motion. Also provided are novel door assemblies, chuck configurations, and vacuum plate bases that enable effective maintenance of cryogenic conditions and high throughput.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 12, 2024
    Assignee: High Precision Devices, Inc.
    Inventors: Michael Snow, Joshua West
  • Patent number: 11927622
    Abstract: An abnormality resulting from connection between a plurality of substrates is easily detected in a semiconductor device including a multilayer semiconductor substrate. The semiconductor device includes a plurality of semiconductor substrates, a connection member, a power supply terminal, and an observation terminal. The connection member is electrically connected on joint surfaces of the plurality of semiconductor substrates to form at least one connection line that extends over the plurality of semiconductor substrates. The power supply terminal is connected to one end of the connection line, and the observation terminal is connected to the other end of the connection line. Power is supplied to the power supply terminal. The observation terminal is used to observe a resistance state of the connection line.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 12, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masashi Tokunaga
  • Patent number: 11927623
    Abstract: A semiconductor test device may include a chamber, a plurality of slots, a plurality of test boards and a plurality of temperature control modules. The slots may be arranged in the chamber. The test boards may be inserted into a part of the slots. The test boards may be configured to receive a plurality of semiconductor devices. The temperature control modules and the test boards may be alternately inserted into other parts of the slots. The temperature control modules may be configured to provide each of the test boards with air having a set temperature.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Nack Hyun Kim
  • Patent number: 11927624
    Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Harsh Patel, Aalok Dyuti Saha, Sanjeev Praphulla Chandra Nyshadham, Subrato Roy, Gaurav Kumar Mittal
  • Patent number: 11927625
    Abstract: A voltage contrast defect analysis method including the following steps is provided. A voltage contrast defect detection is performed on a die to be tested by using an electron beam inspection machine to find out a defect address of a voltage contrast defect. A first scanning electron microscope image at the defect address of the die to be tested is obtained by using a scanning electron microscope. A first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested is measured. The first critical dimension on the die to be tested is compared with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 12, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yue-Ying Yen
  • Patent number: 11927626
    Abstract: In an inspection device, the reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The removal processing section performs, based on the reference signal, processing for removing a noise component, which is due to the output of the external power supply device from the current signal output from the semiconductor sample and outputs a processing signal. The electrical characteristic measurement section measures the electrical characteristics of the semiconductor sample based on the processing signal. The processing signal is subjected to the removal processing performed based on the reference signal from the reference signal output section for which the value of the gain has been set by the gain setting section.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 12, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Toshiki Yamada
  • Patent number: 11927627
    Abstract: A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Tektronix, Inc.
    Inventors: Daniel S. Froelich, Sam J. Strickling
  • Patent number: 11927628
    Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chu-Feng Liao, Hung-Ping Cheng, Yuan-Yao Chang, Shuo-Wen Chang
  • Patent number: 11927629
    Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: March 12, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Pandy Kalimuthu, Anthony Joseph Lell
  • Patent number: 11927630
    Abstract: An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: March 12, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventor: Sounil Biswas
  • Patent number: 11927631
    Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 12, 2024
    Assignee: MORNINGCORE TECHNOLOGY CO., CHINA
    Inventors: Shanzhi Chen, Guobin Su, Yun Yang
  • Patent number: 11927632
    Abstract: A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: March 12, 2024
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventors: Chang-Qing Mu, Yuan Sang, Xue-Shan Han
  • Patent number: 11927633
    Abstract: A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Kawoosa, Pervez Garg, Prateek Giri
  • Patent number: 11927634
    Abstract: A method and a memory device are provided. Data is obtained for a scan operation at an input buffer of a scan kernel in the memory device. The input buffer is adaptable to a first mode and a second mode of the scan kernel. Preprocessing of the data from the input buffer is performed to generate preprocessed data. A different type of preprocessing is performed for the first mode and the second mode. The preprocessed data is filtered to generate a filtered result. The filtered result is provided from the scan kernel to a controller of the memory device.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Andrew Chang, Jingchi Yang, Vinit Apte, Brian Luu
  • Patent number: 11927635
    Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 12, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keyur Payak, Naveen Thomas
  • Patent number: 11927636
    Abstract: A diagnostic device and method diagnoses damage to a breaker that interrupts a current of an energy storage device. The damage to the breaker is diagnosed on the basis of a short-circuit current at a time of an external short circuit. The damage to the breaker can also be diagnosed on a basis of a short-circuit current during a first time from detection to interruption of a short circuit, and a short-circuit current during a second time from the interruption to convergence of the short-circuit current. An energy storage apparatus can include the diagnostic device.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 12, 2024
    Assignee: GS YUASA INTERNATIONAL LTD.
    Inventor: Yuki Imanaka
  • Patent number: 11927637
    Abstract: A sump, ejector, or other pump monitor configured to monitor the amperage of electric current power supplied through the pump monitor to a pump and communicate one or more signals regarding the amperage or variations in amperage to a remote signal receiving device which indicate a predicted failure or actual failure of the pump. In various embodiments, the pump monitor operates with a remote pump failure warning system. The remote signal receiving device or remote pump failure warning system provides suitable warnings to one or more user access devices.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 12, 2024
    Assignee: RF Group LLC
    Inventor: Michael B. Rothbart
  • Patent number: 11927638
    Abstract: A method for detecting a hardware configuration of a device intended to be carried aboard an aircraft turbomachine and controlled by a two-channel protection calculator (8), comprising a power supply able to supply the device, a first measuring box (16) able to measure a first voltage Vs1 at the output of the device and a second measuring box (18) capable of measuring a second voltage Vs2 at the output of the device: a) Send a control voltage to the input of the equipment Vc; b) Measure the first voltage Vs1 and the second voltage Vs2; c) Infer the hardware configuration of the device from the values of the first and second voltages measured Vs1 and Vs2.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 12, 2024
    Assignee: SAFRAN AIRCRAFT ENGINES
    Inventors: Jacques Paul Michel Gauvrit, Davy Philippe Masson
  • Patent number: 11927639
    Abstract: The application provides a high-voltage interlocking device and method for detecting the high-voltage interlocking device. The high-voltage interlocking device includes a first resistance module; a first switch module, a second connection end of the first switch module being connected to a first reference potential through a third resistance module, and a control terminal of the first switch module being configured to receive a first driving signal, to enable the first switch module to be turned on or off; a second resistance module, another end of the second resistance module being connected to a second reference potential; a fourth resistance module; a second switch module, a second connection end of the second switch module being connected to a third reference potential through a fifth resistance module; a fault detection module, configured to determine a fault of the high-voltage component underdetection according to a first detection signal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 12, 2024
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Weiqiang Li, Yanhui Fu, Xingchang Wang, Changjian Liu
  • Patent number: 11927640
    Abstract: An electronic device according to various embodiments of the present invention includes: a memory which stores one or more mapping parameters that indicate the correlation between a voltage change amount and the state of health (SOH) of the battery; and a processor, wherein the processor can be set to: detect that an external device for charging the battery is connected to the electronic device; charge the battery by using a charging current supplied from the external device; decide on at least one mapping parameter among the one or more mapping parameters on the basis of at least the charging current; check the voltage change amount of the battery while the battery is being charged; and acquire the SOH of the battery at least partially on the basis of the at least one mapping parameter and the voltage change amount.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seongho Han, Bookeun Oh, Gilho Kim, Junyoung Oh, Sungun Wi, Jaeyeon Lee
  • Patent number: 11927641
    Abstract: Provided is a battery pack in which the voltage of each battery cell is monitored using an inexpensive general-purpose microcomputer. A battery pack comprises: a plurality of battery cells connected in series; a plurality of voltage detection units which detect the voltage of each of the battery cells; and a microcomputer which measures the voltages of the battery cells from the output of each of the voltage detection units. Switch control circuits for switching on or off the outputs from the voltage detection units to the microcomputer are respectively arranged on each of the voltage detection units. Voltage divider circuits dividing the detected voltages into voltages lower than or equal to the power supply voltage of a control unit are arranged on the output sides of the voltage detection units. The microcomputer inputs the voltages divided by the voltage divider circuits and measures the voltages of the battery cells.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 12, 2024
    Assignee: Koki Holdings Co., Ltd.
    Inventor: Yuki Horie
  • Patent number: 11927642
    Abstract: An open cell detection method includes: (a) generating a control signal by a control unit, to turn on a first balance switch for a first time period; (b) generating the control signal with the control unit, to turn off the first balance switch for a second time period; (c) measuring a voltage value on a first capacitor, with a measure unit; (d) if the voltage value on the first capacitor is less than an open cell threshold, then determining with the control unit that the first cell has an open cell failure; (e) for each cell of the cells, repeating steps (a)-(d); and (f) if at least one cell of the cells has an open cell failure, then determining with the control unit that the battery management system has an open cell failure.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 12, 2024
    Assignee: O2Micro Inc.
    Inventors: Yingguo Zhang, Weidong Xue, Xiaojun Zeng