Patents Issued in March 12, 2024
  • Patent number: 11927998
    Abstract: A power adapter provides power to an information handling system. The power adapter includes a power supply and a power delivery controller. The power supply receives an alternating current (AC) input at one of a plurality of input voltages, and provides a direct current (DC) output at one of a plurality of output voltages, each output voltage being associated with a current limit.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Andrew Sultenfuss, Adolfo Montero, Karun P. Reddy
  • Patent number: 11927999
    Abstract: A process includes an application layer of a host of a computer platform using a smart network interface card (NIC) of the computer platform to provide an input/output (I/O) service for the application layer. The I/O service includes a service that is associated with a cloud operator domain; the smart NIC is installed in a connector; and the application layers associated with a cloud tenant domain. The process includes a baseboard management controller of the smart NIC managing the computer platform. Managing the computer platform includes the baseboard management controller managing the host; the baseboard management controller managing components of the smart NIC other than the baseboard management controller; and managing the host includes the baseboard management controller communicating with the host via the connector to control a system power state of the computer platform.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 12, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Scott P. Faasse, David F. Heinrich
  • Patent number: 11928000
    Abstract: An information handling system includes a management controller that may determine average power consumption of a processor, and determine average power measurement at a power supply unit. If the average power consumption of the processor does not match the average power measurement at the power supply unit, then the system may calibrate the average power consumption of the processor to match the average power measurement at the power supply unit.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Douglas E. Messick, Craig A. Klein, John E. Jenne, Ralph H. Johnson
  • Patent number: 11928001
    Abstract: Systems and methods for musical tempo detection are provided. The method includes detecting peaks and their locations in a waveform of a digital audio track, and dividing the track into first measures with a first-measure length based on a first estimated tempo. The method includes determining distances between a beginning of the first measures and each peak location, and determining a first number of peaks having the same distance from the beginning of the first measures. The method includes dividing the track into second measures with a second-measure length based on a second estimated tempo; determining distances between a beginning of the second measures and each peak location; and determining a second number of peaks having the same distance from the beginning of each of the second measures. The method includes estimating an accurate tempo by comparing the first number of peaks and the second number of peaks.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 12, 2024
    Assignee: inMusic Brands, Inc.
    Inventors: John O'Donnell, Christopher Blane Roman, James Samuel Heintz, Manuel Kaletta, Marcus Tillmans
  • Patent number: 11928002
    Abstract: Embodiments of the present disclosure provide a data transmission method, apparatuses, and a smart watch device. A first BLE module of a first MCU of a smart watch receives an instruction of transmitting data which includes an instruction of transmitting the data to an AP of the smart watch or a mobile terminal. The first BLE module determines whether the AP is in a wake-up state if the instruction is to transmit the data to the AP, and transmits the data to a second BLE module of the AP through a RFCOMM interface if the AP is determined to be in the wake-up state, otherwise, buffers the to-be-transmitted data. The first BLE module synchronizes state information to the second BLE module if the instruction is to transmit the data to the mobile terminal, and transmits the data to the mobile terminal through the RFCOMM interface.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: March 12, 2024
    Assignee: Mobvoi Information Technology Company Limited
    Inventors: Wenjie Zhou, Bo Zhang, Yuanyuan Li
  • Patent number: 11928003
    Abstract: To provide a voltage control device that includes a power supply circuit that supplies electric power to an input terminal of a controlled circuit, a power supply voltage control circuit that controls the power supply voltage to be supplied from the power supply circuit to the controlled circuit, on the basis of the clock signal to be supplied to the controlled circuit, and a clock generation circuit that receives a power supply that is the internal voltage to be applied to a second internal circuit region at a second wiring distance from the input terminal, and generates the clock signal on the basis of the internal voltage, the second wiring distance being longer than a first wiring distance at which a first internal circuit region is located in the controlled circuit, the first wiring distance and the second wiring distance being wiring distances in the controlled circuit from the input terminal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 12, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takahiro Naito
  • Patent number: 11928004
    Abstract: Techniques regarding quantum error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. The set of scaled quantum gates can comprise a quantum gate and an inverse of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 12, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathan Don Earnest-Noble, Caroline Tornow, Daniel Josef Egger
  • Patent number: 11928005
    Abstract: Various embodiments are generally directed an apparatus and method for receiving information to write on a clustered system comprising at least a first cluster and a second cluster, determining that a failure event has occurred on the clustered system creating unsynchronized information, the unsynchronized information comprising at least one of inflight information and dirty region information, and performing a resynchronization operation to synchronize the unsynchronized information on the first cluster and the second cluster based on log information in at least one of an inflight tracker log for the inflight information and a dirty region log for the dirty region information.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: March 12, 2024
    Assignee: NetApp, Inc.
    Inventors: Paul Yuedong Mu, Paul Ngan, Manoj Sundararajan
  • Patent number: 11928006
    Abstract: A system for generating a set of rules for detecting Controller Area Network (CAN) messages anomalies, the system comprising a processing resource configured to: obtain a training set including a plurality of CAN messages, each CAN message having properties; train a model, using the training set, the model characterizing statistical relationships between one or more first types of CAN messages of respective first CAN message type and one or more second types of CAN messages each of respective second CAN message type, wherein the statistical relationships are based on one or more of the properties of the CAN messages of the training set; wherein the model is usable for identifying anomalies within a sequence of input CAN messages.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 12, 2024
    Assignee: SAFERIDE TECHNOLOGIES LTD.
    Inventors: Yehiel Stein, Yossi Vardi, Nadav George Costa
  • Patent number: 11928007
    Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 12, 2024
    Assignee: Siemens Industry Software Inc.
    Inventors: Gajinder Panesar, Iain Robertson, Callum Stewart, Hanan Moller, Melvin Cheah
  • Patent number: 11928008
    Abstract: Provided is a watchdog system including: a software area including a bootloader area and an application area, and a shared memory area storing the last watchdog refresh timing; and an external watchdog module refreshing a watchdog when a transmitted refresh request timing corresponds to window open time in response to a refresh request transmitted from either the bootloader area or the application area and based on the last watchdog refresh timing transmitted from the shared memory area and the transmitted refresh request timing.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: March 12, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Hyo Jung Kim, Jongshik Baek
  • Patent number: 11928009
    Abstract: Aspects of the invention include detecting an error alert from a target computer system. In response to detecting the error alert, performance data is then retrieved from the target computer system. A gated recurrent unit (GRU) neural network is used to generate a prediction of a root cause of the error alert based on the performance data. The weights of a reset gate of the GRU neural network are adjusted based on received feedback of the prediction.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 12, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chun Qi Ji, Qiang Li, Jing Sun, Zong Nan Jin, He Jun
  • Patent number: 11928010
    Abstract: An example system includes a processor that can receive conversation logs of a dialogue system to be analyzed. The processor can train a predictive machine learning model using a training set of the conversation logs on a selected feature to obtain feature values with associated importance values. The processor can select a number of feature values using a significance score calculated based on the associated importance values. The processor can generate an interactive user interface including the selected number of feature values.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Sergey Zeltyn, Avi Yaeli
  • Patent number: 11928011
    Abstract: Embodiments of systems and methods for enhanced drift remediation with causal methods and online model modification are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: detect drift in an Artificial Intelligence (AI) or Machine Learning (ML) model configured to make a prediction or a causal reasoning graphical or structural inference based upon input data, identify a root cause of the drift, and tag the input data with an indication of the root cause.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Dell Products, L.P.
    Inventors: Said Tabet, Jeffery White, George Currie, Xin Ma
  • Patent number: 11928012
    Abstract: Methods, systems, and computer-readable media for verification of configurations of compute clusters. An automatic computational process is used to statically and/or dynamically verify configurations of software components installed on one or more interconnected computing entities constituting a compute cluster. Cluster configuration data is obtained, including data representative of a configuration of the software components. The cluster configuration data is processed to identify errors relating to interactions between the software components. Errors may be reported to users and/or corrected by modifying the compute cluster configuration.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 12, 2024
    Inventor: Albert Heinle
  • Patent number: 11928013
    Abstract: Systems, methods, and software for analyzing data logs. In one embodiment, a method comprises collecting a plurality of the data logs from log-generating elements, converting the data logs into log images, performing image analysis on a plurality of the log images to extract insights, and generating an output based on the insights.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 12, 2024
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Rakshesh Pravinchandra Bhatt, Kiran Kumar HK, B Prasanna Sai Krishna
  • Patent number: 11928014
    Abstract: A method of tracking errors in a system comprising microservices comprises ingesting a plurality of spans generated by the microservices during a given duration of time. The method further comprises consolidating the plurality of spans associated with the given duration of time into a plurality of traces, wherein each trace comprises a subset of the plurality of spans that comprise a common trace identifier. For each trace, the method comprises: a) mapping a respective trace to one or more error stacks computed for the respective trace and to one or more attributes determined for the respective trace; and b) emitting each error stack computed from the respective trace with an associated pair of attributes. The method then comprises reducing duplicate pairs of error stack and associated attributes and maintaining a count for each pair of error stack and associated attributes.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 12, 2024
    Assignee: SPLUNK Inc.
    Inventors: Mayank Agarwal, Steven Flanders, Justin Smith, Gergely Danyi
  • Patent number: 11928015
    Abstract: A fault insertion device (FID) comprises a transceiver and an FPGA. The transceiver receives signals from a MIL-STD-1553/1760 communications bus. The FPGA evaluates the signals received from the communications bus against a set of rules stored by the FPGA. Based upon the set of rules, the FPGA can selectively modify messages received from the communications bus prior to transmission to a remote terminal or a bus controller that is configured to communicate on the communications bus.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason P. Krein, Jeremy W. Giron, Matthew S. Geuss, Robert Nevett, IV, Stephen T. Simpson, Roger Martin Kilgore, Jacob Edward Leemaster
  • Patent number: 11928016
    Abstract: Embodiments of the invention are directed to systems, method, and devices for detecting failures in distributed systems. A failure detection platform may identify anomalies in time series data, the time series data corresponding to historical network messages. The anomalies can be labeled and used to train a first predictive model. At least one other model may be trained using the time series data, the anomaly labels and a supervised machine-learning algorithm. A third model can be trained to identify a system failure based at least in part on the outputs provided by the first and the second model. The third model, once trained, can be utilized to predict a future system failure.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 12, 2024
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventor: Minghua Xu
  • Patent number: 11928017
    Abstract: A method includes receiving a point data anomaly detection query from a user. The query requests the data processing hardware to determine a quantity of anomalous point data values in a set of point data values. The method includes training a model using the set of point data values. For at least one respective point data value in the set of point data values, the method includes determining, using the trained model, a variance value for the respective point data value and determining that the variance value satisfies a threshold value. Based on the variance value satisfying the threshold value, the method includes determining that the respective point data value is an anomalous point data value. The method includes reporting the determined anomalous point data value to the user.
    Type: Grant
    Filed: May 21, 2022
    Date of Patent: March 12, 2024
    Assignee: Google LLC
    Inventors: Zichuan Ye, Jiashang Liu, Forest Elliott, Amir Hormati, Xi Cheng, Mingge Deng
  • Patent number: 11928018
    Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11928019
    Abstract: A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 12, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Dance Wu, Chuanhai Zhou, Hong Yu Chou
  • Patent number: 11928020
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: March 12, 2024
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 11928021
    Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Melissa I. Uribe
  • Patent number: 11928022
    Abstract: A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Microchip Technology Incorporated
    Inventor: Avinash Halageri
  • Patent number: 11928023
    Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Schaefer
  • Patent number: 11928024
    Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Synopsys, Inc.
    Inventor: Karthik Thucanakkenpalayam Sundararajan
  • Patent number: 11928025
    Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, Brent Keeth
  • Patent number: 11928026
    Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoi Ju Chung, Jang Ryul Kim
  • Patent number: 11928027
    Abstract: Embodiments include receiving fixed size error checking and correction data blocks and metadata at a memory controller. Embodiments may include performing data to symbol mapping based upon the fixed size data blocks and providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error. Embodiments may include receiving data at a memory based upon an output from the first encoder and the second encoder and receiving data from the memory at a first decoder without metadata configured for full detection correction of single device error and at a second decoder with metadata configured for partial detection correction. Embodiments may include re-mapping symbol data from the first decoder and the second decoder to actual data and generating output data blocks and metadata.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Modi Dipakkumar Trikamlal, Maddula Balakrishna Chaitanya
  • Patent number: 11928028
    Abstract: An exception handler for dynamic remediation of fatal errors is described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a Central Processing Unit (CPU) and a memory coupled to the CPU, the memory having program instructions stored thereon that, upon execution, cause the IHS to: in response to an error, call a CPU Exception Service Routine (ESR); and at least one of: re-initialize a pre-boot network stack and transmit error data to a remote service using the pre-boot network stack; or re-initialize a pre-boot storage stack and store the error data using the pre-boot storage stack.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products, L.P.
    Inventors: Shekar Babu Suryanarayana, Vivek Viswanathan Iyer
  • Patent number: 11928029
    Abstract: A system that implements a data storage service may store data for a database table in multiple replicated partitions on respective storage nodes. In response to a request to back up a table, the service may back up individual partitions of the table to a remote storage system independently and (in some cases) in parallel, and may update (or create) and store metadata about the table and its partitions on storage nodes of the data storage service and/or in the remote storage system. Backing up each partition may include exporting it from the database in which the table is stored, packaging and compressing the exported partition for upload, and uploading the exported, packaged, and compressed partition to the remote storage system. The remote storage system may be a key-value durable storage system in which each backed-up partition is accessible using its partition identifier as the key.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 12, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Maximiliano Maccanti, Timothy Andrew Rath, Rama Krishna Sandeep Pokkunuri, Akshat Vig, Clarence Wing Yin Ng, Srivaths Badrinath Copparam, Rajaprabhu Thiruchi Loganathan, Wei Xiao, William Alexander Stevenson
  • Patent number: 11928030
    Abstract: A method includes creating a deduplicated universal share (US) of data objects, which in turn includes receiving a US of the data objects, deduplicating the US, wherein deduplicating the US includes: hashing segments of the US to generate respective US segment fingerprints; comparing US segment fingerprints to fingerprints for respective segments held in deduplication storage in order to identify segments in the deduplication storage that equate to the US segments, respectively, of the US; storing identifiers that directly or indirectly identify locations, respectively, of the segments, respectively, in the deduplication storage that equate to the US segments, respectively, of the US. After creating the deduplicated universal share, a deduplicated backup of the US is created without reassembling the US from segments held in the deduplication storage, the creating the deduplicated backup including: creating a list that comprises copies of the stored identifiers, and storing the list.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 12, 2024
    Assignee: Veritas Technologies LLC
    Inventors: Shuangmin Zhang, Xianbo Zhang, Shengzhao Li, Xu Jiang, Weibao Wu
  • Patent number: 11928031
    Abstract: An illustrative data storage management system enables a Tenant to retain control over criteria for protecting the Tenant's data, and hides details of the Service Provider's infrastructure. The Service Provider may have many data centers, each one represented within the system by a Resource Pool with attributes that reflect the infrastructure resources of the corresponding data center. A system analysis, which is triggered by the Tenant's choices for data protection, keys in on a suitable Resource Pool. The system analysis identifies suitable system resources within the Resource Pool and associates them to the data source. Subsequent data protection jobs invoke proper system components based on the associations created by the system analysis. In some embodiments, the system will invoke infrastructure resources created on demand when a data protection job is initiated rather than being pre-existing resources.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: March 12, 2024
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Anand Vibhor, Niteen Jain
  • Patent number: 11928032
    Abstract: Techniques for data management are described. A monotonically increasing time source that indicates an elapsed time since a reference event may be activated. Multiple snapshots of a computing object may be generated in accordance with a schedule for backing up the computing object, where the schedule may include a retention duration for retaining snapshots. Based on generating the snapshots, timestamps for the snapshots may be stored, where the timestamps may indicate respective values of the monotonically increasing time source. As part of an expiration job, a reference value of the monotonically increasing time source may be identified based on the retention duration and a current value indicated by the monotonically increasing time source. Also, a snapshot of the snapshots may be expired based on a timestamp of the snapshot corresponding to a value of the monotonically increasing time source that is less than the reference value.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 12, 2024
    Assignee: Rubrik, Inc.
    Inventors: Vijay Karthik, Stephen Charles O'Hara-Smith, Sandeep Majji, Samyak Jain, Aman Bansal
  • Patent number: 11928033
    Abstract: A method of remote device diagnosis and mitigation includes receiving a signal indicative of an intermittent technical state of a first device. Immediately responsive thereto, the method includes interrogating the first device for parameters. The method includes interrogating the first device for the parameters at a third time outside receipt of the signal. The parameters include a transient parameter present at a first time of the intermittent technical state and not present a second time following the first time. The method includes recording the parameters from the first time in a first data file and the parameters for the third time in an additional data file. The first data file is compared with the additional data file to identify a difference in a parameter indicative of a cause of the intermittent technical state. The method includes remotely implementing a change on the first device to mitigate the cause.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 12, 2024
    Assignee: Ivanti, Inc.
    Inventor: Liam Hughes
  • Patent number: 11928034
    Abstract: Network configuration details associated with a host are collected with each bare metal recovery (BMR) backup of the host. The network configuration details are stored in backup storage with each BMR backup copy. A target host is booted into a preinstallation environment. The target host is configured into a DHCP mode to allow the target host to establish a network connection to a backup management server. Details about the host are received from a user. A listing of BMR backup copies corresponding to the host details are retrieved from the backup management server. A selection of a BMR backup copy to be restored onto the target host is received. Network configuration details corresponding to the selected BMR backup copy are downloaded from backup storage. A recovery wizard at the target host is populated with the network configuration details.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Amarendra Behera, Shelesh Chopra, Tushar Dethe, Sunil Yadav
  • Patent number: 11928035
    Abstract: Embodiments of the present disclosure relate to a method, a device and a computer program product for recovering data. The method comprises in response to receiving a request to recover data from a backup node to a source node, determining a plurality of candidate backup nodes having copies of the data; determining respective performance indicators of the plurality of candidate backup nodes; and determining, from the plurality of candidate backup nodes, the backup node for recovering the data to the source node based on the respective performance indicators of the plurality of candidate backup nodes.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 12, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Qi Wang, Weiyang Liu, Yuanyi Liu, Zengjie Zhang, Jin Ru Yan
  • Patent number: 11928036
    Abstract: A method of recovering a storage device from a failure mode by a controller, the method comprising executing a boot up of the storage device, determining whether an instruction for pseudo boot up of the storage device has been received, switching from the boot up to a pseudo boot up of the storage device if an instruction for the pseudo boot up has been received, and resuming operation of the storage device from the prior operational state. The pseudo boot up restores the storage device to a prior operational state up to the point in time when the storage device encountered a failure triggering event that caused the storage device to enter the failure mode.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventors: Kentaro Sugino, Mahesh Bhadragiri Acharya, Sharwan Lal Saini
  • Patent number: 11928037
    Abstract: The technology disclosed herein enables the restoration of a database version across cloud environments. In a particular embodiment, a method provides receiving, in a second cloud environment from a first cloud environment, first metadata describing a first data version stored in the first cloud environment. The first data version includes first data items and the first metadata. After receiving the first metadata, the method provides receiving, in the second cloud environment, an instruction to restore the first data items to the second cloud environment. In response to the instruction, the method provides restoring the first data items to the second cloud environment using the first metadata.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: March 12, 2024
    Assignee: Rubrik, Inc.
    Inventors: Pin Zhou, Prasenjit Sarkar
  • Patent number: 11928038
    Abstract: An approach for managing data set access based on data set relevance. The approach monitors data set access activities associated with a user. The approach detects access of a first data set by the user. The approach determines a group of data sets associated with the first data set based on a data set mapping associated with the user. The approach recalls one or more data sets of the group of data sets from a slower storage device to a faster storage device.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jing Wen Chen, Zhao Yu Wang, Peng Hui Jiang, Jing BJ Ren, Yi Jie Ma, Wen Zhong Liu
  • Patent number: 11928039
    Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technologies, Inc.
    Inventors: Yang Lu, Kang-Yong Kim, Mark Kalei Hadrick, Keun Soo Song
  • Patent number: 11928040
    Abstract: An API adapter test support system includes an API adapter test support apparatus, a user terminal simulation apparatus and a user server simulation apparatus. The user terminal simulation apparatus and the user server simulation apparatus are connected to a wholesale service apparatus to which an API adapter. The API adapter test support apparatus includes a test scenario creation unit configured to create a test scenario that ensures comprehensiveness of a test case of an API adapter test, a control signal test scenario execution unit configured to execute a control signal API test for the API adapter by using the test scenario, and a data signal test scenario execution unit configured to execute a data signal API test for the user terminal simulation apparatus and the user server simulation apparatus by using the test scenario.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: March 12, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Sho Kanemaru, Tomoki Ikegaya, Kensuke Takahashi, Tsuyoshi Toyoshima
  • Patent number: 11928041
    Abstract: Embodiments of a system for determining a data gravity index score and implementing pervasive data center architecture is disclosed. In some embodiments, the system can calculate a data gravity index score based on the amount of data stored in a given location, an amount of data in motion in the given location, a bandwidth index associated with the given location, and a latency index associated with the given location. Based on data gravity index scores, in some embodiments, the system can localize traffic to improve network performance, improve security operations, and generate software-defined-network overlay.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: March 12, 2024
    Assignee: Digital Realty Trust, Inc.
    Inventors: Dave Dennis McCrory, Anthony Bennett Bishop
  • Patent number: 11928042
    Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Dat T. Le, George Vergis
  • Patent number: 11928043
    Abstract: Embodiments of systems and methods for adapting a log severity level that is applied to log files associated with a target application based on user interaction. In an illustrative, non-limiting embodiment, an adaptive log level control system includes computer-executable instructions for monitoring user interaction with a target application executed on the IHS, identifying a usage pattern of the user interaction, and determining that the usage pattern is indicative of a problem with the target application. The instructions may then adjust a log severity level of log files associated with the target application according to the detected problem.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: March 12, 2024
    Assignee: Dell Products, L.P.
    Inventors: Indumathi Ganesan, Sreehari Ganesh Tummala, Harshendra Shetty, Shivendra Katiyar
  • Patent number: 11928044
    Abstract: Techniques for a service provider network to communicatively couple services and/or applications in a serverless computing environment. A pipe component can configure a pipe to integrate two services by transmitting data between services and/or applications using the pipe. The pipe may also be configured to transform how a service processes an event, control timing of event transmissions using the pipe, define an event structure for an event, and/or batch events. Pipes enable an application or service to exchange data with a variety of services provided by the service provider network while controlling what type of data is generated, stored, or transmitted.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Nikita Pinski, Mohamed Marzouk Adedoyin Mounirou, Jakub Mateusz Narloch
  • Patent number: 11928045
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include simulating a processor model and a hardware model, each executed with a corresponding simulator thread on a simulation platform. Embodiments may also include simulating embedded software using the processor model. The simulating may include updating a given register of the processor model that stores a value that changes in response to switching between processes within the embedded software. Embodiments may further include setting a simulator breakpoint and a software breakpoint and enabling debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bishnupriya Bhattacharya, Andrew Robert Wilmot, Zhiting Duan, Neeti Khullar Bhatnagar
  • Patent number: 11928046
    Abstract: An analysis system receives data streams generated by instances of instrumented software executing on external systems. The analysis system evaluates an expression using data values of the data streams over a plurality of time intervals. For example, the analysis system may aggregate data values of data streams for each time interval. The analysis system determines whether or not a data stream is considered for a time interval based on when the data value arrives during the time interval. The analysis system determines a maximum expected delay value for each data stream being processed. The analysis system evaluates the expression using data values that arrive before their maximum expected delay values. The analysis system also determines a failure threshold value for a data stream. If a data value of a data stream fails to arrive before the failure threshold value, the analysis system marks the data stream as dead.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 12, 2024
    Assignee: Splunk Inc.
    Inventors: Phillip Liu, Arijit Mukherji, Rajesh Raman
  • Patent number: 11928047
    Abstract: Mechanisms are provided to generate a test dataset for software application development. A baseline mixed reality (MR) environment simulation of an existing process is generated that models applications of an application landscape. A requirement for an application that is to be developed is received and a MR component model is generated to represent the application based on a machine learning computer model processing of the requirements data structure and a knowledge corpus. The MR component model modifies the baseline MR environment simulation, and executes the modified MR environment simulation to simulate the modified MR environment simulation. The simulation is monitored for user input specifying a contextual scenario and context data is collected from the MR component models of the modified MR environment simulation. A test dataset for testing a coded version of the SUD application is generated based on the contextual scenario and the collected data.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Venkata Vara Prasad Karri, Sarbajit K. Rakshit, Kamal Kiran Trood Yamala, Suresh Nagulakonda