Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.

Abstract: A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: Embodiments are related to systems and methods for forming vias in a substrate, and more particularly to systems and methods for reducing substrate surface disruption during via formation.

Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: According to an embodiment of the present invention, a removal module using an electric field and a magnetic field so as to self-assemble, on cells arranged in a matrix form of an assembly substrate, semiconductor light-emitting elements introduced in a fluid accommodated in a chamber, and then remove a semiconductor light-emitting element mis-assembled with the assembly substrate comprises: a fluid supply unit for supplying the fluid; and a housing of which one side is connected to the fluid supply unit, an upper plate is adjacent to the assembly substrate, and a lower plate is adjacent to the chamber, wherein the upper plate has: a nozzle hole allowing communication between the inner space of the housing and the inner space of the chamber so that the fluid supplied from the fluid supply unit is injected at a site in which the semiconductor light-emitting element is mis-assembled on the assembly substrate; and one pair of partition parts facing each other with the nozzle hole as the center thereof.

Abstract: A controller of a substrate processing apparatus causes execution of: a cleaning process of cleaning at least a bottom surface of a cover by a cleaning liquid that fills a space between a top surface of a substrate and the bottom surface of the cover by supplying, in a state in which a vertical distance between the top surface of a substrate (a cleaning substrate) held by a substrate holder and the bottom surface of the cover is set to a first distance, the cleaning liquid to the top surface of the substrate while rotating the substrate; and after the cleaning process, a drying process of drying at least the bottom surface of the cover by stopping, in a state in which the vertical distance is set to a second distance greater than the first distance, the supply of the cleaning liquid while rotating the substrate.

Abstract: A detachable etching tool for etching a plurality of silicon carbide pieces has a first supporting column and a second supporting column, both of which are fixed through a tool fixing block. A bracket is arranged on the tool fixing block, and a limiting rod is installed on the lower end surface of the bracket. The bracket is inserted into the tool fixing block through the limiting rod and fixed on the tool fixing block with a fastening mechanism that comprises a base, a fixing seat, a telescopic spring, a telescopic guide column, a sliding block, a guide block, an inserting rod and a push-pull mechanism. The etching tool addresses low productivity per unit time and long time consumption in the etching processing.

Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.

Abstract: A wafer holder includes a mounting table that has a mounting surface for a workpiece at a top, a supporting member that supports the mounting table from a lower side, a first cylindrical member one end of which is joined hermetically to a lower surface of the mounting table, and a second cylindrical member that is provided inside the first cylindrical member and one end of which is joined hermetically to the lower surface of the mounting table.

Abstract: A processing apparatus for a thermal treatment of a workpiece is presented. The processing apparatus includes a processing chamber, a workpiece support disposed within the processing chamber, a gas delivery system configured to flow one or more process gases into the processing chamber from the a first side of the processing chamber, one or more radiative heating sources disposed on the second side of the processing chamber, one or more dielectric windows disposed between the workpiece support and the one or more radiative heating sources, a rotation system configured to rotate the one or more radiative heating sources, and a workpiece temperature measurement system configured at a temperature measurement wavelength range to obtain a measurement indicative of a temperature of a back side of the workpiece.

Abstract: A bonding head for mounting components comprises a shaft and a housing part in which the shaft is supported. The bearing of the shaft enables a rotation of the shaft about an axis and a displacement of the shaft in the longitudinal direction of the axis by a predetermined stroke. The bonding head further comprises an electric motor with a stator attached to the housing part and a rotor attached to the shaft, an encoder for measuring the rotational position of the shaft, and a force generator for applying a force to the shaft. The stator comprises coils to which currents can be applied, the rotor comprises a plurality of permanent magnets. A length of the permanent magnets measured in the longitudinal direction of the axis is shorter or longer than an effective length of the coils measured in the longitudinal direction of the axis by at least the stroke.

Abstract: The invention relates to an inspection unit intended for use in devices for transferring electronic components from a first substrate to a second substrate and/or for applying adhesive from a reservoir to the second substrate, comprising an image capturing unit, which is assigned an illumination unit, wherein the illumination unit is designed to direct light of different wavelengths onto a second holder, which in turn is designed to support an object located on the second substrate, which is to be captured by the image capturing unit, wherein a sixteenth, seventeenth, eighteenth and/or nineteenth conveying unit is designed to convey the respective image capturing unit and/or its associated optics, including focussing optics, a beam deflector and/or an illumination unit, along the second holder.

Abstract: A transportation monitoring method is provided, including the following steps. A monitoring image of a robot blade outside a carrier is captured from a fixed field of view by an image capturing device. The robot blade is configured to move an item into or out of the carrier. Next, a sampling area is obtained from the monitoring image by a processing device. Also, a tilting state of the robot blade is determined according to the sampling area by the processing device. When the processing device determines that the robot blade is tilted, the processing device sends a warning signal. A transportation monitoring system is also provided.

Abstract: The present invention relates to a method and an apparatus for determining the position of a substrate within a closed chamber, wherein the substrate is moved within the chamber by a transport system comprising at least one rotating shaft. A load-converting element is provided adjacent to at least one of the rotating shafts, wherein the load-converting element detects a load acting on the at least one rotating shaft and converts it into an electrical parameter. While no substrate is present on the at least one rotating shaft, a first output signal corresponding to a first value of the electrical parameter is measured. The output signal is then monitored and a presence of the substrate on the at least one rotating shaft is detected when the output signal differs from the first output signal by at least a predetermined amount.

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

Abstract: A wafer boat for supporting a plurality of semiconductor wafers in a furnace is disclosed. The wafer boat includes a set of fingers each having a contact protuberance which contacts and supports a semiconducting wafer. The contact protuberances may be arranged in a rotationally symmetric pattern about the wafer boat.

Abstract: A device of mass transferring chips includes a first substrate, which includes a first surface with a chip-connecting area configured to attach a chip, a second surface opposite to the first surface, and a patterned recess. The patterned recess is disposed on the first surface or the second surface. A projection of at least a portion of the patterned recess on the first surface is spaced apart from the chip-connecting area. The device further includes a second substrate with a third surface. The third surface has a chip-receiving area configured to attach the chip from the first substrate.

Abstract: A transfer system for wafer cassettes includes a tray and a rail compatible with the tray. The tray includes a base plate, a through hole, a wall, and a pair of first positioning features. The through hole is disposed on a center of the base plate, in which the through hole has a first direction axis and a second direction axis perpendicular to the first direction axis. The wall extends from a surface of the base plate and surrounding the through hole, in which the wall separates the base plate into an interior region and an exterior region. The pair of first positioning features having a first level height are in the interior region and arranged parallel to the first direction axis.

Abstract: A method and apparatus for loading substrates in an inspection station is disclosed herein. In one embodiment a loading module is disclosed that includes a loading station for two or more substrate cassettes, a first lane comprising a first conveyor that is substantially aligned with one of the two or more substrate cassettes and a conveyor system, a second lane comprising a second conveyor that is substantially aligned with another of the two or more substrate cassettes and positioned in a spaced-apart relation relative to the first lane, and a lateral transfer module positioned between the first lane and the second lane that is adapted to move substrates from the second lane to the first lane.

Abstract: A substrate transport apparatus comprising a support frame an articulated arm connected to the support frame, having at least one movable arm link and an end effector connected to the movable arm link, with a substrate holding station located thereon. Wherein the movable arm link is a reconfigurable arm link having a modular composite arm link casing, formed of link case modules rigidly coupled to each other, and a pulley system cased in and extending through the rigidly coupled link case modules substantially end to end of the modular composite arm link casing, wherein the rigidly coupled link case modules include link case end modules connected by at least one interchangeable link case extension module having a predetermined characteristic determining a length of the movable arm link, wherein at least one interchangeable link case extension module is selectable for connection to link case end modules forming the reconfigurable arm link.

Abstract: A transport apparatus includes a hand, a drive mechanism, a cover member, and a gas supply member. The hand is configured to hold a wafer. The drive mechanism is configured to transport the wafer by moving the hand. The cover member has an opposing surface opposed to a surface of the wafer held by the hand and is formed with a plurality of holes opened in the opposing surface. The gas supply member is configured to supply an inert gas to the surface of the wafer via the plurality of holes of the cover member. The plurality of holes are formed in the opposing surface so that an opening ratio of an outer peripheral portion of the opposing surface is higher than an opening ratio of a central portion of the opposing surface.

Abstract: A substrate handling apparatus according to one or more embodiments may include: a base, an elevating unit that is connected to the base to freely elevate and lower, an arm that is rotatably connected to the elevating unit, a disk that is provided on the arm, and a hand that is rotatably connected to the arm, wherein in case that the hand is provided on a position to overlap the arm, the disk is provided under the substrate extracted by the hand.

Abstract: A method of constructing an E-puck includes forming at least one trench into a lower substrate, depositing an electrode material onto the lower substrate and into the at least one trench, removing excess electrode material from the lower substrate to leave the electrode material within the at least one trench to form an electrode, and forming a dielectric on the lower substrate and the electrode. The electrode is between the lower substrate and the upper substrate. Forming the at least one trench into the lower substrate forms at least one standoff portion adjacent to the at least one trench and the at least one standoff portion reduces dishing of the electrode material during removal of the excess electrode material from the lower substrate.

Abstract: A chuck for heating and clamping a workpiece, such as a semiconductor workpiece, is disclosed. The chuck is configured to allow the workpiece to be heated to temperatures in excess of 600° C. Further, while the workpiece is heating, the components that make up the chuck may be maintained at a much lower temperature, such as room temperature. The chuck includes a housing, formed as a hollow cylinder with sidewalls and an open end. Electrodes are disposed at the top surface of the sidewalls to clamp the workpiece. A heat source is disposed in the cavity and emits radiated heat toward the workpiece. A clamp ring may be used to secure the workpiece. In some embodiments, a thermal sensor is used to monitor the temperature of the workpiece.

Abstract: A method includes determining an alignment error between a discrete component of a discrete component assembly mounted in a laser-assisted transfer system and a target position on a target substrate, the discrete component assembly including the discrete component adhered to a support by a dynamic release layer; based on the alignment error, determining a beam offset characteristic; and providing a signal indicative of the beam offset characteristic to an optical element of the laser-assisted transfer system, the optical element being configured to adjust a position of a beam pattern relative to the discrete component according to the beam offset characteristic.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.

Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

Abstract: A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.

Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

Abstract: According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: The present application discloses a method for manufacturing a fin field effect transistor, comprising: step 1: forming fins; step 2, forming first gate structures; and step 3, forming source and drain areas, comprising: step 31: forming a second hard mask layer; step 32: opening a formation area of FinFET, and performing the first time etching on the second hard mask layer; step 33: performing the second time etching to form first grooves in the fins, wherein the second time etching vertically and horizontally etches the isolation dielectric layer, when the second groove is formed next to the exposed surfaces of the isolation dielectric layer, the exposed surfaces of the fins and the first polysilicon gate, as the result, the second groove forms a bridge path; step 34: forming a sacrificial sidewall to fully fill the bridge path; and step 35: filling the first groove with an epitaxial layer.

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.

Abstract: A system and method for in-situ characterization of functional devices. The system comprises a vacuum chamber; a pump system coupled to the vacuum chamber for evacuation the vacuum chamber to near ultra high vacuum pressures of about 10?8 mbar or lower; a sample holder for a functional device based on nanostructured materials disposed inside the vacuum chamber and configured to provide electrical connection to the functional device for measuring electrical properties of the functional device; and a source system for exposing a surface/interface of the functional device to a modification species; whereby the system is configured to measure the electrical properties of the functional device in-situ upon the exposure to the modification species.

Abstract: Disclosed herein is a method for determining the endpoint of an etch operation used for forming high aspect ratio features and/or over low open area (<1%) on a substrate in a processing chamber. The method begins by obtaining a reference emission curve. An etch operation is performed on a patterned substrate. A plasma optical emission intensity is measured for each of the etch cycles. A differential curve between the reference emission and the plasma optical emissions is calculated. And endpoint is determined for the etch operation on the first substrate based on an inflection point detection or other unique features through pattern recognition in the differential curve for stopping the etch of the first substrate.

Abstract: A semiconductor device package includes a substrate; an electronic component disposed on the substrate; multiple supporting structures disposed on the substrate; and a reinforced structure disposed on the supporting structures and extending in parallel with the substrate.

Abstract: In an assembly in which a space between two elements is filled with a filler containing resin, a configuration that can limit both the size of the assembly and the cost of the fillers is provided. An assembly of stacked elements has: first element having first surface; resin layer that is arranged on first surface and that contains a plurality of fillers; and second element that is arranged on resin layer and that has second surface that is in contact with resin layer. In a section that is perpendicular to second surface, the average flattening ratio of fillers that are in contact with second surface is larger than the average flattening ratio of fillers that are not in contact with second surface. Here, the flattening ratio is a ratio of the maximum length of the filler in a direction parallel to second surface to the maximum thickness of the filler in a direction perpendicular to second surface.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board.

Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.