Abstract: A compilation method includes: receiving a signal to be compiled and a working frequency signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the working frequency signal to determine a first compilation value.

Abstract: New CMOS harvesting circuits are proposed that improve 2-port/multiport Register File Array circuit speed and substantially lower the energy cost of moving data along local and global bitpaths when engaging harvested data to self-limit energy dissipation. The uncertainty in BL signal development due to statistical variations in cell read current is eliminated by self-disabling action in the selected cell when the electric potential of harvested data matches the BL voltage from signal development while demanding fewer peripheral circuit transistors per column than conventional sensing schemes. Proposed bit path circuits engage harvested charge to provide immunity to disturb current noise during concurrent Read and Write access along a WL-eliminating the performance, area and energy overheads of BL keeper circuits typically required in conventional Register File arrays.

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: Provided is a storage apparatus that reduces the power needed to write corrected data back to a memory. The storage apparatus includes a memory and a write control section. The memory stores data in units of multiple cells each representing a predetermined value. The write control section receives write-back data having a specific value in a position corresponding to at least one of the multiple cells, as well as a write-back command regarding the specific value. The write control section performs control to write the specific value only to the cell corresponding to the position indicative of the specific value in the write-back data.

Abstract: The invention is notably directed to a device comprising a plurality of resistive memory elements. The plurality of resistive memory elements comprises a resistive material. The device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to perform a temporary resistance change of the resistive material of the subset for a predefined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that a resistance of the subset of the plurality of resistive elements reverts automatically during the predefined retention period from the second resistance state to the first resistance state by an inherent material property of the resistive material, thereby automatically deleting the second binary state.

Abstract: Disclosed are a compute-in-memory array and module, and a data computing method; a storage cell is configured to form an array used for computation; the storage cell consists of bitcells serially connected in sequence; a bitcell comprises a switching device and a resistive memory; the switching device is connected in series or in parallel with the resistive memory; the write resistance value of the storage cell is determined by means of controlling the switching state of the switching device so as to change the resistance state of the resistive memory. Since resistive memories have different resistance states, a resistive memory can be set in different resistance states by means of the switching state of the switching device, such that the storage cell is at a required write resistance value, thereby enabling the quick implementation of a write operation of the bitcell.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal ?. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

Abstract: A memory array that includes a plurality of memory blocks and a plurality of source switches is introduced. Each of the source switches corresponds to one of the memory blocks, and each of the source switches is coupled to a common source line of the corresponding one of the memory blocks. A selected source switch, which corresponds to a selected memory block among the memory blocks for a program operation, is configured to bias the common source line of the selected memory block to a reference voltage during a program period of the program operation. An unselected source switch, which corresponds to an unselected memory block among the memory blocks for the program operation, is configured to float the common source line of the unselected memory block during the program period of the program operation.

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.

Abstract: A method of using boot-time metadata in a storage system is provided. The method includes writing a fragmentation stride to a solid-state storage device of the storage system, the fragmentation stride defining a granularity on which fragmentation of erase blocks of the solid-state storage device occurs. The method includes allocating portions of erase blocks for at least one process in the storage system, in accordance with the fragmentation stride and writing boot up metadata at offsets that are based on the fragmentation stride, in the solid-state storage device.

Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.

Abstract: The present technology includes a method of operating a controller capable of controlling a semiconductor memory device including a plurality of memory cells. The method of operating the controller includes sensing error correction failure of data read from the semiconductor memory device, generating a new read voltage for re-reading the data, determining whether the new read voltage belongs to an allowable range depending on a read voltage statistical value of previous read voltages according to which error corrections were successful on previously read data, and determining, based on a result of the determining whether the new read voltage belongs to the allowable range, a read voltage to be used in a next read operation of re-reading the data.

Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Abstract: A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.

Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.

Abstract: Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.

Abstract: A One Time Programmable (OTP) memory can have a memory cell, which includes two series diodes as a fuse structure.

Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.

Abstract: An OTP readout circuit includes an OTP circuit having a first OTP cell in which data is programmable only once, and a readout-possible signal output unit configured to generate a readout-possible voltage for reading out the data and output the generated readout-possible voltage to the OTP circuit. The readout-possible voltage from the readout-possible signal output unit causes the OTP circuit to read out the data programmed into the first OTP cell.

Abstract: An eFuse one-time programmable (OTP) memory is provided. The eFuse OTP memory supports inter integrated circuit (I2C) communication, and an operation method thereof. The eFuse OTP memory includes: an eFuse intellectual property (IP) which data writes once and data reads multiple times for a plurality of addresses; and an I2C slave which communicates with an I2C master based on a serial clock line and a serial data line, and performs the data write and the data read to and from the eFuse IP.

Abstract: An anti-fuse memory: an inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

Abstract: To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) format or in a single level cell (SLC) format. These ramp rates can be determined through device characterization and stored as parameter values on the memory die. Different ramp rate interval values can also be used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in an MLC format or in an SLC format.

Abstract: This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

Abstract: A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

Abstract: A redundancy managing method and apparatus for semiconductor memories is disclosed. The redundancy managing method for semiconductor memories utilizes bitmap type storage by defining an appropriate storage space according to the type of a fault.

Abstract: A calibration control circuit includes an off-chip calibration circuit, an on-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a user. The on-chip calibration circuit is configured to receive an enable signal and perform a ZQ self-calibration process on the memory to obtain a second calibration code adapted to a current environmental parameter when the enable signal is in an active state. The mode switching circuit is configured to receive a calibration mode signal, the first calibration code and the second calibration code, and determine the first calibration code as a ZQ calibration code when the calibration mode signal indicates an off-chip calibration mode, or, determine the second calibration code as the ZQ calibration code when the calibration mode signal indicates an on-chip calibration mode.

Abstract: A compilation method includes the following: receiving a signal to be compiled and a resistance matching signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and in the case where the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal according to the resistance matching signal to determine a first compiled value.

Abstract: Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

Abstract: In one embodiment, a method for identifying candidate sequences for genotyping a genomic sample comprises obtaining a plurality of sequence reads mapping to a genomic region of interest. The plurality of sequence reads are assembled into a directed acyclic graph (DAG) comprising a plurality of branch sites representing variation present in the set of sequence reads, each branch site comprising two or more branches. A path through the DAG comprises a set of successive branches over two or more branch sites and represents a possible candidate sequence of the genomic sample. One or more paths through the DAG are ranked by calculating scores for one or more branch sites, wherein the calculated score comprises a number of sequence reads that span multiple branch sites in a given path. At least one path is selected as a candidate sequence based at least in part on its rank.

Abstract: Provided herein are systems, methods, and computer program products using tumor phylogeny, mutation rates, and machine learning to produce a clinical projection, such as patient survival, risk of malignancy, and therapeutic options. The method includes generating sequence variation data that identifies, characterizes, or quantifies at least one mutation in tumor sequence data of a tumor of a patient. The method also includes generating a phylogenic tree depicting clonal evolution of cells in the tumor of the patient. The method further includes determining at least one feature of the phylogenic tree including at least one value quantifying rates of mutation and/or at least one value representing at least one aspect of a structure of the phylogenic tree. The method further includes training a machine learning model to be configured to generate a projection for the patient comprising a clinical outcome or disease progression.