Abstract: An improved information management system is described herein in which the information management system can evaluate the deduplication performance of secondary copy operations and dynamically adjust the manner in which secondary copy data is created to minimize the negative effects of performing deduplication. Furthermore, the improved information management system can improve deduplication performance by applying different storage policies to different types of applications running on a client computing device. Moreover, the improved information management system can automatically detect the region of a client computing device and apply an appropriate information management policy to the client computing device to avoid inconsistencies or other errors resulting from administrator control.

Abstract: Techniques for processing read/write requests involve determining an average response time for read/write requests to a storage device within a predetermined time period, and comparing the average response time with at least one predetermined threshold. Such techniques further involve adjusting a read/write request upper limit of the storage device based on the comparison between the average response time and the at least one predetermined threshold. Here, the read/write request upper limit indicates the maximum number of read/write requests in a read/write request queue for the storage device. In this way, the read/write request upper limit of a storage device may be dynamically adjusted based on a current response time of the storage device for processing read/write requests, and slow read/write processing caused by the accumulation of read/write requests at one storage device can be avoided.

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include a latency monitor and an operation controller. The latency monitor may count an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests from a host during each of a plurality of periods, calculate gaps which are difference values between the over-latency count values of the plurality of periods, and generate latency information including the over-latency count values and the gaps. The operation controller may determine, based on the latency info oration, whether each gap between at least two target periods among the plurality of periods exceeds a threshold value, and delay a response to the requests according to a determination result.

Abstract: A method of dynamically adjusting workload of a data storage system includes, while processing a first workload, calculating a saturation value of a saturation metric that scales substantially linearly with an I/O per second (IOPS) rate relative to a maximum IOPS rate of the system, determining that the saturation value is one of (1) above a high threshold and (2) below a low threshold, and performing a workload adjustment operation that establishes a second workload by (1) subtracting from the first workload based on the saturation value being above the high threshold, and (2) adding to the first workload based on the saturation value being below the low threshold, then subsequently processing the second workload.

Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Abstract: A tiered memory fabric workload performance optimization system includes a workload management device coupled to a processing fabric and a memory fabric. The workload management system receives a workload request to perform a workload including sub-workloads, and identifies a respective processing system in the processing fabric for performing each of the sub-workloads. The workload management device then determines, for use by each respective processing system identified for performing the sub-workloads, a respective memory system in the memory fabric to provide memory systems in different memory tiers in the memory fabric that optimize characteristic(s) of a workload performance pipeline provided by the respective processing systems identified for performing the sub-workloads.

Abstract: A multi-tenant database may maintain a plurality of datasets on a memory device that is subject to degraded operation caused by a subset of possible state transitions within the device's memory cells. A storage engine may identify entropy characteristics of datasets, independently of other datasets hosted on the memory, and use the entropy to construct a symbol table that maps from data within the dataset to symbols that may be stored on the memory device with a minimized number of state transitions.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory in response to a command from a host. The controller manages a first area and a second area in a memory space provided to the host, to which an area of the non-volatile memory is mapped. The first area is an area used by the host as a main memory. The second area is an area where valid data is stored.

Abstract: A method of predicting usage levels of solid-state drives (SSDS) includes receiving time series usage data from each SSD over a plurality of monitoring intervals (lags), and using a first portion of the time series usage data to train (fit) an ARIMA model to the time series data. A unique ARIMA model (order) is determined for each SSD from the unique time series % usage data of each SSD. The ARMIA model is then fit to the time series % usage data and used in a predictive manner to predict a future date when the % usage will exceed a threshold % usage value. By predicting when the SSDs will meet particular thresholds, it is possible to plan for and procure replacement SSDs to enable currently installed SSDs to be removed from service before the currently installed SSD % usage levels exceed threshold values, thus enabling the currently installed SSDs to be repurposed.

Abstract: Upon determining that a reference condition is satisfied, a storage device may determine target memory dies among a plurality of memory dies included in the storage device on the basis of temperatures of the plurality of memory dies, and then write data according to the determination of the target memory dies. For example, the storage device may write data to the target memory dies in an interleaving manner, may write data to a memory die that is not a target memory die only when data is not being written to any other of the plurality of memory dies, or both. The reference condition may relate to a temperature of the storage device.

Abstract: Exemplary methods, apparatuses, and systems include determining that a memory component to be subjected to a background data integrity scan does not currently satisfy an activity threshold. The background data integrity scan is delayed in response to determining memory component does not satisfy the activity threshold. In response to detecting a background data integrity scan trigger event, the background data integrity scan is performed.

Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

Abstract: A technique is configured to provide various data protection schemes, such as replication and erasure coding, for data blocks of volumes served by storage nodes of a cluster configured to perform deduplication of the data blocks. Additionally, the technique is configured to ensure that each deduplicated data block complies with data redundancy guarantees of the data protection schemes, while improving storage space of the storage nodes. In order to satisfy the data integrity guarantees while improving available storage space, the storage nodes perform periodic garbage collection for data blocks to optimize storage in accordance with currently applicable data protection schemes.

Abstract: Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.

Abstract: A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.

Abstract: Disclosed is a method for preforming the data mirror comprising: receiving from an application executing on a computing device a request to write data to a first local persistence memory of the computing device; issuing an async write operation to mirror the write request to write a same data to a second local persistence memory of the computing device; performing a write operation to write the data to the first local persistence memory by using a central processing unit (CPU) from the processing resource of the computing device; determining, by an additional CPU, a status completion result indicating whether the async write operation is complete; and in response to determining the async write operation is complete, determining, by the additional CPU, a status check result indicating whether the async write operation is successful.

Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.

Abstract: A serial presence detect (SPD) device includes a region of nonvolatile memory for SPD data and an additional region for other (e.g., vendor) use. The additional region may be subdivided into write protect regions that can be individually and independently write protected. To configure the write protection, a password key scheme is used to enter a mode whereby the write protection attributes may be configured. Another password key scheme is used to exit the write protection configuration mode.

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

Abstract: Apparatuses, methods and techniques for controlling memory access in a data processing system are disclosed. The operating data processing system comprises multiple subsystems, each comprising at least one processing element and at least one peripheral device. Memory transaction control circuitry receives memory transaction information of a memory transaction comprising a stream identifier indicative of the issuing peripheral device. A main control register indicates an address of a stream table having multiple entries each comprising an owning subsystem identifier. At least one subsystem control register corresponding to each subsystem of the multiple subsystems stores memory access checking configuration information. On receipt of the memory transaction information an entry of the stream table is selected in dependence on the stream identifier. At least one subsystem control register. corresponding to the subsystem identified by the owning subsystem identifier of the entry is selected.

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

Abstract: Systems and methods are disclosed for reducing idle power usage of a storage device. The storage device can include a storage media configured, a data interface configured to connect to the host device, a media controller, and a bridge controller. The bridge controller can be further configured to, in response to receiving an idle status message from the media controller, save state data of the media controller, send a shutdown command to the media controller to stop it from using power. The bridge controller can be further configured to, in response to receiving a read operation or a write operation from the host device, start power to the media controller, provide the media controller with the saved state data, receive data responsive to the read operation or the write operation from the media controller, and transmit the responsive data to the host device.

Abstract: A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

Abstract: A system includes a semiconductor device configured to store data and a controller communicatively coupled to the semiconductor device. The semiconductor device and the controller are configured to; in response to determining that particular data stored in the semiconductor device satisfies a reliability condition, obtain first readout data by reading the particular data at a first read voltage, and obtain second readout data by reading the particular data at a second read voltage. The second read voltage is different from the first read voltage. The semiconductor device and the controller are configured to compare the first readout data and the second readout data and obtain a comparison result; and, based on the comparison result, determine whether to perform an error correction process on the particular data.

Abstract: A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An exemplary surveillance system is provided having a plurality of data generating devices, and nodes for data handling of the data streams generated form the data generating devices. The system may be configured to fragment the data streams and store the fragments among the plurality of nodes of the system. The system may be configured to redundantly transmit data through the nodes so the fragmented data stream arrive at the desired location for storage. The data transmission may permit redirection or retransmission based on node or data transmission failure.

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Abstract: In some implementations, a computing device may configure a new device based on a current state of an old device, including settings, preferences, and other user data. The data may be transferred from the old device to the new device, and then relocated according to a manifest that details positions of the data on the old device. The destination device may be rebooted into a configuration mode to allow for the relocation of the transferred data, and then rebooted again to configure the destination device to provide access to the data in its respective relative locations on the destination device.

Abstract: A storage device, and a method of operating the storage device, includes a plurality of memory devices configured to store peak power information including information about a plurality of peak power periods and information about IDs respectively corresponding to the plurality of peak power periods. The storage device also includes a memory controller configured to assign an ID to each of the plurality of memory devices and control the memory devices so that one or more memory devices having an identical ID corresponding to a target period, among the plurality of peak power periods, perform a memory operation at peak power.

Abstract: A technique for achieving data mobility between storage systems having different block sizes includes identifying a baseline size that is common to the block sizes of the storage systems. The technique further includes generating fingerprints of blocks based on extents having the common baseline size. Fingerprint-based data mobility is then achieved by comparing extent-based fingerprints, or combinations thereof, across different storage systems to identify matching data.

Abstract: A method is provided. The method includes receiving a set of data blocks to be stored in a storage system. The storage system includes a plurality of non-volatile memory modules. The method also includes generating a set of segments based on the set of data blocks. A respective segment comprising portions of one or more erase blocks. The method further includes writing the set of segments to the non-volatile memory modules based on orderings of the portions of the one or more erase blocks.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a memory bank and be coupled to a set of devices. The I/O agent circuit may assign a device of the set of devices to a subdomain of a plurality of subdomains implemented for the memory bank. The I/O agent circuit may store, in that memory bank, a set of transactions of the device in association with the subdomain assigned to the device. The I/O agent circuit may execute the set of transactions such that transactions stored in the memory bank in association with other ones of the plurality of subdomains than the subdomain assigned to the device do not block execution of the set of transactions.

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

Abstract: A method for tracking a progress of data copying for a live migration includes transferring, by a storage controller, a first data structure to a live migration server, the first data structure including a first status identifier indicating a location of a source data to be copied from a source storage to a target storage, and selectively generating or selectively clearing, by the storage controller, a second status identifier in or from a second data structure, based on a first current copying location of the live migration server, the second status identifier indicating a location of a first user data write to the source storage.

Abstract: A method and system for live migration of an index in a document store are provided. The method includes creating a new index based on a change request, wherein the change request designates at least one change relative to a current index, wherein the new index includes all mappings and settings of the current index together with the at least one requested change, wherein the new index and the current index are properties of the document store; initiating a reindexing process of the new index by copying documents from the current index to the new index, wherein the current index remains active during the reindexing of the new index; resharding the current index; and upon successful completion of the reindexing process, deleting the current index and directing all write and read requests to the new index.

Abstract: In a method for storing index metadata associated with stored data, a storage device provides a first metadata storage unit and a second metadata storage unit, wherein a size of the first metadata storage unit is greater than a size of the second metadata storage unit. When a size of target data reaches a specified threshold, the storage device stores index metadata of the target data based on the first metadata storage unit. When the size of the target data is less than the specified threshold, the storage device stores the index metadata of the target data based on the second metadata storage unit.

Abstract: Techniques for forecasting temperatures of storage objects in a storage system using machine learning (ML). The techniques can include forecasting at least one temperature of a storage object using at least one ML model, modifying storage of the storage object based on the at least one temperature of the storage object, and, having modified storage of the storage object, obtaining at least one performance metric associated with the storage object. The techniques can further include, based on the performance metric(s), varying a frequency of forecasting the at least one temperature of the storage object, retraining the at least one ML model used in forecasting the at least one temperature, and/or adjusting at least one operational parameter of the system. The techniques provide increased accuracy over known statistical approaches to forecasting temperatures of storage objects, leading to increased performance gains in terms of IO latency, IO operations per second, and bandwidth.

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.

Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.

Abstract: A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.

Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a racing handler.

Abstract: A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

Abstract: A method, computer program product, and computer system for placing, by a computing device, an IO in a Kernel-Endpoint (KE) of a plurality of KEs, wherein the IO may be sent by a host and received in a kernel. The IO in the KE may be pulled from a kernel volume specific handle. The IO may be routed to a corresponding user volume associated with the IO.