Abstract: Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

Abstract: A memory system includes a non-volatile memory and a controller. The non-volatile memory includes at least one memory chip. The controller is electrically coupled to the non-volatile memory. The controller transmits a first instruction to the non-volatile memory, and transmits a second instruction to the non-volatile memory after transmitting the first instruction. The first instruction and the second instruction form a series of sequences. In a case where the non-volatile memory satisfies a condition, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses. In a case where the non-volatile memory does not satisfy the condition, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses. The second period is different from the first period.

Abstract: Distributed architecture for executing information management services using shared platform microservices, containerization techniques, and regional core services. This architecture decentralizes the traditional model by segmenting the various functions of the centralized control and information manager into modular cloud microservices. This modularization not only enhances system flexibility but also allows for a more dynamic configuration, with certain elements being deployable as containers. The resilient architecture leverages the inherent scalability and adaptability of cloud technology.

Abstract: A memory system is connectable to a host. The memory system comprises a semiconductor memory and a memory controller electrically connected to the semiconductor memory. The memory controller, upon receiving a command from the host, the command instructing to update one or more of the plurality of firmwares stored in the first block, change at least one of a plurality of firmwares stored in any one of a plurality of slots of a first block, and change an active slot information stored in a first area of the first block.

Abstract: One example method includes copying selected backup data from a secondary storage system to a provisioned primary storage volume, creating a snapshot of the primary storage volume, using the snapshot to create a thin clone volume, masking the thin clone volume, and mounting the thin clone volume, and recovering the backup data from the thin clone volume. The recovered backup data may be made available to a secondary workload that includes an enterprise application.

Abstract: Techniques perform data detection. Such techniques involve determining, based on a start sector address of a first mapping range composed of sectors in a physical address space, a first mapping region where the start sector address is located, the first mapping range corresponding to a first virtual block. Such techniques further involve comparing the first mapping region with a second mapping region, a second mapping range corresponding to a second virtual block different from the first virtual block at least partially corresponding to the second mapping region. Such techniques further involve comparing the first mapping range with the second mapping range in response to the first mapping region being the same as the second mapping region. Such techniques further involve determining that the first mapping range overlaps the second mapping range in response to that the first mapping range and the second mapping range have a common range.

Abstract: A control circuit for a non-volatile memory array includes an interface to receive requests, a common request queue connected to the interface and a common request buffer connected to the common request queue. The common request buffer is configured to receive the requests from the common request queue in their received order and buffer unfinished requests directed to memory addresses such that for any address in the non-volatile memory array no more than one unfinished request is in the common request buffer.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support packed commands for improved performance and reduced power consumption. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving a plurality of commands from a storage driver for execution by a flash memory device; packaging, by the memory controller of the host device, the plurality of commands as a packed command in a packet; and transmitting, by the memory controller of the host device to the flash memory device, the packet comprising the packed command for execution by the flash memory device. The use of packed commands may be based on determining the command acknowledgement delay from the flash memory device exceeds a threshold delay. Other aspects and features are also claimed and described.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for management of suspend and resume operations in a memory system are described. An example system includes a memory device and a controller. The controller is configured to: while performing data transfer to the memory device for a first operation corresponding to a first command, check whether a second command is received, wherein performing the data transfer to the memory device comprises performing the data transfer in terms of allocation units (AUs). In response to determining that the second command is received and that data transfer in a current AU is completed, the controller sends a suspend command to the memory device.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device.

Abstract: A memory control device (20) includes an arbiter (21) that accepts an access request to a memory (10) including a plurality of bank groups each of which has a plurality of banks, and a memory controller (23) that issues a command corresponding to the access request accepted by the arbiter (21), and in a case where the arbiter (21) accepts an access request to a first bank group of the plurality of bank groups, the arbiter (21) suspends acceptance of another access request to the first bank group.

Abstract: Techniques detect a sequential stream. Such techniques involve receiving a plurality of input/outputs (IOs). Such techniques further involve storing corresponding IO descriptors in a pool for the received plurality of IOs. Such techniques further involve predicting the plurality of IOs as a target sequential stream according to a plurality of IO descriptors stored in the pool that correspond to a first set of IOs. Such techniques further involve determining that the received plurality of IOs are the target sequential stream in response to detecting that the plurality of IO descriptors stored in the pool match a second set of IOs. The second set of IOs is a plurality of IOs sequentially arranged subsequent to the first set of IOs in the target sequential stream.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may retrieve, from a solid state drive (SSD), information that includes an original storage size of the SSD, a number of terabytes written, and a number of program/erase (P/E) cycles that occurred within the SSD; determine that a number of terabytes written is not above the threshold value of terabytes written; determine a threshold number of P/E cycles remaining associated with the SSD; determine that a number of P/E cycles remaining of the SSD is above the threshold number of P/E cycles remaining associated with the SSD; determine an overprovisioning percentage, which would produce a write amplification factor at or below a write amplification factor threshold, based at least on the number of P/E cycles remaining; determine configuration data for the SSD; and configure the SSD with the configuration data.

Abstract: A data storage device tracks information about the ages and read counts of blocks of memory, which are indicative of data retention and read disturb issues, respectively. The data storage device uses a machine-learning model to predict which blocks in the memory are likely to contain errors based on the tracked information, and a read scrub operation is performed only on those blocks. Limiting the number of blocks that are read scrubbed reduces read amplification and reduces the time required for the read scrub process.

Abstract: A system includes a non-volatile memory configured with a wear-leveling media pool, and a controller. The wear-leveling media pool has an initial endurance limit and is divided into a plurality of virtual partitions. Each virtual partition is assigned a respective endurance threshold. The controller is configured to monitor a first endurance parameter for each virtual partition based on the first endurance parameter for a respective virtual partition satisfying or not satisfying the respective endurance threshold of the respective virtual partition, evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions.

Abstract: The present disclosure relates generally to computer systems and, more particularly, to a cache refresh system and related processes and methods of use. The method of refreshing data in cache memory includes: setting, by a computer system, a refresh indicator to “true”; refreshing data in the cache memory, by the computer system, upon a determination that the refresh indicator is set to “true”; and setting, by the computer system, the refresh indicator to “false” after the refreshing of the cache memory.

Abstract: Disclosed are methods and systems that can perform a loopback operation during a power loss protection (PLP) procedure. In some implementations, a method includes identifying, upon issuance of a command abort signal for aborting a command queued in the memory system, a current state of the command, receiving, by the memory system, one or more input/output (IO) packets corresponding to the current state of the command, and performing operations corresponding to the command on the one or more IO packets.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to select a source block, read metadata associated with the source block and compare to a logical block address to physical block address (L2P) table, determine if a flash management unit (FMU) of the source block is valid, and add a new entry associated with the FMU into a valid FMU buffer when the FMU of the source block is determined to be valid. The controller is further configured to determine that the source block has been fully validated and select a next source block based on a valid counter. The valid counter corresponds to an amount of valid data of the next source block.

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

Abstract: In some embodiments of the disclosed technology, a memory controller may include a data strobe signal (DQS) calibration circuit configured to calibrate timing of a data strobe signal (DQS) for a plurality of memory dies by performing N unit DQS calibration operations, wherein N is a natural number, wherein performing the N unit DQS calibration operations includes: performing M unit DQS calibration operations in a normal mode on the plurality of memory dies, wherein M is a natural number smaller than N; upon failure of calibration during the M unit DQS calibration operations in the normal mode, determining a representative memory die of the plurality of memory dies that causes the failure of calibration; and performing N?M unit DQS calibration operations in a conditional mode on the plurality of memory dies by varying parameters associated with the representative memory die of the plurality of memory dies.

Abstract: A storage system configuration alternation system implements storage system reconfiguration alternation by determining a first set of storage system optimization policies to be applied during periods where the workload on the storage system is primarily transactional, and determining a second set of storage system optimization policies to be applied during periods where the workload on the storage system is primarily bandwidth intensive. The storage system configuration alternation system monitors the storage system workload to identify whether the storage system workload is primarily transactional or primarily bandwidth intensive. Based on the current monitored determination, the configuration alternation system selectively applies either the first or second set of storage system policies. A primarily bandwidth intensive workload may be determined based on a combination of a high percentage read IO operations of maximum read size, low CPU utilization, and high back-end bandwidth utilization.

Abstract: A memory cell array includes a first bank of memory cells, a second bank of memory cells adjacent to the first bank of memory cells, a first set of bit lines and a second set of bit lines. The first set of bit lines extend in a first direction, is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. The second set of bit lines extend in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate.

Abstract: A storage device may search for a target page among pages included in a first memory block of a plurality of memory blocks each including a plurality of pages, and when an uncorrectable error occurs while reading data stored in the target page, may overwrite dummy data into the target page and then store address information indicating a location of the target page in a second memory block among the plurality of memory blocks.

Abstract: A semiconductor memory device, and a method of operation, includes a memory block including a plurality of memory strings. The semiconductor memory device also includes a peripheral circuit performing a main program operation on drain select transistors included in the memory block, and a test program operation and a threshold voltage monitoring operation on memory cells included in the memory block. The semiconductor memory device further includes control logic controlling the peripheral circuit to detect a disturb susceptible memory string, among the plurality of memory strings, based on a result of performing the threshold voltage monitoring operation on the memory cells, and to perform an additional program operation on a drain select transistor included in the disturb susceptible memory string.

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract: Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

Abstract: Implementations described herein relate to memory devices including a single-level cell (SLC) block storing data for migration to multiple multi-level cell (MLC) blocks. In some implementations, a memory device includes multiple MLC blocks that include MLCs, with each MLC being capable of storing at least four bits of data, and multiple SLC blocks that can store data prior to the data being written to one of the MLC blocks. Each SLC block may be capable of storing different data sets that are destined for storage in different MLC blocks. The memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the SLC blocks and a corresponding MLC block for which data stored in the memory location is destined. Numerous other implementations are described.

Abstract: An apparatus includes processing circuitry that performs data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier, and configuration application circuitry applies the set of memory transaction parameters with respect to memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation and a maximum target allocation of a storage capacity of at least part of a memory system in handling the memory transaction that identifies the partition identifier.

Abstract: Provided is a storage controller for controlling a storage memory. The storage memory includes at least one first tier memory and at least one second tier memory. The first tier memory has a higher access speed than the second tier memory. The storage memory is being arranged to store memory blocks of data grouped in memory chunks associated with an index. A memory chunk indicates the size of a memory operation. The storage controller is configured to determine that a memory chunk is to be moved from the first tier memory to the second tier memory, and write the memory chunk to the second tier memory. The storage controller is configured to receive a read request for the memory chunk and in response thereto determine whether the memory chunk is current in the first tier memory, and if so, read the memory chunk from the first tier memory.

Abstract: An apparatus in an illustrative embodiment comprises at least one processing device that includes a processor coupled to a memory. The at least one processing device is configured to maintain for a first storage system a plurality of index tables characterizing data replicated between the first storage system and respective ones of at least two or more additional storage systems, to receive a request to replicate a particular data item between the first storage system and a designated one of the two or more additional storage systems, to access, responsive to the received request, a corresponding one of the index tables characterizing data replicated between the first storage system and the designated one of the two or more additional storage systems, and to control replication of the particular data item based at least in part on one or more entries of the corresponding one of the index tables.

Abstract: Described are techniques for application-consistent snapshots. The techniques include determining that a scheduled snapshot of a storage volume is imminent, where the storage volume stores input/output (I/O) data associated with an application that executes on a host server. The techniques further include initiating at least one host buffer flush prior to the scheduled snapshot being performed, where I/O data in a host buffer associated with the application is transferred to a write cache of the storage volume to reduce an amount of I/O data in the host buffer when performance of the scheduled snapshot begins. The techniques further include initiating, after the host buffer flush has completed, a write cache flush to write the I/O data in the write cache to the storage volume. The techniques further include initiating the scheduled snapshot of the storage volume in response to an indication that the write cache flush has completed.

Abstract: Methods, systems, and computer-readable storage media for receiving a workload period, during which a workload is applied to a database system, providing a set of ML models based on historical data representative of historical executions of the workload over the workload period, each ML model configured to predict a cluster arrival rate curve (cARC), and during execution of the workload period and, for each timeslice of a plurality of timeslice of the workload period: providing a predicted cARC from each ML model, the predicted cARC representative of a predicted workload, determining column visiting times for each of a plurality of columns of each of a plurality of tables stored in the database system, generating a column list based on the column visiting times, and loading column data representative of columns included in the column list into low-latency memory prior to execution of a workload during the respective timeslice.

Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Abstract: A storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device including a plurality of zones, a memory device including a plurality of zones; a buffer memory device including a plurality of slots; and a memory controller including a plurality of zone buffers respectively corresponding to the plurality of zones. The memory controller may store write data in one or more of the plurality of slots, store map data corresponding to the write data in a zone buffer that corresponds to a zone in which the write data is to be stored, and then store the write data, which is stored in the one or more slots, in the zone corresponding to the zone buffer based on the map data stored in the zone buffer.

Abstract: A memory system includes a nonvolatile memory, a memory controller, and a control circuit including a buffer and configured to store a first address transmitted by the memory controller in the buffer, generate a second address based on the first address stored in the buffer, and transmit the generated second address to the nonvolatile memory.

Abstract: Dynamic memory area configuration includes designating a portion of memory as a specialized memory unit, and reserving a first portion of specialized memory unit for a plurality of page frame table entries (PFTEs) representing a plurality of frames in the specialized memory. One or more of the PFTEs are stored in respective queue entries within a queue in a reserved area of the specialized memory unit. A particular queue entry indicates that a particular PFTE associated with a particular frame is available for use. An offline request to take a second portion of the specialized memory unit offline is received. Whether to fulfill the offline request is determined based on whether the second portion of the specialized memory unit has an associated queue entry within the queue indicating that the associated frame is not in use back a portion of a page frame table (PFT) or the specialized memory unit.

Abstract: This application provides a table entry reading method and apparatus, a network device, and a computer-readable storage medium. The method includes: when a read command is received from an interface module, determining a target controller from a plurality of controllers by polling according to a preset polling rule, and determining a correspondence between the interface module and the target controller; sending the read command to the target controller, so that the target controller obtains a table entry corresponding to the read command from a target memory corresponding to the target controller in a plurality of memories; and receiving the table entry returned by the target controller, and sending the table entry to the interface module based on the correspondence between the interface module and the target controller.

Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Abstract: Systems, methods and products for performing file retention operations in a system in which a content management system accesses multiple cloud-based data stores that are compliant with a common file transfer protocol, but use different vendor-specific protocols for file retention operations, where a retention framework is coupled between the content management system and the data stores. The content management system performs file access operations by accessing an SDK that generates requests for these operations which follow the common set of protocols. The content management system performs file retention operations by accessing a retention framework that uses the information received from the content management system to identify the targeted file, identify the data store in which the targeted file is stored, and generate a request for a retention operation that is configured according to the data-store-specific retention protocols which correspond to the identified data store.

Abstract: Systems and methods for monitoring memory accesses. A storage system comprises a first memory device, a second memory device, and a controller configured to communicate with the first memory device and the second memory device. The controller is configured to: receive, from a computing device, a first request for first data; identify a first address based on the first request; search the first memory device for the first address; modify a first count maintained in the second memory device for the first address; receive from the computing device a second request; and provide the first count in response to the second request.

Abstract: Utilizing multiple redundancy schemes within a unified storage element, including: receiving, in a storage system at a unified storage element that integrates both fast durable storage and bulk durable storage, a data storage operation from a host computer; storing, in accordance with a first data resiliency technique that corresponds to a RAID N+R format, data corresponding to the data storage operation within the fast durable storage of the unified storage element; and responsive to determining that the complete RAID stripe has been written to the fast durable storage, moving a portion of the stored data from the fast durable storage to the bulk durable storage of the unified storage element, the bulk durable storage storing the data in accordance with a second data resiliency technique that corresponds to a RAID M+R format, wherein M is different from N.

Abstract: An information processing system includes a processor configured to: receive a job; divide the job into multiple job divisions; and for each job division, when the job division is set to be processed by using a local functionality processed in a local environment including the information processing system, cause the local environment to process the job division, and, when the job division is set to be processed by using a cloud functionality processed in a cloud environment which does not include the information processing system, cause the cloud environment to process the job division.

Abstract: An image forming system includes an image former, a first reader, and a second reader. The image former forms an image on a recording medium. The first reader is disposed upstream of the image former in a conveyance direction of the recording medium, and reads the recording medium. The second reader is disposed downstream side of the image former in the conveyance direction of the recording medium, and reads the recording medium. Based on a result of reading the recording medium in one of the first reader and the second reader, the other of the first reader and the second reader is controlled.

Abstract: A non-transitory computer-readable storage medium storing a printer driver that enables information related to a fixed price print service to be easily confirmed before printing. The printer driver includes a code for displaying a print setting screen for receiving a print setting for printing by a printer on a display unit of an information processing apparatus in which the printer driver is installed, and a code for displaying information related to a fixed price print service with the printer on the display unit.

Abstract: Communication setting information for use in UWB communication is exchanged between a mobile terminal and an image forming apparatus by BLE communication. When the mobile terminal transmits job data to which information of a ranging target to the image forming apparatus by UWB communication based on the exchanged communication setting information, the image forming apparatus having received the data starts ranging and transmits ranging request data to the ranging target based on the information of the ranging target added to the data.

Abstract: A printing system comprising first and second information processing apparatuses connected and an image forming apparatus. The first information processing apparatus performs a first print service that stores a print job. The second information processing apparatus performs the second print service that holds a maximum print amount and a current print amount. The first print service obtains the maximum print amount and the current print amount from the second print service when the image forming apparatus executes the print job, determines whether a total of a print amount according to the print job and the current print amount exceeds the maximum print amount, and if the total of the print amount according to the print job and the current print amount does not exceed the maximum print amount, causes the image forming apparatus to execute the print job.