Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that can correct residual bit errors. The bit errors correctable by the ECC schemes not only include those errors that have been existing in input data used for the RAID process, but also those bit errors may have been propagated due to the existing errors.

Abstract: Methods and apparatus for preference based selection of storage network memory for data storage. In an example, a computing device receives a data object for storage in memory of the storage network and determines a system level storage efficiency preference associated with the data object. The computing device selects a set of storage nodes of a plurality of sets of storage nodes for storage of the data object based, at least in part, on the system level storage efficiency preference. The computing device further determines dispersed storage error encoding parameters for the data object, encodes the data object in accordance with the dispersed storage error encoding parameters to produce encoded data slices, and generates system addressing information for the encoded data slices.

Abstract: A method for performing checkpointing for fault tolerance of an application is provided, which is performed by one or more processors, and includes storing accelerator data associated with an application at a specific time point as a checkpoint, storing operation data associated with the application performed after the specific time point, and performing application fault tolerance based on the checkpoint and the stored operation data.

Abstract: Data associated with an object to be stored is received from a source system for a destination logical storage container selected among a plurality of destination logical storage containers. A total number of the destination logical storage containers allowed to be concurrently supported by the source system is limited. The selected destination logical storage container is shared by a plurality of objects of the source system. Based at least in part on an identifier associated with the object, a child logical storage container corresponding to the object is identified. The child logical storage container is different from the selected destination logical storage container. The data associated with the object received for the selected destination logical storage container is automatically stored in the identified child logical storage container.

Abstract: A process for performing a dedicated backup in a containerized environment is provided. In example aspects, a backup pod performs a backup process for an associated application. The backup pod is customized to contain backup tools that are specific to the backup process for the associated application. The backup pod works in connection with a backup manager that may interface with different backup pods customized for use in conjunction with different containerized applications. In some cases, the backup manager coordinates with each backup pod to provide backup processes for the different containerized applications.

Abstract: A network system for running distributed environment applications is provided, including a main network part for interface between devices belonging to a plurality of device groups, and a sub-network part for interface between devices belonging to sub-device group, in which the sub-device group includes at least some of the devices belonging to each of different device groups.

Abstract: Systems and methods are disclosed for generating a backup of configuration information files at a system controller and storing this backup at a server via the use of a network device.

Abstract: A method and system for efficient data recovery via change block tracking and replication comprising storing data using secured and immutable storage snapshots from a plurality of first devices on a plurality of storage arrays via a first network path and a second network path, determining a condition of data loss, power loss, or a cyber compromise event, and based on determining the condition, instantiating recovery of data using the secured and immutable storage snapshots from the plurality storage arrays via a third network path.

Abstract: A data retention event preparation/recovery system includes a chassis, a plurality of NAND subsystems included in the chassis, and a data retention event preparation/recovery subsystem that is included in the chassis and coupled to the plurality of NAND subsystems. The data retention event preparation/recovery subsystem determines that the plurality of NAND subsystems will experience a data retention event and, in response, identifies a first subset of the plurality of NAND subsystems that exceed an error threshold, identifies at least one overprovisioned block in the plurality of NAND subsystem, copies data that is stored on the first subset of the plurality of NAND subsystems to the at least one overprovisioned block in the plurality of NAND subsystems, and power offs the plurality of NAND subsystems to begin the data retention event.

Abstract: Disclosed in embodiments of the present application are a BIOS problem locating method and apparatus, and a medium. The method includes: constructing functional modules according to historical sample data; according to node information corresponding to each functional module, dividing data codes corresponding to the functional modules into data sub-codes; determining target identifier information according to correspondence between the data sub-codes and identifier information; when a problem occurs to a certain data sub-code, storing the target identifier information to a preset memory; and if an anomaly occurs to BIOS operation, according to the target identifier information recorded in the memory, quickly locating the abnormal target data sub-code.

Abstract: A method for testing a computer system. The method includes executing by a testing tool a performance test case associated with a service of the computer system, and applying by the testing tool a load to the computer system in response to executing a sequence of actions of the performance test case. The method additionally includes monitoring by a monitoring tool experience parameters of the computer system that define a user experience of the service as the performance test case is executed, and aggregating by the monitoring tool the experience parameters. The method further includes communicating by the monitoring tool and actual result to the testing tool, and comparing by the testing tool the expected result of the performance test case with the actual result of the performance test case to evaluate the impact of the applied load to the experience of the service.

Abstract: Embodiments described herein relate to a method for recommending changes to a system that includes a remote access controller (RAC). The one or more embodiments of the invention described above may improve the functioning of an information handling system (IHS) and the ability to use an RAC for troubleshooting and correcting problems with the IHS, even when the IHS is off-line or experiencing an OS failure. In one or more embodiments of the invention a bare metal orchestrator, which is separate from the IHS, monitors the IHS and uses machine learning to determine when to switch the RAC from shared mode to dedicated mode, so that the RAC is in a dedicated mode when it is probable that the IHS will fail.

Abstract: Systems, methods, and computer-readable media for intercepting telemetry events obtained during operation of an application and analyzing the telemetry events are provided. The analysis can generate vulnerability reports that are supplemented with contextual data to assist a user in remediation efforts.

Abstract: Systems, methods, and computer-readable media for intercepting telemetry events obtained during operation of an application and analyzing the telemetry events are provided. The analysis can generate drift reports that can inform users at which point in time a particular change to the software affected an operation thereof.

Abstract: A method and system for rendering a stack trace visualization display has been developed. A first stack trace associated with execution of an application during a time period is received from a central processing unit profiler. A first stack trace visualization display is rendered including a plurality of stack frames stacked in accordance with an order of ancestry based on the first stack trace. Rendering at least one stack frame involves rendering at a first location of the first stack trace visualization display, a stack frame rectangle for the at least one stack frame in accordance with the order of ancestry and rendering at a second location of the first stack trace visualization display, stack frame specific text for the at least one stack frame. The second location overlays the first location. Rendering of the stack frame rectangle is independent of the rendering of the stack frame specific text.

Abstract: A method comprises analyzing application data and performance data of a plurality of devices using one or more machine learning techniques. In the method, performance states of respective ones of the plurality of devices are determined, and priorities of applications of the respective ones of the plurality of devices is determined based at least in part on the analyzing. The method further comprises predicting a priority of the plurality of devices based at least in part on the performance states and the priorities of the applications. A report of the priority of the plurality of devices is generated.

Abstract: A method for system monitoring in a hierarchical network of distributed edge devices includes a master edge, first and second client edges connected via a first communication interface to the master edge, the method including receiving sensor data from a sensor device via a second communication interface, determining a first local model parameter representing a machine learning (ML) model of the at least first client edge based on the sensor data; storing the first local model parameter in a data storage of the at least first client edge; collecting the first local model parameter from the at least first client edge; and generating a global ML model based on the at least first local model parameter, wherein the global ML model is used for monitoring a system performance or a condition of the system.

Abstract: A computing resource allocation system receives entity resource usage data describing computing resource usage of an executable service platform by an entity as part of a first allocation generated using a first allocation mechanism. A computing resource allocation system generates an entity resource model based on the entity resource usage data of the computing resource usage of the executable service platform as part of the first allocation mechanism. A computing resource allocation system simulates computing resource usage of the executable service platform by the entity as part of a second allocation mechanism based on the entity resource model and the entity resource usage data. A computing resource allocation system estimates a second allocation to provide to the entity based on the simulating.

Abstract: Systems and methods provide for an integrated script development and script validation platform. The integrated script development and script validation platform archives data in a way such that the dependencies between contributions of code strings (e.g., script sets) are detected and recorded. That is, the systems and methods detect dependency branches in the script code of script sets. By doing so, the systems and methods may identify individual performance characteristics for a given script set as well as determine the overall impact on the application itself.

Abstract: An embodiment for a method of using machine learning algorithms to proactively identify potential errors in code instance data for creating technical documentation. The embodiment may receive code instance data. The embodiment may generate error classifications for the received code instance data using a convolutional neural network and natural language processing techniques. The embodiment may perform a correlation analysis to derive correlations between the generated error classifications for the received code instance data and similarly occurring classifications in one or more historical code instances. The embodiment may calculate a score for each of the derived correlations, the calculated score corresponding to a likelihood that the similarly occurring classifications in the one or more other code instances represents a potential error. The embodiment may output notifications to a user for each of the derived correlations for which the calculated score exceeds a threshold value.

Abstract: Methods, systems, and computer-readable storage media for receiving a crash report provided as a computer-readable file, providing a stack trace from the crash report, adding component information to the stack trace, for each component identified in the stack trace, determining a set of features, processing sets of features through a ML model to provide a prediction identifying a component as a bug component, and assigning the bug component for resolution through a crash management system.

Abstract: Computer executable instructions including code sections are received and compared to previously analyzed computer executable instructions. The code sections are then analyzed and assigned a risk score. If the risk score is over a threshold, an alarm may be communicated or the system may substitute computer executable instructions that may have been created according to a standard or have been previously approved.

Abstract: The present disclosure provides a log supervision method and a system. The method includes: acquiring, by a mobile terminal, a log generated by an application; adding, by the mobile terminal, a device id, a startup id and an event id to the log to obtain a standardized log, where the device id is used for uniquely identifying the mobile terminal, the startup id is used for identifying a number of times of startup of the application after the application is installed, and the event id is used for identifying a number of times of event occurrence of the application after the application is installed; sending, by the mobile terminal, the standardized log to a server; summarizing, by the server, all standardized logs from different mobile terminals, and determining whether the standardized logs are incorrect.

Abstract: A method and system for automated and role-based control of a centralized marketplace for products. The method includes: mapping a first role, from among a plurality of predetermined roles of marketplace participants, to a first user based on first registration information, mapping a second role, from among the plurality of predetermined roles of marketplace participants, to a second user based on second registration information; executing, for the first user, a first microservice based on the first role of the first user, the first role being a developer role; and executing, for the second user, a second microservice based on the second role of the second user, the second role being a customer role, wherein the first microservice comprises a publishing process for publishing a product of the first user in the centralized marketplace, and wherein the second microservice comprises a deployment process for deploying the product to an infrastructure of the second user.

Abstract: Software applications often incorporate an embedded browser to perform web-based operations. Not all browsers operate the same way, for example, elements within tabs in Microsoft Edge browsers use messages to communicate through web extensions, while Microsoft Internet Explorer (IE) browsers use the original browsers helper object (BHO). A consequence of the different paradigms is that certain graphical elements may be duplicated in a resource table. A test development may fail to identify the duplication and may produce extraneous or erroneous tests. By launching on a system and monitoring the system's executing processes, a browser application may be determined to be running and, if so, a refresh operation is performed on an application under test (AUT). If the AUT refresh operation results in a browser also performing a refresh, the type of embedded browser may be identified and any duplicates of the same graphical elements identified and merged for subsequent testing.

Abstract: A computing device for automatic management of test cases for testing of source code associated with computer software applications. The computing device accesses an original corpus of source code. One or more previously-generated test cases associated with the original corpus of source code are accessed. An updated corpus of source code is accessed, the updated corpus of source code an update from the original corpus of source code. The computing device generates automatically one or more new test cases for testing of the updated corpus of source code, the one or more new test cases automatically generated based upon the accessed one or more previously-generated test cases. The updated corpus of source code is compiled. The compiled updated corpus of source code is executed with the one or more new test cases.

Abstract: A computing system encodes a next graph based on modified source code files recorded by the next code commit event. The computing system inputs the next graph to a graph machine learning model, the graph machine learning model being trained by graphs representing modified source code files and software test results corresponding to multiple code commit events occurring prior to the next code commit event in the sequence of code commit events. The computing system determines an order of test cases of the next code commit event using the graph machine learning model in an inference mode. The computing system executes the test cases according to the order during the software development build process corresponding to the next code commit event.

Abstract: A semiconductor storage device according to an embodiment includes a first word line connected to a gate of a first memory cell transistor, a second word line connected to a gate of a second memory cell transistor, a first word line selection transistor capable of supplying a voltage from a voltage supply circuit to the first word line, a second word line selection transistor capable of supplying the voltage from the voltage supply circuit to the second word line, an insulating film provided between the first word line selection transistor and the second word line selection transistor, and a first wiring having at least a part provided on the insulating film and extending in a first direction, in which the voltage supply circuit is capable of supplying a first voltage lower than a ground voltage to the first wiring.

Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.

Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.

Abstract: According to one embodiment, a controller, in response to receiving, from a host, a first command requesting secure erase of secure erase target data associated with a first logical area identifier, stores a copy of first mapping information that corresponds to the first logical area identifier, among mapping information that is included in a first table. The controller executes at least a data erase operation for one or more first blocks storing the secure erase target data. In a first mode, the controller, in response to receiving, from the host, a read command that specifies the first logical area identifier, reads data from a storage location corresponding to a first physical address that is mapped to the first logical area identifier in the copy of the first mapping information.

Abstract: A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.

Abstract: Systems and methods for memory representation and management are disclosed. A request to allocate memory in a first storage medium is identified. The first storage medium may be associated with a first tier of a memory hierarchy. The memory may be represented via at least a first node of a first data structure in response to the request. The first data structure may be associated with the first tier. Activity associated with a memory address represented by the first node may be tracked, and an order for the first node in the first data structure may be updated based on the activity. An association of the first node may be moved from the first data structure to a second data structure. The second data structure may be associated with a second tier of the memory hierarchy.

Abstract: Disclosed is a power loss protection method. In some implementations, the method includes initiating a timer to indicate a progress of a power loss protection procedure that performs a data transfer upon occurrence of a power loss interrupt event, initiating a first data transfer operation to transfer a first amount of data to a memory device, and upon an indication by the timer that the power loss protection procedure has reached a predetermined progress level, continuing the first data transfer operation until the first amount of data is transferred to the memory device, or upon an indication by the timer that the power loss protection procedure has failed to reach the predetermined progress level, discontinuing the first data transfer operation and performing a second data transfer operation to transfer a second amount of data to the memory device, wherein the second amount is less than the first amount.

Abstract: A controller includes at least one register configured to store a doorbell regarding a submission queue storing at least one request generated by a host, a first cache configured to store data corresponding to a first result of an operation performed in response to the at least one request, a second cache configured to store data corresponding to a second result of an operation performed in response to a read look ahead (RLA) request generated based on the at least one request, and a cache size manager configured to adjust a size of the second cache based on an update cycle of the doorbell and a change of a number of the at least one request corresponding to the doorbell.

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Abstract: In one embodiment, a processor includes interconnect circuitry, processing circuitry, a first cache, and cache controller circuitry. The interconnect circuitry communicates over a processor interconnect with a second processor that includes a second cache. The processing circuitry generates a memory read request for a corresponding memory address of a memory. Based on the memory read request, the cache controller circuitry detects a cache miss in the first cache, which indicates that the first cache does not contain a valid copy of data for the corresponding memory address. Based on the cache miss, the cache controller circuitry requests the data from the second cache or the memory based on a current bandwidth utilization of the processor interconnect.

Abstract: There is provided a memory controller including an interface and a processor. The processor fetches a memory request in one of a plurality of queues storing a plurality of memory requests from a host, compares a destination address of the memory request with a first stored destination address, among one or more stored destination addresses in a storage, associates the memory request with the first stored destination address in the storage based on a match between the destination address of the memory request and the first stored destination address in the storage, and processes one or more entries in the storage in response to the memory request.

Abstract: Provided are a computer program product, system, and method for providing demotion hints with track access requests. A track access request is generated for a track in the storage system. A determination is made whether the track access request is for a designated utility. The track access request is submitted with a demotion hint to cause the track to be indicated on a transient cache list in response to determining that the track access request is for the designated utility. The track access request is submitted without a demotion hint in response to determining that the track access request is not for the designated utility to cause the track to be indicated on a prolonged cache list. The demotion of tracks is first attempted from the transient cache list before demoting tracks from the prolonged cache list.

Abstract: Techniques are provided for atomic writes for persistent memory. In response to receiving a write operation, a new per-page structure with a new page block number is allocated. New data of the write operation is persisted to a new page of the persistent memory having the new page block number, and the new per-page structure is persisted to the persistent memory. If the write operation targets a hole after the new data and the new per-page structure have been persisted, then a new per-page structure identifier of the new per-page structure is inserted into a parent indirect page of a page comprising the new data. If the write operation targets old data after the new data and the new per-page structure have been persisted, then an old per-page structure of the old data is updated with the new page block number.

Abstract: Caching techniques can include: receiving a read I/O operation requesting to read from a logical address; determining whether a mapping cache includes a descriptor for the logical address, the mapping cache including two hash tables; responsive to determining that the mapping cache includes the descriptor for the logical address, performing read hit mapping cache processing which includes using a physical location identified by the descriptor to read content stored at the logical address; and responsive to determining that the mapping cache does not include the descriptor for the logical address, performing read miss mapping cache processing which includes adding the descriptor to the mapping cache. Read miss mapping cache processing can include adding the descriptor to a first hash table, used to access the descriptor by the logical address, and adding the descriptor to a second hash table used to access the descriptor by the physical location.

Abstract: Caching techniques can include: receiving, from a host, a read I/O operation requesting to read from a logical address; determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing read hit mapping cache processing including: obtaining physical location information from the descriptor, wherein the physical location information identifies a physical location on non-volatile storage including first content stored at the logical address; reading, using the physical location information, the first content from the physical location; performing validation processing to validate the first content using a hash value included in the descriptor; and responsive to validation processing successfully validating the first content, returning the first content to the host.

Abstract: Computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. Use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. To reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual memory to continuous regions of physical memory, thereby increasing the coverage of each entry in the virtual address translation hierarchy. The present disclosure provides hardware support for optimizing this huge memory page selection.

Abstract: A method for solving a Cache address alias and an apparatus for solving a Cache address alias are provided. The method includes determining a corresponding first virtual address based on a received access instruction; querying an address maintenance list to determine a target item corresponding to the first virtual address when an access based on the first virtual address is not hit, information recorded in the target item including a target Tag, a target address alias bit, and a target Cache; determining a second virtual address based on the first virtual address and the target item, and setting information in the second virtual address to be invalid, in which the second virtual address and the first virtual address are mapped to the same physical address; and acquiring information corresponding to the access instruction and writing it back to the first virtual address.

Abstract: Apparatuses, systems, and techniques to manage a cache located on a processor of a computing system using eviction priority based on based on memory reuse. Memory addresses associated with a workload of an application executing using the processor are identified. An amount of reuse of the memory addresses corresponding to the workload is determined. A cache management policy for the workload is determined based on the amount of reuse. The cache management policy is applied to the cache.

Abstract: Systems and methods for a storage system are disclosed. The storage system includes a first storage medium, a processor configured to communicate with the first storage medium, and a memory coupled to the processor. The memory stores instructions that, when executed by the processor, cause the processor to: receive a request for accessing data; search the first storage medium based on the request; receive a command from a computing device, the command including a configuration parameter; and based on the command, modify architecture of the first storage medium from a first architecture to a second architecture corresponding to the configuration parameter.

Abstract: Systems and methods are disclosed for error management in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a world identifier checker circuitry configured to check memory requests for one or more memory mapped resources that are received via the bus that have been tagged with a world identifier to determine whether to allow or reject access based on the tagged world identifier; a world identifier checker circuitry configured to compare the tagged world identifier to a world list for a resource that specifies which world identifiers supported by the integrated circuit are authorized for access to the resource; and a data store configured to store world error data, including the tagged world identifier of a memory request that has been rejected by the world identifier checker circuitry.

Abstract: Provided are a computer program product, system, and method for using a transient cache list and prolonged cache list to manage tracks in cache based on a demotion hint with a track access request. A track is staged into the cache in response to a request for the track. A determination is made as to whether the request provides a demotion hint. The track is indicated in a transient cache list in response to determining that the request provides the demotion hint. The track is indicated in a prolonged cache list in response to determining that the request does not provide the demotion hint. The track is demoted from the cache in response to the request for the track comprising a read request, returning the track to the read request, and the track is indicated in the transient cache list.

Abstract: A device driver comprises a device controller and a first encoder provides encoder data according to a first encoder protocol capable of being converted to an associated first controller protocol. In the device driver, encoder data conforming to a first encoder protocol is received, wherein: the first encoder protocol is not the same as a second encoder protocol, the second encoder protocol is capable of being converted to an associated second controller protocol that is not the same as a first controller protocol associated with the first encoder protocol, and the device controller is configured according to the second controller protocol. The encoder data is converted, according to at least one controller protocol conversion rule, into converted controller data conforming to the second controller protocol that is thereafter provided to the device controller.