Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a fiducial having a length size greater than a width size of the fiducial, wherein the fiducial comprises at least one first area and at least one second area, wherein the at least one first area is to stop light from a light source and the at least one second area is to pass light from the light source during a determination of an alignment between the first integrated circuit device and a second integrated circuit device.

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.

Abstract: A semiconductor device includes a semiconductor substrate, a first test pattern disposed on the semiconductor substrate, and a second test pattern located adjacent to the first test pattern. The first test pattern includes an overlay pattern, and the second test pattern includes a test element group.

Abstract: Aligning pillars of a three-dimensional NAND memory assembly can include forming a first pillar and a corresponding first pillar alignment feature in at least a portion of a first substrate stack. The alignment method can include depositing a second substrate stack on the first substrate stack, covering the first pillar alignment feature and the first pillar, and depositing a first masking layer on at least a portion of the second substrate stack. Illumination light can be used to illuminate a portion of the first masking layer. A reflected portion of the illumination light can indicate a location of the first pillar alignment feature corresponding to the first pillar. Particular wavelengths of the illumination light can be blocked or filtered by the first masking layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first conductive feature, a first light-emitting feature, a first pattern and a second pattern. The first light-emitting feature is disposed on the substrate. The first pattern is disposed on the first light-emitting feature. The second pattern is disposed on the first pattern. The first conductive feature is disposed on the substrate and at least laterally overlaps the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance to the light of the first wavelength. The second pattern has a second transmittance to the light of the first wavelength. The first transmittance is different from the second transmittance.

Abstract: The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and including a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark includes a fluorescence material.

Abstract: A structure comprising: metal lines and viabars that surround a periphery of an active area of a semiconductor device; at least one viabar that extends through multiple layers of the semiconductor device, wherein the at least one viabar connects a metal line of one layer of the structure with a metal line of another layer of the structure; and a connection viabar that terminates at a metal line of a layer between the one layer of the structure and the another layer of the structure, wherein a thickness of the connection viabar is less than a thickness of the at least one viabar.

Abstract: Methods for reducing warpage and increasing the effectiveness of hybrid bond void testing are disclosed. A semiconductor package has a first side and a second side, with a dummy bond pad located on the second side, and at least one metal-containing layer between the first side and the second side (for example a redistribution layer). A warpage control structure is provided in the semiconductor package that extends from the first side into the semiconductor package, and is aligned with the dummy bond pad. The warpage control structure is made of a low-density filling. This relieves stress that causes/increases warpage. When a hybrid bond is formed between the semiconductor package and another semiconductor package, the warpage control structure maximizes acoustic wave penetration for testing the quality of the hybrid bond at the dummy bond pad.

Abstract: An electronic device includes a semiconductor die having a semiconductor body, a metallization structure over the semiconductor body and a conductive terminal, the metallization structure including a top level having neighboring first and second top metal structures that extend in a plane of orthogonal first and second directions, the first top metal structure is electrically coupled to the conductive terminal, the conductive terminal extends over a portion of the first top metal structure and away from the plane along a third direction orthogonal to the first and second directions, and the first top metal structure is spaced apart from the second top metal structure in the plane by a spacing distance of 60 ?m or more.

Abstract: An electronic device includes a multilevel package substrate and a semiconductor die, where the multilevel package substrate has first and second levels in respective first and second planes in a stack, the first level including a first conductive feature, and the second level including a second conductive feature, and the semiconductor die has a conductive peripheral terminal, a conductive interior terminal, a peripheral region, and an interior region. The peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal extends from the peripheral region to the first level, the conductive interior terminal extends from the interior region to the first level, the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level has no conductive feature under the peripheral contact portion.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a stack structure including a cell array region and a contact region extending from the cell array region, a cell plug penetrating the cell array region of the stack structure, a conductive gate contact penetrating the contact region of the stack structure, and a plurality of first support structures bordering a perimeter of the conductive gate contact and disposed to be spaced apart from the center of the conductive gate contact at a first distance.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

Abstract: An integrated circuit (IC) device includes an IC die on a substrate, and the substrate includes a group of conductive lines between a high-permittivity dielectric layer and a low-permittivity dielectric layer, with a ground plane separated from the conductive lines by either the high- or low-permittivity dielectric layer. The substrate may include other low-permittivity dielectric layers. The substrate may include other groups of conductive lines between ground planes. The high-permittivity dielectric layer may be within a low-permittivity dielectric core layer.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of III-V material. Other embodiments may be described and/or claimed.

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

Abstract: A package structure and a formation method are provided. The package structure includes a chip structure bonded to a substrate through dielectric-to-dielectric bonding and metal-to-metal bonding and interconnect dielectric layers formed over the chip structure. The package structure further includes interconnect conductive structures formed in the interconnect dielectric layers and a transmission line formed in the interconnect dielectric layers. The package structure further includes a magnetic structure formed in the interconnect dielectric layers and separated from the transmission line by the interconnect dielectric layers. In addition, the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structures.

Abstract: A compact antenna module with integrated thermal management. The module includes at least one antenna and amplifier such as power amplifiers or low-noise amplifiers. An anisotropic thermal interface material is positioned such that it is in thermal communication with these components. The anisotropic thermal interface material includes plural aligned thermally anisotropic composite layers having a first thermal conductivity in a first direction and a second, larger thermal conductivity in a second direction and extend substantially parallel to each other in the first direction. The layers include hexagonal boron nitride (hBN) in a binder aligned in the second direction approximately perpendicular to the first direction such that x-y planes of the hBNalign in the second direction. In this manner, the thermal conductivity in the second direction is at least 13.5 W/mK, with a dielectric constant of less than 4, and a loss tangent of less than 0.007.

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

Abstract: A first conductive feature of a first substrate is bonded to a second conductive feature of a second substrate. The first conductive feature is formed by depositing a conductive base layer on the first substrate, the first substrate having an opening formed therein, recessing the conductive base layer in the opening, and depositing a conductive surface layer on the recessed conductive base layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive feature and the second conductive feature.

Abstract: The present disclosure is directed to package-on-package structures having a package substrate with an embedded logic package disposed on the package substrate and having heat conductive pathways being provided in the package-on-package structure for removing heat from the logic package. In an aspect, the heat conductive pathways enable a downward transfer of the heat generated by the logic package toward the package substrate. In another aspect, the heat conducting pathways may include a heat transfer layer formed proximally to a bottom surface of the logic package. In a further aspect, the heat conducting pathways may include one or more metal vias in the package substrate.

Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first metal pad provided on a first surface of the first chip and a first circuit connected to the first metal pad. The second chip has a second surface bonded to the first surface of the first chip. The second chip includes a second metal pad provided on the second surface and bonded to the first metal pad, and a second circuit connected to the second metal pad. The first metal pad has a first recess formed in the first surface, and a first carbon film is provided in the first recess.

Abstract: A semiconductor package includes a first semiconductor chip including first bonding pads disposed in a first main region on a first surface of a first substrate, first dummy bonding pads disposed in a first peripheral region on the first surface of the first substrate, and a first passivation layer disposed on the first surface, and a second semiconductor chip on the first semiconductor chip and including a wiring layer on a third surface of a second substrate and including redistribution pads in a second main region, second bonding pads disposed on the redistribution pads, second dummy bonding pads disposed in a second peripheral region on the wiring layer, and a second passivation layer disposed on the wiring layer. The first bonding pads and the second bonding pads are directly bonded to each other. The first dummy bonding pads and the second dummy bonding pads are directly bonded to each other.

Abstract: A method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. The first dielectric layer is bonded to the second dielectric layer. At a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

Abstract: A structure includes a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion and a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The structure further includes an interface layer having at least one electrically conductive oxide material between the first layer and the second layer. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion, and at least one second region between the at least one electrically insulative second portion and the at least one electrically insulative fourth portion.

Abstract: One embodiment provides a solder alloy including Ag in a content of 2.7 wt % to 3.3 wt %. Cu in a content of 0.50 wt % to 0.75 wt %. Bi in a content of 0.8 wt % to 1.2 wt %. Ni in a content of 0.03 wt % to 0.10 wt %. Pd in a content of 0.01 wt % to 0.04 wt %, and a remainder of Sn and unavoidable impurities.

Abstract: A unified crackstop structure is described incorporating at least two semiconductor builds, each having a crackstop structure on its periphery and a metal wall or line extending from one crackstop structure to the other.

Abstract: A semiconductor package comprise: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a set of front conductive patterns formed on the front surface; a set of rear conductive patterns formed on the rear surface; and a set of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns via a set of front solder balls; a set of rear solder balls electrically connected to the set of rear conductive patterns, respectively; wherein the set of front solder balls comprises one or more first-type solder balls and one or more second-type solder balls, and the set of rear solder balls comprises one or more first-type solder balls and one or more second-type solder balls; and wherein the first-type solder balls of the set of front solder balls are elec

Abstract: An electronic device includes a semiconductor die, a support structure and bond wires, where the semiconductor die has a semiconductor body, a metallization structure over the semiconductor body, and a conductive terminal, the metallization structure includes a top level that extends in a plane of orthogonal first and second directions, the conductive terminal extends away from the plane along an orthogonal third direction, and the support structure has a conductive metal feature with an attachment location. The bond wires are on the attachment location and a package structure at least partially encloses the semiconductor die and a portion of the support structure, where the conductive terminal is soldered to the attachment location of the conductive feature over at least some of the bond wires.

Abstract: According to an example aspect of the present invention, there is provided a bonding structure for forming at least one electrical connection between an optoelectronic component and a photonic substrate. The bonding structure comprises a pillar structure between the optoelectronic component and the photonic substrate, and a bonding layer comprising bonding material on the pillar structure. The pillar structure for at least one individual electrical connection comprises at least two portions and at least one gap between the portions for receiving extra bonding material of the bonding layer.

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the set of second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

Abstract: A semiconductor device includes a cavity package including a substrate and at least one output lead disposed higher than the substrate, in a side view, to create a cavity. A transistor die is disposed within the cavity. A top surface of the transistor die is lower than a top surface of the output lead when viewed in the side view. A first substrate is disposed within the cavity and is separate from the transistor die. A top surface of the first substrate is lower than the top surface of the output lead in the side view. A shunt wire connects an output of the transistor die to the first substrate, and an output wire connects the output of the transistor substrate to the output lead. The shunt wire or the output wire is disposed and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire.

Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.

Abstract: A bonded assembly may be formed by performing a chip plasma clean process on a semiconductor chip; generating at least one chip infrared image of a cleaned side of the semiconductor chip; measuring an average emissivity of at least one metallic region in the at least one chip infrared image; performing a subsequent processing step selected from a bonding step and an alternative processing step based on the measured average emissivity. The bonding step is performed if the measured average emissivity is less than a predetermined emissivity threshold value. The alternative processing step is performed if the measured average emissivity is greater than the predetermined emissivity threshold value. The alternative processing step may be selected from an additional clean step and an additional inspection step.

Abstract: Compliant inserts for pin dipping processes are disclosed herein. An example apparatus disclosed herein includes a pin array to transfer material to a package substrate of an integrated circuit package, a cover plate, an elastic insert to be disposed between the cover plate and the pin array.

Abstract: The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.

Abstract: A method of manufacturing a batch of semiconductor assemblies is provided. The method includes coupling dies to die paddles, the die paddles being provided on a lead frame in a 2×n array in pairs having an opposing orientation. Each die paddle defines a respective semiconductor assembly. The method further includes coupling connectors to the dies, and moulding a fused casing over the semiconductor assemblies using a mould which surrounds the 2×n array, the fused casing at least partly surrounding the 2×n array. The method further includes cutting the fused casing at, at least three positions, partially surrounding an individual one of the 10 plurality of semiconductor assemblies, and punching a lead side of the semiconductor assembly, to define an individual casing, from the fused casing, and singulate the semiconductor assembly from the 2×n array.

Abstract: Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.

Abstract: A semiconductor package may include a first redistribution layer, bridge dies on an upper surface of the first redistribution layer, a second redistribution layer on the bridge dies and electrically connected to the bridge dies, conductive posts between the first and second redistribution layer, and semiconductor chips on an upper surface of the second redistribution layer. Each bridge die may include connection pads on an upper surface of the bridge dies. A pitch between first connection pads of a first bridge die among the bridge dies may be smaller than a pitch between second connection pads of a second bridge die among the bridge dies. A distance between an upper surface of the first bridge die and a lower surface of the second redistribution layer may be smaller than a distance between an upper surface of the second bridge die and a lower surface of the second redistribution layer.

Abstract: Semiconductor device assemblies with support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

Abstract: A package structure includes a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.

Abstract: A stacking structure including a first die and a second die bonded with the first die is provided. The first die has a first region and a second region encircled by the first region. The first die includes first metallization structures having a first seal ring structure and a first bonding structure having first dummy pads located over the first seal ring structure. The second die includes second metallization structures having a second seal ring structure and a second bonding structure having second dummy pads located over the second seal ring structure. The first die and the second die are bonded through bonding of the first and second bonding structures. The first and second seal ring structures are substantially vertically aligned, and the first dummy pads are respectively bonded with the second dummy pads.