Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
  • Patent number: 10468304
    Abstract: Implementations of a method of separating a wafer from a boule including semiconductor material may include: creating a damage layer in a boule comprising semiconductor material. The boule may have a first end and a second end. The method may include cooling the first end of the boule and heating the second end of the boule. A thermal gradient may be formed between the cooled first end and the heated second end. The thermal gradient may assist a silicon carbide wafer to separate from the boule at the damage layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10446753
    Abstract: A vapor deposition apparatus in which a deposition process is performed by moving a substrate, the vapor deposition apparatus including a supply unit that injects at least one raw material gas towards the substrate, and a blocking gas flow generation unit that is disposed corresponding to the supply unit and generates a gas-flow that blocks a flow of the raw material gas.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Kwang Kim, Seung-Yong Song, Myung-Soo Huh, Suk-Won Jung, Choel-Min Jang, Jae-Hyun Kim, Sung-Chul Kim
  • Patent number: 10407799
    Abstract: The disclosure relates to a semimetal compound of Pt and a method for making the same. The semimetal compound is a single crystal material of PtSe2. The method comprises: providing a PtSe2 polycrystalline material; placing the PtSe2 polycrystalline material in a reacting chamber; placing chemical transport medium in the reacting chamber; evacuating the reacting chamber to be vacuum less than 10 Pa; placing the reacting chamber at a temperature gradient, wherein the reacting chamber has a first end at a temperature of 1200 degrees Celsius to 1000 degrees Celsius and a second end opposite to the first end and at a temperature of 1000 degrees Celsius to 900 degrees Celsius; and keeping the reacting chamber in the temperature gradient for 10 days to 30 days.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 10, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke-Nan Zhang, Ming-Zhe Yan, Shu-Yun Zhou, Yang Wu, Shou-Shan Fan
  • Patent number: 10361273
    Abstract: A silicon carbide substrate whose majority carrier density is 1×1017 cm?3 or greater is such that a standard deviation of minority carrier lifetime as obtained by ?-PCD analysis is 0.7 ns or less in an area other than an area within a distance of 5 mm from an outer perimeter of a main surface.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 23, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Kaji, Shunsaku Ueta, Tsutomu Hori, Shin Harada
  • Patent number: 10354862
    Abstract: An apparatus for manufacturing a group III nitride single crystal including: a reaction vessel including a reaction area, wherein in the reaction area, a group III source gas and a nitrogen source gas are reacted such that a group III nitride crystal is grown on a substrate; a susceptor arranged in the reaction area and supporting the substrate; a group III source gas supply nozzle supplying the group III source gas to the reaction area; and a nitrogen source gas supply nozzle supplying the nitrogen source gas to the reaction area, wherein the nitrogen source gas supply nozzle is configured to supply the nitrogen source gas and at least one halogen-based gas selected from the group consisting of a hydrogen halide gas and a halogen gas to the reaction area.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 16, 2019
    Assignee: TOKUYAMA CORPORATION
    Inventors: Toru Nagashima, Masayuki Fukuda
  • Patent number: 10312426
    Abstract: Lanthanum strontium manganate (La0.67Sr0.33MnO3, i.e., LSMO)/lanthanum manganate (LaMnO3, i.e., LMO) perovskite oxide metal/semiconductor superlattices were investigated for potential p-type thermoelectric applications. Growth optimizations were performed using pulsed laser deposition to achieve epitaxial superlattices of LSMO (metal)/LMO (p-type semiconductor) on strontium titanate (STO) substrates. The cross-plane Seebeck coefficient of the thermoelectric superlattice measured between the substrate and the capping layer has a value of at least 1600 ?V/K measured at about 300K.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 4, 2019
    Assignee: Purdue Research Foundation
    Inventors: Pankaj Jha, Timothy D. Sands
  • Patent number: 10232855
    Abstract: An electronic control unit (11) of a drive assist apparatus (10) acquires electric power source identification information for identifying a source of an electric power currently charged in a battery and electric power amount information representing an electric power amount corresponding to the source from an electric power acquisition unit (14), thereby recognizing a battery remaining amount SOCrg representing a green electric power, a battery remaining amount SOCj representing a privately generated green electric power, and a battery remaining amount SOCrs representing a non-green electric power. The unit (11) presents travelable ranges each formed by connecting a group of maximum reachable points to which a PHV can reach by using each of a battery total remaining amount SOCr and the battery remaining amounts SOCrg, SOCj, and SOCrs to a user (driver) by using an information presentation unit (12).
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 19, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Matsumoto, Kentaro Takahashi, Masato Endo
  • Patent number: 10184191
    Abstract: Provided is a method for manufacturing a silicon carbide single crystal capable of easily separating a silicon carbide single crystal from a pedestal. The method includes the step of fixing a seed substrate to a pedestal with a stress buffer layer being interposed therebetween, the step of growing a silicon carbide single crystal on the seed substrate, the step of separating the silicon carbide single crystal from the pedestal at the stress buffer layer, and the step of removing a residue of the stress buffer layer adhering to the silicon carbide single crystal subjected to the step of separating.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 22, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tsutomu Hori, Shunsaku Ueta, Akira Matsushima
  • Patent number: 10145026
    Abstract: Methods for large-scale manufacturing of semipolar gallium nitride boules are disclosed. The disclosed methods comprise suspending large-area single crystal seed plates in a rack, placing the rack in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and growing crystals ammonothermally. A bi-faceted growth morphology may be maintained to facilitate fabrication of large area semipolar wafers without growing thick boules.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: December 4, 2018
    Assignee: SLT TECHNOLOGIES, INC.
    Inventors: Mark P. D'Evelyn, Dirk Ehrentraut, Derrick S. Kamber, Bradley C. Downey
  • Patent number: 10103174
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 16, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 10094017
    Abstract: A process of preparing polycrystalline group III nitride chunks comprising the steps of (a) placing a group III metal inside a source chamber; (b) flowing a halogen-containing gas over the group III metal to form a group III metal halide; (c) contacting the group III metal halide with a nitrogen-containing gas in a deposition chamber containing a foil, the foil comprising at least one of Mo, W, Ta, Pd, Pt, Ir, or Re; (d) forming a polycrystalline group III nitride layer on the foil within the deposition chamber; (e) removing the polycrystalline group III nitride layer from the foil; and (f) comminuting the polycrystalline group III nitride layer to form the polycrystalline group III nitride chunks, wherein the removing and the comminuting are performed in any order or simultaneously.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 9, 2018
    Assignee: SLT TECHNOLOGIES, INC.
    Inventors: Douglas W. Pocius, Derrick S. Kamber, Mark P. D'Evelyn, Jonathan D. Cook
  • Patent number: 10081883
    Abstract: Provided is a method for producing a SiC single crystal having a concave growth surface and containing no inclusions, even when conducting large diameter crystal growth. This is achieved by a method for producing a SiC single crystal in which a seed crystal substrate held on a seed crystal holding shaft is contacted with a Si—C solution having a temperature gradient such that the temperature decreases from the interior toward the liquid level, to cause crystal growth of a SiC single crystal, wherein the seed crystal holding shaft has a shaft portion and a seed crystal holding portion at the bottom end of the shaft portion, and the ratio of the diameter D1 of the shaft portion to the diameter D2 of the seed crystal holding portion (D1/D2) is no greater than 0.28.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: September 25, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Motohisa Kado, Hironori Daikoku, Kazuhiko Kusunoki, Kazuaki Seki
  • Patent number: 10062567
    Abstract: In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped III-V semiconductor materials are also provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Christian Lavoie
  • Patent number: 10056477
    Abstract: A nitride heterojunction bipolar transistor with one or more polarization-assisted alloy hole-doped short-period superlattice layers are described herein. The transistor may comprise a substrate, a sub-collector region coupled to the substrate, a collector region coupled to the sub-collector portion, a base portion region to the collector portion, and a short-period superlattice (SPSL) emitter region coupled to the base portion. The SPSL emitter includes a plurality of first emitter layers and a plurality of second emitter layers that are alternating layers that form the SPSL emitter. The first emitter layers have a lower bandgap than the second emitter layers, and the vertical transport through the SPSL emitter region occurs via quantum tunneling. Other embodiments are also described.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 21, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Suk Choi, Christopher L. Chua, Noble M. Johnson
  • Patent number: 10048142
    Abstract: Provided are a method by which the degrees of the strains of lattices in a plurality of bulk SiC single crystals can be relatively evaluated, and a reference SiC single crystal to be used in the method.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: August 14, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Kiyoshi Kojima, Masashi Nakabayashi
  • Patent number: 10023795
    Abstract: Embodiments of the invention provide a ceramic composites and synthesis methods that include providing a plurality of nanoparticles with at least one first rare-earth single-crystal compound, and mixing the plurality of nanoparticles with at least one ceramic material and at least one ceramic binder including at least one solvent. The method further includes preparing a ceramic green-body from the mixture, and sintering the ceramic green-body to form a ceramic composite of a polycrystalline ceramic with a plurality of embedded single-crystal nanorods. The embedded single-crystal nanorods include at least one second rare-earth single crystal compound. The at least one second rare-earth single crystal compound can include or be derived from the at least one first rare-earth single crystal compound.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 17, 2018
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventor: Cun-Zheng Ning
  • Patent number: 9985181
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Patent number: 9919972
    Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 20, 2018
    Assignee: Melior Innovations, Inc.
    Inventors: Mark S. Land, Ashish P. Diwanji, Andrew R. Hopkins, Walter J. Sherwood, Douglas M. Dukes, Glenn Sandgren, Brian L. Benac
  • Patent number: 9916996
    Abstract: A vapor phase growth method of growing a film on a substrate by supplying material gases to the substrate while heating the substrate with a heating unit according to an embodiment, the method includes: measuring a temperature of the substrate with a radiation thermometer; executing a temperature feedback control to control an output of the heating unit to cause a measurement value of the radiation thermometer to have a set value when a film is not grown on the substrate; and executing a constant output control to maintain an output of the heating unit constant when a film causing thin-film interference in a wavelength measured by the radiation thermometer is grown on the substrate.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 13, 2018
    Assignee: NuFlare Technology Inc.
    Inventors: Takumi Yamada, Takanori Hayano, Tatsuhiko Iijima, Yuusuke Sato
  • Patent number: 9899392
    Abstract: The inventive concepts provide silicon precursors, methods of forming a layer using the same, and methods of fabricating a semiconductor device using the same. The silicon precursor includes a silane group including two or more silicon atoms. The silicon precursor has a high and uniform adsorption property on surfaces of layers (e.g., a silicon layer, an oxide layer, and a nitride layer) that are mainly used when semiconductor devices are fabricated.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 20, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DOW CORNING CORPORATION
    Inventors: JunHyun Cho, Michael David Telgenhoff, Xiaobing Zhou, Kyunghye Jung, Younjoung Cho
  • Patent number: 9887131
    Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: February 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 9873938
    Abstract: A biaxially textured crystalline layer formed on a substrate using ion beam assisted deposition (IBAD) is provided. The biaxially textured crystalline layer includes an oriented CaF2 crystalline layer having crystalline grains oriented in both in-plane and out-of-plane directions, where the out-of-plane orientation is a (111) out-of-plane orientation. The oriented CaF2 crystalline layer is disposed for growth of a subsequent epitaxial layer and the CaF2 crystalline layer is an IBAD CaF2 layer. The biaxially textured CaF2 layer can be used in a photovoltaic cell, an electronic or optoelectronic device, an integrated circuit, an optical sensor, or a magnetic device.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 23, 2018
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Bruce M. Clemens, James R. Groves, Garrett J. Hayes, Bingrui Joel Li, Alberto Salleo
  • Patent number: 9837563
    Abstract: A method of forming a Group II-VI multijunction semiconductor device comprises providing a Group IV substrate, forming a first subcell from a first Group II-VI semiconductor material, forming a second subcell from a second Group II-VI semiconductor material, and removing the substrate. The first subcell is formed over the substrate and has a first bandgap, while the second subcell is formed over the first subcell and has a second bandgap which is smaller than the first bandgap. Additional subcells may be formed over the second subcell with the bandgap of each subcell smaller than that of the preceding subcell and with each subcell preferably separated from the preceding subcell by a tunnel junction. Prior to the removal of the substrate, a support layer is affixed to the last-formed subcell in opposition to the substrate.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 5, 2017
    Assignee: EPIR Technologies, Inc.
    Inventors: Sivalingam Sivananthan, James W. Garland, Michael W. Carmody
  • Patent number: 9831363
    Abstract: An epitaxially grown III-V layer is separated from the growth substrate. The III-V layer can be an inverted lattice matched (ILM) or inverted metamorphic (IMM) solar cell, or a light emitting diode (LED). A sacrificial epitaxial layer is embedded between the GaAs wafer and the III-V layer. The sacrificial layer is damaged by absorbing IR laser radiation. A laser is chosen with the right wavelength, pulse width and power. The radiation is not absorbed by either the GaAs wafer or the III-V layer. No expensive ion implantation or lateral chemical etching of a sacrificial layer is needed. The III-V layer is detached from the growth wafer by propagating a crack through the damaged layer. The active layer is transferred wafer-scale to inexpensive, flexible, organic substrate. The process allows re-using of the wafer to grow new III-V layers, resulting in savings in raw materials and grinding and etching costs.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: November 28, 2017
    Inventor: John Farah
  • Patent number: 9803293
    Abstract: The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of the ingots into wafers, annealing of the wafers in a manner that avoids dissociation or decomposition of the wafers. This annealing process is effective to improve transparency of the wafers and/or otherwise remove contaminants from wafers.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: October 31, 2017
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
  • Patent number: 9806176
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mark van Dal
  • Patent number: 9783881
    Abstract: A linear evaporation apparatus includes a thermal insulation chamber, and crucibles, evaporation material heaters and a mixing chamber installed in the thermal insulation chamber. The mixing chamber includes a flow limiting and adjusting layer, a flow channel adjusting member, a mixed layer and a linear evaporation layer. The flow limiting and adjusting layer is a rectangular sheet with flow limit holes corresponsive to the crucibles respectively; the flow channel adjusting member is an interconnected structure having at least one flow inlet corresponsive to some of the flow limit holes and at least one flow outlet, and the mixed layer is a substantially I-shaped sheet structure, and the linear evaporation layer is a rectangular sheet having a linear source evaporation opening tapered from both ends to the middle, so as to improve the uniformity of the thin film and the utilization of the evaporation materials.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 10, 2017
    Assignee: NATIONAL CHUNG-SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shih-Chang Liang, Wei-Chieh Huang, Chao-Nan Wei, Cuo-Yo Ni, Hui-Yun Bor
  • Patent number: 9777401
    Abstract: A method for producing a single crystal includes a step of placing a source material powder and a seed crystal within a crucible; and a step of growing a single crystal on the seed crystal. The crucible includes a peripheral wall part and a bottom part and a lid part that are connected to the peripheral wall part to close the openings of the peripheral wall part. In the step of growing the single crystal on the seed crystal, the crucible is disposed on a spacer so as to form a space starting directly below an outer surface of the bottom part, and the peripheral wall part and an auxiliary heating member that is placed so as to face the outer surface of the bottom part with the space therebetween are heated by induction heating to sublime the source material powder to cause recrystallization on the seed crystal.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: October 3, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsaku Ueta, Tsutomu Hori, Akira Matsushima
  • Patent number: 9741819
    Abstract: The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Xuan Zhang
  • Patent number: 9728412
    Abstract: An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 8, 2017
    Assignee: STMICROELECTRONICS S.R.L
    Inventors: Alessandra Alberti, Paolo Badala′, Antonello Santangelo
  • Patent number: 9691856
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Amlan Majumdar, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Patent number: 9663367
    Abstract: Systems and a method for forming carbon allotropes are described. An exemplary reactor system for the production of carbon allotropes includes a hybrid reactor configured to form carbon allotropes from a reactant gas mixture in a Bosch reaction. The hybrid reactor includes at least two distinct zones that perform different functions including reaction, attrition, catalyst separation, or gas separation.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 30, 2017
    Assignees: EXXON MOBIL UPSTREAM RESEARCH COMPANY, SOLID CARBON PRODUCTS, LLC
    Inventors: Russell J. Koveal, Jr., Terry A. Ring
  • Patent number: 9657409
    Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Melior Innovations, Inc.
    Inventors: Glen Sandgren, Ashish P. Diwanji, Andrew R. Hopkins, Walter J. Sherwood, Douglas M. Dukes, Mark S. Land, Brian L. Benac
  • Patent number: 9630160
    Abstract: Disclosed are an apparatus and method for continuously producing carbon nanotubes. More specifically, disclosed are an apparatus for continuously producing carbon nanotubes including i) a reactor to synthesize carbon nanotubes, ii) a separator to separate a mixed gas from the carbon nanotubes transferred from the reactor, iii) a filter to remove all or part of one or more component gases from the separated mixed gas, and iv) a recirculation pipe to recirculate the filtered mixed gas to the reactor for carbon nanotubes. Advantageously, the apparatus and method for continuously producing carbon nanotubes enable rapid processing, exhibit superior productivity and excellent conversion rate of a carbon source, significantly reduce production costs, reduce energy consumption due to decrease in reactor size relative to capacity, and generate little or no waste gas and are thus environmentally friendly.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: April 25, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Kwang-Hyun Chang, Jin-Do Kim, Kwang-Woo Yoon
  • Patent number: 9580837
    Abstract: In a method for growing bulk SiC single crystals using chemical vapor transport, wherein silicon acts as a chemical transport agent for carbon, a growth crucible is charged with a solid carbon source material and a SiC single crystal seed disposed therein in spaced relationship. A halosilane gas, such as SiCl4 and a reducing gas, such as H2, are introduced into the crucible via separate inlets and mix in the crucible interior. The crucible is heated in a manner that encourages chemical reaction between the halosilane gas and the reducing gas leading to the chemical reduction of the halosilane gas to elemental silicon (Si) vapor. The produced Si vapor is transported to the solid carbon source material where it reacts with the solid carbon source material yielding volatile Si-bearing and C-bearing molecules.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: February 28, 2017
    Assignee: II-VI Incorporated
    Inventors: Ilya Zwieback, Varatharajan Rengarajan, Bryan K. Brouhard, Michael C. Nolan, Thomas E. Anderson
  • Patent number: 9576793
    Abstract: An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Giuseppe Abbondanza
  • Patent number: 9551086
    Abstract: A method of preparing silicon carbide powder is provided, which includes mixing first silicon carbide powder with a liquid silicon carbide precursor, annealing the mixture at a first temperature and converting the silicon carbide precursor to a ?-phase silicon carbide particulate material, and annealing the material at a second temperature and grain-growing the first silicon carbide powder to second silicon carbide powder using the ?-phase silicon carbide particulate material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: January 24, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Kyoung Seok Min
  • Patent number: 9523157
    Abstract: The invention relates to the technology for producing three-dimensional monocrystals and can preferably be used in optoelectronics for manufacturing substrates for various optoelectronic devices, including light-emitting diodes that emit light in the ultraviolet region. The method for growing an AlN monocrystal by gas-phase epitaxy from a mixture containing a source of Al and NH3 comprises arranging the Al source and a substrate, with the growth surface of said substrate turned towards said Al source, opposite one another in a growth chamber, said source and substrate forming a growth zone, producing a flow of NH3 in the growth zone; and heating the Al source and the substrate to temperatures that ensure the growth of the AlN monocrystal on the substrate. The Al source used is only free Al, the substrate is pretreated with Ga and/or In, whereupon the Al source is cooled to a temperature of 800-900° C. and the substrate is annealed by being heated to a temperature of 1300-1400° C.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 20, 2016
    Inventors: Mikhail Yurievich Pogorelsky, Alexei Petrovich Shkurko, Alexei Nikolaevich Alexeev, Viktor Petrovich Chaly
  • Patent number: 9508531
    Abstract: The method of the present invention is related to a technique of efficiently purging source gases remaining on a substrate and improving in-plane uniformity of a substrate. The method of the present invention includes forming a thin film on a substrate accommodated in a process chamber by (a) supplying a source gas into the process chamber, and (b) supplying an inert gas into the process chamber while alternately increasing and decreasing a flow rate of the inert gas supplied into the process chamber and exhausting the source gas and the inert gas from the process chamber.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 29, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Koei Kuribayashi, Shinya Ebata
  • Patent number: 9440859
    Abstract: A silicon carbide powder includes at least one group selected from a first group comprising an alpha phase silicon carbide pulverulent body of which a granule size (D50) is greater than 0 ?m and less than 45 ?m with impurities less than 10 ppm, a second group comprising an alpha phase silicon carbide pulverulent body of which a granule size is greater than 45 ?m and less than 75 ?m with impurities less than 10 ppm, and a third group comprising an alpha phase silicon carbide pulverulent body of which a granule size is greater than 75 ?m and less than 110 ?m with impurities less than 10 ppm. In addition, a method for preparing a silicon carbide powder includes adding seeds to a beta silicon carbide powder, and forming an alpha silicon carbide powder by heat treating the beta silicon carbide powder.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: September 13, 2016
    Assignees: LG INNOTEK CO., LTD, RESEARCH BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Byung Sook Kim, Dong Geun Shin, Jung Eun Han, Kyoung Seok Min
  • Patent number: 9437776
    Abstract: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 6, 2016
    Assignee: Toshiba Corporation
    Inventors: Chao-Kun Lin, Heng Liu
  • Patent number: 9431536
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a top surface and a side surface. A width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Huang Wu, Jian-Shian Chen
  • Patent number: 9337164
    Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 10, 2016
    Assignee: Freescale Semiconductors, Inc.
    Inventor: Rama I. Hegde
  • Patent number: 9331233
    Abstract: A method of manufacturing at least one semiconducting micro- or nano-wire used for formation of an optoelectric structure, optoelectronic structures including the micro- or nano-wires, and a method enabling manufacture of the photoelectronic structures. The method includes providing a semiconducting substrate, forming a crystalline buffer layer on the substrate, the buffer layer having a first zone over at least part of its thickness composed mainly of magnesium nitride in a form MgxNy, and forming at least one semiconducting micro- or nano-wire on the buffer layer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 3, 2016
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Amelie Dussaigne, Philippe Gilet, Francois Martin
  • Patent number: 9328431
    Abstract: An apparatus for manufacturing a silicon carbide single crystal grows the silicon carbide single crystal on a surface of a seed crystal made from a silicon carbide single crystal substrate by supplying a material gas for silicon carbide from below the seed crystal. The apparatus includes a base having a first side and a second side opposite to the first side. The seed crystal is mounted on the first side of the base. The apparatus further includes a purge gas introduction mechanism for supporting the base and for supplying a purge gas to the base from the second side of the base. The base has a purge gas introduction path for discharging the supplied purge gas from the base toward an outer edge of the seed crystal.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 3, 2016
    Assignee: DENSO CORPORATION
    Inventors: Kazukuni Hara, Yuuichirou Tokuda
  • Patent number: 9324559
    Abstract: A multi chamber thin film deposition apparatus and a method for depositing films, is provided. Each chamber includes a three dimensional gas delivery system including process gases being delivered downwardly toward the substrate and laterally toward the substrate. A pumping system includes an exhaust port in each chamber that is centrally positioned underneath the substrate being processed and therefore the gas flow around all portions of the edge of the substrate are equally spaced from the exhaust port thereby creating a uniform gas flow profile which results in film thickness uniformity of films deposited on both the front and back surfaces of the substrate. The deposited films demonstrate uniform thickness on the front and back of the substrate and extend inwardly to a uniform distance on the periphery of the backside of the substrate.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lan Hai Wang, Ding-I Liu, Si-Wen Liao, Po-Hsiung Leu, Yong-Hung Yang, Chia-Ming Tai
  • Patent number: 9284682
    Abstract: A method for treating a fabric for ultraviolet radiation protection is disclosed which comprises the steps of adding zinc oxide nanoparticles to a solution of 3-glycidyloxypropyl-trimethoxysilane, adding silicon dioxide to the mixture of zinc oxide nanoparticles and 3-glycidyloxypropyl-trimethoxysilane, placing a fabric in the mixture of zinc oxide nanoparticles, 3-glycidyloxypropyl-trimethoxysilane, and silicon dioxide, curing the fabric, and washing the fabric.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 15, 2016
    Assignee: THE SWEET LIVING GROUP, LLC
    Inventors: Robert B Kramer, Ronald Kramer, Nicholas Marshall, Jason Rosenberg, Ram B Gupta
  • Patent number: 9252206
    Abstract: The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material 11 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 2, 2016
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Satoshi Torimi, Satoru Nogami, Tsuyoshi Matsumoto
  • Patent number: 9246049
    Abstract: A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×1018 cm?3 or more and 3×1019 cm?3 or less, and a thermal conductivity of 1.2 W/cmK or more and 3.5 W/cmK or less. Alternatively, the substrate has an electron mobility ? [cm2/Vs] of more than a value represented by loge?=17.7?0.288 logen and less than a value represented by loge?=18.5?0.288 logen, where the substrate has a n-type carrier concentration n [cm?3] that is 1.2×1018 cm?3 or more and 3×1019 cm?3 or less.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 26, 2016
    Assignee: SCIOCS COMPANY LIMITED
    Inventor: Yuichi Oshima
  • Patent number: 9222166
    Abstract: It is an objective of the invention to provide a slide part in which a seal member formed of an elastic body is in sliding contact with a hard member. There is provided a slide part comprising: a hard member having an amorphous carbon coating containing nitrogen formed on an outermost surface of a substrate; and a seal member formed of an elastic body, the seal member being in sliding contact with the hard member, wherein: content of the nitrogen in the coating is 3 at. % or more and 25 at. % or less, taking a total content of the carbon and the nitrogen in the coating as 100 at. %; the seal member contains fluorine at least in a sliding contact surface region thereof; and content of the fluorine in the surface region of the seal member is equal to or more than the nitrogen content in the coating.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 29, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Itto Sugimoto