Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
  • Patent number: 11685660
    Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Vapor deposition processes and articles formed by those processes utilizing such high purity SiOC and SiC.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 27, 2023
    Assignee: Pallidus, Inc.
    Inventor: Mark S. Land
  • Patent number: 11268209
    Abstract: A method for preparing a seed crystal including a protective film includes preparing i) a first layer composition of a first binder resin and a first solvent and ii) a second layer composition of a second binder resin, a filler, and a second solvent, applying the first layer composition to the rear surface of a seed crystal to form a first coating layer on the rear surface of the seed crystal and drying the first coating layer to form a first layer on the rear surface of the seed crystal, and applying the second layer composition onto the first layer to form a second coating layer on the first layer, followed by heat treating to form a second layer on the first layer wherein the first layer and the second layer are sequentially disposed on the rear surface of the seed crystal, and wherein the first layer has a thickness corresponding to 30% or less of the distance from the bottom surface of the first layer to the top surface of the second layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 8, 2022
    Assignee: SENIC INC.
    Inventors: Sang Ki Ko, Jung-Gyu Kim, Jung Woo Choi, Byung Kyu Jang, Kap-Ryeol Ku
  • Patent number: 11227771
    Abstract: An etching method for etching a substrate using a molten alkali, wherein, while an oxide coating is formed on the surface of the substrate PL to be etched in a high-temperature oxygen-containing environment, the surface to be etched is isotropically etched to remove the oxide coating using a molten alkali AL brought into a prescribed high-temperature range.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 18, 2022
    Inventors: Junichi Ikeno, Yohei Yamada, Hideki Suzuki
  • Patent number: 11145785
    Abstract: The present invention provides a semiconductor light emitting device including a substrate, a first semiconductor layer, a first cladding layer, an active layer, a second cladding layer and a second semiconductor layer, and a manufacturing method. The first semiconductor layer may be an n-type semiconductor including a III-V semiconductor or a II-VI semiconductor. The second semiconductor layer may be a p-type semiconductor including a I-VII semiconductor. The semiconductor light emitting device may further include a third cladding layer between the active layer and the second cladding layer, the third cladding layer including a III-V semiconductor or a II-VI semiconductor. Therefore, by providing the hybrid type semiconductor light emitting device and the manufacturing method thereof, the luminous efficiency limit of the p-type semiconductor can be overcome.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 12, 2021
    Assignee: PETALUX INC.
    Inventors: Do Yeol Ahn, Seung Hyun Yang
  • Patent number: 11004656
    Abstract: Disclosed are embodiments of an ion beam sample preparation and coating apparatus and methods. A sample may be prepared in one or more ion beams and then a coating may be sputtered onto the prepared sample within the same apparatus. A vacuum transfer device may be used with the apparatus in order to transfer a sample into and out of the apparatus while in a controlled environment. Various methods to improve preparation and coating uniformity are disclosed including: rotating the sample retention stage; modulating the sample retention stage; variable tilt ion beam irradiating means, more than one ion beam irradiating means, coating thickness monitoring, selective shielding of the sample, and modulating the coating donor holder.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: May 11, 2021
    Assignee: Gatan, Inc.
    Inventors: John Andrew Hunt, Steven Thomas Coyle, Michael Patrick Hassel-Shearer, Thijs C Hosman
  • Patent number: 10896776
    Abstract: A nano magneto-rheological fluid, comprising nano-scale magnetizable magnetic particles, wherein an average particle size or a minimum size in one dimension is less than 100 nanometers; and fluids used as carrier liquids, wherein the magnetic particles are dispersively distributed in the fluids. An apparatus for making the nanometric magnetorheological fluid including a ball mill, a settling separator located downstream of the ball mill for receiving the primary magnetic particles, a magnetic separator located downstream of and connected to the settling separator for receiving the upper layer of fluid containing fine magnetic particles, and an agitator for mixing the desired secondary magnetic particles with a carrier liquid and an additive.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 19, 2021
    Inventor: Yanling Liang
  • Patent number: 10886320
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10879062
    Abstract: A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes: controlling a temperature of a sputtering target, and modulating between a gallium-rich condition and a gallium-lean condition, wherein the gallium-rich condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, and wherein the gallium-lean condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value. Some embodiments include a load lock configured to load a substrate wafer into the system and remove the GaN structure from the system; and a plurality of deposition chambers, wherein the plurality of deposition chambers includes a GaN-deposition chamber configured to grow at least the first GaN layer on a template that includes the substrate wafer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 29, 2020
    Inventor: Robbie J. Jorgenson
  • Patent number: 10861722
    Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 8, 2020
    Inventors: Benjamin Colombeau, Sheng-Chin Kung, Patricia M. Liu
  • Patent number: 10851470
    Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 1, 2020
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
  • Patent number: 10830948
    Abstract: An embodiment of the invention relates to an optical device which is capable of realizing a secondary nonlinear optical phenomenon. The optical device is a fiber-type optical device which is comprised of glass containing SiO2, and includes a core region, a first cladding region, and a second cladding region. At least a part of a glass region configured by the core region and the first cladding region has such a repetition structure that a first section serving as a poled crystal region and a second section serving as an amorphous region are alternately disposed along a longitudinal direction of the optical device.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 10, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shigehiro Nagano
  • Patent number: 10753010
    Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Vapor deposition processes and articles formed by those processes utilizing such high purity SiOC and SiC.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 25, 2020
    Assignee: Pallidus, Inc.
    Inventor: Mark S. Land
  • Patent number: 10741762
    Abstract: The present invention relates to a method for the deposition of at least one layer of an organic material on a substrate by (a) providing a source of a solid organic material in an atmosphere at a pressure comprised between 50 and 200 kPa, (b) heating said organic material to a first temperature to produce a vapor of said organic material, (c) exposing at least one surface of a substrate having a second temperature lower than said first temperature to said vapor to deposit organic material from said vapor onto said at least one surface of said substrate.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 11, 2020
    Assignee: CLAP Co., Ltd.
    Inventors: Thomas Musiol, Dieter Freyberg, Jochen Brill
  • Patent number: 10685820
    Abstract: A sputtering target formed from monocrystalline silicon is provided, wherein a sputter surface of the sputtering target is a plane inclined at an angle that exceeds 1° and is less than 10° from a {100} plane. The sputtering target formed from monocrystalline silicon provides a sputtering target which yields superior mechanical strength as well as exhibiting a sputter performance which is equivalent to that of a {100} plane. From a different perspective, in addition to superior mechanical strength, the monocrystalline silicon sputtering target yields superior particle characteristics, sputtering rate, crack resistance, surface shape uniformity and other characteristics.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 16, 2020
    Inventors: Hiroshi Takamura, Ryosuke Sakashita, Shuhei Murata
  • Patent number: 10643908
    Abstract: A manufacturing method of a silicon epitaxial wafer having an epitaxial layer grown on a mirror wafer of silicon, including: using a PL measuring apparatus to measure photoluminescence (PL) spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line. The method enables sorting out a silicon epitaxial wafer which realizes a negligible level of white flaw failures in case of manufacturing an imaging element with the use of the silicon epitaxial wafer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 5, 2020
    Inventor: Yasushi Mizusawa
  • Patent number: 10546741
    Abstract: A selective growth method of selectively growing a thin film on an underlayer, on which an insulating film and a conductive film are exposed, includes: preparing a workpiece having the underlayer on which the insulating film and the conductive film are exposed; and selectively growing a silicon-based insulating film on the insulating film by repeating a plurality of times a first step of adsorbing an aminosilane-based gas onto the insulating film and the conductive film and a second step of supplying a reaction gas for reacting with the adsorbed aminosilane-based gas to form the silicon-based insulating film, wherein the conductive film is vaporized by reaction with the reaction gas so that the conductive film is reduced in thickness.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 28, 2020
    Inventors: Hiroki Murakami, Akira Shimizu
  • Patent number: 10522555
    Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Gunter Grasshoff, Carsten Peters
  • Patent number: 10513799
    Abstract: A method for manufacturing a silicon carbide single crystal includes: packing a silicon carbide source material into a crucible, the silicon carbide source material having a flowability index of not less than 70 and not more than 100; and sublimating the silicon carbide source material by heating the silicon carbide source material.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Sho Sasaki, Shin Harada, Tsutomu Hori
  • Patent number: 10468304
    Abstract: Implementations of a method of separating a wafer from a boule including semiconductor material may include: creating a damage layer in a boule comprising semiconductor material. The boule may have a first end and a second end. The method may include cooling the first end of the boule and heating the second end of the boule. A thermal gradient may be formed between the cooled first end and the heated second end. The thermal gradient may assist a silicon carbide wafer to separate from the boule at the damage layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 5, 2019
    Inventor: Michael J. Seddon
  • Patent number: 10446753
    Abstract: A vapor deposition apparatus in which a deposition process is performed by moving a substrate, the vapor deposition apparatus including a supply unit that injects at least one raw material gas towards the substrate, and a blocking gas flow generation unit that is disposed corresponding to the supply unit and generates a gas-flow that blocks a flow of the raw material gas.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 15, 2019
    Inventors: Jin-Kwang Kim, Seung-Yong Song, Myung-Soo Huh, Suk-Won Jung, Choel-Min Jang, Jae-Hyun Kim, Sung-Chul Kim
  • Patent number: 10407799
    Abstract: The disclosure relates to a semimetal compound of Pt and a method for making the same. The semimetal compound is a single crystal material of PtSe2. The method comprises: providing a PtSe2 polycrystalline material; placing the PtSe2 polycrystalline material in a reacting chamber; placing chemical transport medium in the reacting chamber; evacuating the reacting chamber to be vacuum less than 10 Pa; placing the reacting chamber at a temperature gradient, wherein the reacting chamber has a first end at a temperature of 1200 degrees Celsius to 1000 degrees Celsius and a second end opposite to the first end and at a temperature of 1000 degrees Celsius to 900 degrees Celsius; and keeping the reacting chamber in the temperature gradient for 10 days to 30 days.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 10, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke-Nan Zhang, Ming-Zhe Yan, Shu-Yun Zhou, Yang Wu, Shou-Shan Fan
  • Patent number: 10361273
    Abstract: A silicon carbide substrate whose majority carrier density is 1×1017 cm?3 or greater is such that a standard deviation of minority carrier lifetime as obtained by ?-PCD analysis is 0.7 ns or less in an area other than an area within a distance of 5 mm from an outer perimeter of a main surface.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 23, 2019
    Inventors: Naoki Kaji, Shunsaku Ueta, Tsutomu Hori, Shin Harada
  • Patent number: 10354862
    Abstract: An apparatus for manufacturing a group III nitride single crystal including: a reaction vessel including a reaction area, wherein in the reaction area, a group III source gas and a nitrogen source gas are reacted such that a group III nitride crystal is grown on a substrate; a susceptor arranged in the reaction area and supporting the substrate; a group III source gas supply nozzle supplying the group III source gas to the reaction area; and a nitrogen source gas supply nozzle supplying the nitrogen source gas to the reaction area, wherein the nitrogen source gas supply nozzle is configured to supply the nitrogen source gas and at least one halogen-based gas selected from the group consisting of a hydrogen halide gas and a halogen gas to the reaction area.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 16, 2019
    Inventors: Toru Nagashima, Masayuki Fukuda
  • Patent number: 10312426
    Abstract: Lanthanum strontium manganate (La0.67Sr0.33MnO3, i.e., LSMO)/lanthanum manganate (LaMnO3, i.e., LMO) perovskite oxide metal/semiconductor superlattices were investigated for potential p-type thermoelectric applications. Growth optimizations were performed using pulsed laser deposition to achieve epitaxial superlattices of LSMO (metal)/LMO (p-type semiconductor) on strontium titanate (STO) substrates. The cross-plane Seebeck coefficient of the thermoelectric superlattice measured between the substrate and the capping layer has a value of at least 1600 ?V/K measured at about 300K.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 4, 2019
    Assignee: Purdue Research Foundation
    Inventors: Pankaj Jha, Timothy D. Sands
  • Patent number: 10232855
    Abstract: An electronic control unit (11) of a drive assist apparatus (10) acquires electric power source identification information for identifying a source of an electric power currently charged in a battery and electric power amount information representing an electric power amount corresponding to the source from an electric power acquisition unit (14), thereby recognizing a battery remaining amount SOCrg representing a green electric power, a battery remaining amount SOCj representing a privately generated green electric power, and a battery remaining amount SOCrs representing a non-green electric power. The unit (11) presents travelable ranges each formed by connecting a group of maximum reachable points to which a PHV can reach by using each of a battery total remaining amount SOCr and the battery remaining amounts SOCrg, SOCj, and SOCrs to a user (driver) by using an information presentation unit (12).
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 19, 2019
    Inventors: Satoru Matsumoto, Kentaro Takahashi, Masato Endo
  • Patent number: 10184191
    Abstract: Provided is a method for manufacturing a silicon carbide single crystal capable of easily separating a silicon carbide single crystal from a pedestal. The method includes the step of fixing a seed substrate to a pedestal with a stress buffer layer being interposed therebetween, the step of growing a silicon carbide single crystal on the seed substrate, the step of separating the silicon carbide single crystal from the pedestal at the stress buffer layer, and the step of removing a residue of the stress buffer layer adhering to the silicon carbide single crystal subjected to the step of separating.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 22, 2019
    Inventors: Tsutomu Hori, Shunsaku Ueta, Akira Matsushima
  • Patent number: 10145026
    Abstract: Methods for large-scale manufacturing of semipolar gallium nitride boules are disclosed. The disclosed methods comprise suspending large-area single crystal seed plates in a rack, placing the rack in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and growing crystals ammonothermally. A bi-faceted growth morphology may be maintained to facilitate fabrication of large area semipolar wafers without growing thick boules.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: December 4, 2018
    Inventors: Mark P. D'Evelyn, Dirk Ehrentraut, Derrick S. Kamber, Bradley C. Downey
  • Patent number: 10103174
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 16, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 10094017
    Abstract: A process of preparing polycrystalline group III nitride chunks comprising the steps of (a) placing a group III metal inside a source chamber; (b) flowing a halogen-containing gas over the group III metal to form a group III metal halide; (c) contacting the group III metal halide with a nitrogen-containing gas in a deposition chamber containing a foil, the foil comprising at least one of Mo, W, Ta, Pd, Pt, Ir, or Re; (d) forming a polycrystalline group III nitride layer on the foil within the deposition chamber; (e) removing the polycrystalline group III nitride layer from the foil; and (f) comminuting the polycrystalline group III nitride layer to form the polycrystalline group III nitride chunks, wherein the removing and the comminuting are performed in any order or simultaneously.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 9, 2018
    Inventors: Douglas W. Pocius, Derrick S. Kamber, Mark P. D'Evelyn, Jonathan D. Cook
  • Patent number: 10081883
    Abstract: Provided is a method for producing a SiC single crystal having a concave growth surface and containing no inclusions, even when conducting large diameter crystal growth. This is achieved by a method for producing a SiC single crystal in which a seed crystal substrate held on a seed crystal holding shaft is contacted with a Si—C solution having a temperature gradient such that the temperature decreases from the interior toward the liquid level, to cause crystal growth of a SiC single crystal, wherein the seed crystal holding shaft has a shaft portion and a seed crystal holding portion at the bottom end of the shaft portion, and the ratio of the diameter D1 of the shaft portion to the diameter D2 of the seed crystal holding portion (D1/D2) is no greater than 0.28.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: September 25, 2018
    Inventors: Motohisa Kado, Hironori Daikoku, Kazuhiko Kusunoki, Kazuaki Seki
  • Patent number: 10062567
    Abstract: In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped III-V semiconductor materials are also provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Christian Lavoie
  • Patent number: 10056477
    Abstract: A nitride heterojunction bipolar transistor with one or more polarization-assisted alloy hole-doped short-period superlattice layers are described herein. The transistor may comprise a substrate, a sub-collector region coupled to the substrate, a collector region coupled to the sub-collector portion, a base portion region to the collector portion, and a short-period superlattice (SPSL) emitter region coupled to the base portion. The SPSL emitter includes a plurality of first emitter layers and a plurality of second emitter layers that are alternating layers that form the SPSL emitter. The first emitter layers have a lower bandgap than the second emitter layers, and the vertical transport through the SPSL emitter region occurs via quantum tunneling. Other embodiments are also described.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 21, 2018
    Inventors: Suk Choi, Christopher L. Chua, Noble M. Johnson
  • Patent number: 10048142
    Abstract: Provided are a method by which the degrees of the strains of lattices in a plurality of bulk SiC single crystals can be relatively evaluated, and a reference SiC single crystal to be used in the method.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: August 14, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Kiyoshi Kojima, Masashi Nakabayashi
  • Patent number: 10023795
    Abstract: Embodiments of the invention provide a ceramic composites and synthesis methods that include providing a plurality of nanoparticles with at least one first rare-earth single-crystal compound, and mixing the plurality of nanoparticles with at least one ceramic material and at least one ceramic binder including at least one solvent. The method further includes preparing a ceramic green-body from the mixture, and sintering the ceramic green-body to form a ceramic composite of a polycrystalline ceramic with a plurality of embedded single-crystal nanorods. The embedded single-crystal nanorods include at least one second rare-earth single crystal compound. The at least one second rare-earth single crystal compound can include or be derived from the at least one first rare-earth single crystal compound.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 17, 2018
    Inventor: Cun-Zheng Ning
  • Patent number: 9985181
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Patent number: 9919972
    Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 20, 2018
    Assignee: Melior Innovations, Inc.
    Inventors: Mark S. Land, Ashish P. Diwanji, Andrew R. Hopkins, Walter J. Sherwood, Douglas M. Dukes, Glenn Sandgren, Brian L. Benac
  • Patent number: 9916996
    Abstract: A vapor phase growth method of growing a film on a substrate by supplying material gases to the substrate while heating the substrate with a heating unit according to an embodiment, the method includes: measuring a temperature of the substrate with a radiation thermometer; executing a temperature feedback control to control an output of the heating unit to cause a measurement value of the radiation thermometer to have a set value when a film is not grown on the substrate; and executing a constant output control to maintain an output of the heating unit constant when a film causing thin-film interference in a wavelength measured by the radiation thermometer is grown on the substrate.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 13, 2018
    Assignee: NuFlare Technology Inc.
    Inventors: Takumi Yamada, Takanori Hayano, Tatsuhiko Iijima, Yuusuke Sato
  • Patent number: 9899392
    Abstract: The inventive concepts provide silicon precursors, methods of forming a layer using the same, and methods of fabricating a semiconductor device using the same. The silicon precursor includes a silane group including two or more silicon atoms. The silicon precursor has a high and uniform adsorption property on surfaces of layers (e.g., a silicon layer, an oxide layer, and a nitride layer) that are mainly used when semiconductor devices are fabricated.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 20, 2018
    Inventors: JunHyun Cho, Michael David Telgenhoff, Xiaobing Zhou, Kyunghye Jung, Younjoung Cho
  • Patent number: 9887131
    Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: February 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 9873938
    Abstract: A biaxially textured crystalline layer formed on a substrate using ion beam assisted deposition (IBAD) is provided. The biaxially textured crystalline layer includes an oriented CaF2 crystalline layer having crystalline grains oriented in both in-plane and out-of-plane directions, where the out-of-plane orientation is a (111) out-of-plane orientation. The oriented CaF2 crystalline layer is disposed for growth of a subsequent epitaxial layer and the CaF2 crystalline layer is an IBAD CaF2 layer. The biaxially textured CaF2 layer can be used in a photovoltaic cell, an electronic or optoelectronic device, an integrated circuit, an optical sensor, or a magnetic device.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 23, 2018
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Bruce M. Clemens, James R. Groves, Garrett J. Hayes, Bingrui Joel Li, Alberto Salleo
  • Patent number: 9837563
    Abstract: A method of forming a Group II-VI multijunction semiconductor device comprises providing a Group IV substrate, forming a first subcell from a first Group II-VI semiconductor material, forming a second subcell from a second Group II-VI semiconductor material, and removing the substrate. The first subcell is formed over the substrate and has a first bandgap, while the second subcell is formed over the first subcell and has a second bandgap which is smaller than the first bandgap. Additional subcells may be formed over the second subcell with the bandgap of each subcell smaller than that of the preceding subcell and with each subcell preferably separated from the preceding subcell by a tunnel junction. Prior to the removal of the substrate, a support layer is affixed to the last-formed subcell in opposition to the substrate.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 5, 2017
    Assignee: EPIR Technologies, Inc.
    Inventors: Sivalingam Sivananthan, James W. Garland, Michael W. Carmody
  • Patent number: 9831363
    Abstract: An epitaxially grown III-V layer is separated from the growth substrate. The III-V layer can be an inverted lattice matched (ILM) or inverted metamorphic (IMM) solar cell, or a light emitting diode (LED). A sacrificial epitaxial layer is embedded between the GaAs wafer and the III-V layer. The sacrificial layer is damaged by absorbing IR laser radiation. A laser is chosen with the right wavelength, pulse width and power. The radiation is not absorbed by either the GaAs wafer or the III-V layer. No expensive ion implantation or lateral chemical etching of a sacrificial layer is needed. The III-V layer is detached from the growth wafer by propagating a crack through the damaged layer. The active layer is transferred wafer-scale to inexpensive, flexible, organic substrate. The process allows re-using of the wafer to grow new III-V layers, resulting in savings in raw materials and grinding and etching costs.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: November 28, 2017
    Inventor: John Farah
  • Patent number: 9806176
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 31, 2017
    Inventor: Mark van Dal
  • Patent number: 9803293
    Abstract: The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of the ingots into wafers, annealing of the wafers in a manner that avoids dissociation or decomposition of the wafers. This annealing process is effective to improve transparency of the wafers and/or otherwise remove contaminants from wafers.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: October 31, 2017
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
  • Patent number: 9783881
    Abstract: A linear evaporation apparatus includes a thermal insulation chamber, and crucibles, evaporation material heaters and a mixing chamber installed in the thermal insulation chamber. The mixing chamber includes a flow limiting and adjusting layer, a flow channel adjusting member, a mixed layer and a linear evaporation layer. The flow limiting and adjusting layer is a rectangular sheet with flow limit holes corresponsive to the crucibles respectively; the flow channel adjusting member is an interconnected structure having at least one flow inlet corresponsive to some of the flow limit holes and at least one flow outlet, and the mixed layer is a substantially I-shaped sheet structure, and the linear evaporation layer is a rectangular sheet having a linear source evaporation opening tapered from both ends to the middle, so as to improve the uniformity of the thin film and the utilization of the evaporation materials.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 10, 2017
    Inventors: Shih-Chang Liang, Wei-Chieh Huang, Chao-Nan Wei, Cuo-Yo Ni, Hui-Yun Bor
  • Patent number: 9777401
    Abstract: A method for producing a single crystal includes a step of placing a source material powder and a seed crystal within a crucible; and a step of growing a single crystal on the seed crystal. The crucible includes a peripheral wall part and a bottom part and a lid part that are connected to the peripheral wall part to close the openings of the peripheral wall part. In the step of growing the single crystal on the seed crystal, the crucible is disposed on a spacer so as to form a space starting directly below an outer surface of the bottom part, and the peripheral wall part and an auxiliary heating member that is placed so as to face the outer surface of the bottom part with the space therebetween are heated by induction heating to sublime the source material powder to cause recrystallization on the seed crystal.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: October 3, 2017
    Inventors: Shunsaku Ueta, Tsutomu Hori, Akira Matsushima
  • Patent number: 9741819
    Abstract: The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 22, 2017
    Inventors: Haiyang Zhang, Xuan Zhang
  • Patent number: 9728412
    Abstract: An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 8, 2017
    Inventors: Alessandra Alberti, Paolo Badala′, Antonello Santangelo
  • Patent number: 9691856
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Amlan Majumdar, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Patent number: 9663367
    Abstract: Systems and a method for forming carbon allotropes are described. An exemplary reactor system for the production of carbon allotropes includes a hybrid reactor configured to form carbon allotropes from a reactant gas mixture in a Bosch reaction. The hybrid reactor includes at least two distinct zones that perform different functions including reaction, attrition, catalyst separation, or gas separation.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 30, 2017
    Inventors: Russell J. Koveal, Jr., Terry A. Ring