Forming From Vapor Or Gaseous State (e.g., Vpe, Sublimation) Patents (Class 117/84)
  • Patent number: 10332974
    Abstract: A method of making a semiconductor device includes: (a) providing a semiconductor substrate that is made from a material containing an element of boron group; (b) forming on the semiconductor substrate a buffer structure that includes an aluminum nitride buffer film formed using a physical vapor deposition technique; and (c) forming on the buffer structure a semiconductor unit that includes a GaN-based epitaxial layer, the GaN-based epitaxial layer having a hexagonal crystal structure and being formed using a chemical vapor deposition technique.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 25, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chun-Yen Chang, Chen-Yu Li, Hao-Chung Kuo
  • Patent number: 10309009
    Abstract: Disclosed is a carbon thin-film device and method for manufacturing the same. The method includes forming a functional group on a surface of a substrate and functionalizing the substrate, and depositing a carbon thin film through ALD on the substrate in which the functional group is formed.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyungjun Kim, Taejin Choi, Jeong-Gyu Song
  • Patent number: 10302864
    Abstract: An example method of forming a deterministic thin film from a crystal substrate is described herein. The method can include implanting ions into a surface of the crystal substrate to form a thin film crystal layer, and bonding the crystal substrate and a handle substrate to form a bilayer bonding interface between the crystal substrate and the handle substrate. The method can also include exfoliating the thin film crystal layer from the crystal substrate, patterning the thin film crystal layer to define a deterministic thin film, etching one or more trenches in the thin film crystal layer, etching the bilayer bonding interface via the one or more trenches, and releasing the deterministic thin film from the handle substrate.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Ohio State Innovation Foundation
    Inventors: Ronald M. Reano, Li Chen
  • Patent number: 10297463
    Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Katsuyoshi Suzuki, Hiroshi Takeno, Koji Ebara
  • Patent number: 10262863
    Abstract: A method for manufacturing a SiC epitaxial wafer according to one aspect of the present invention includes separately introducing, into a reaction space for SiC epitaxial growth, a basic N-based gas composed of molecules containing an N atom within the molecular structure but having neither a double bond nor a triple bond between nitrogen atoms, and a Cl-based gas composed of molecules containing a Cl atom within the molecular structure, and mixing the N-based gas and the Cl-based gas at a temperature equal to or higher than the boiling point or sublimation temperature of a solid product generated by mixing the N-based gas and the Cl-based gas.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 16, 2019
    Assignees: SHOWA DENKO K.K., Central Research Institute Of Electric Power Industry
    Inventors: Keisuke Fukada, Masahiko Ito, Isaho Kamata, Hidekazu Tsuchida, Hideyuki Uehigashi, Hiroaki Fujibayashi, Masami Naito, Kazukuni Hara, Takahiro Kozawa, Hirofumi Aoki
  • Patent number: 10229831
    Abstract: A method of fabricating a nitride semiconductor substrate including forming a buffer layer on a surface of a growth substrate, growing a first nitride semiconductor layer on the buffer layer, growing a second nitride semiconductor layer on the first nitride semiconductor layer, and removing the growth substrate may be provided. The forming a buffer layer may deform the surface of the growth substrate to have a convex shape. The forming a buffer layer and the growing a first nitride semiconductor layer may be performed within a first process chamber. The growing a second nitride semiconductor layer and the removing the growth substrate may be performed within a second process chamber.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjo Tak, Sammook Kang, Mihyun Kim, Junyoun Kim
  • Patent number: 10105687
    Abstract: A photocatalyst in the form of chloroplast-like heterostructures of Bi2S3—ZnS is disclosed. Additionally, methods for producing the chloroplast-like heterostructures of Bi2S3—ZnS with controlled morphology, as well as methods for the photocatalytic production of hydrogen gas under visible light irradiation employing the chloroplast-like heterostructures of Bi2S3—ZnS are disclosed.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 23, 2018
    Assignee: Imam Abdulrahman Bin Faisal University
    Inventor: Muhammad Nawaz
  • Patent number: 10020203
    Abstract: An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1×1012?1×1013 atoms/cm3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 1×108?3×109 atoms/cm3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 8×1017 atoms/cm3 or more.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 10, 2018
    Assignee: SUMCO CORPORATION
    Inventors: Yasuo Koike, Tomokazu Katano, Toshiaki Ono
  • Patent number: 9966261
    Abstract: Described herein is a technique capable of improving the uniformity of device characteristics. A method of manufacturing a semiconductor device may include: (a) accommodating in a process chamber a substrate having an organic film thereon; (b) supplying a metal-containing gas to the substrate; (c) supplying a first oxygen-containing gas and a dilute gas to the substrate, the dilute gas containing at least one of a second oxygen-containing gas and an inert gas; (d) performing a cycle a predetermined number of time, the cycle including (b) and (c), wherein a flow rate of the first oxygen-containing gas is equal to or greater than a flow rate of the dilute gas in one of the cycle performed the predetermined number of time.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Katsuhiko Yamamoto, Naofumi Ohashi
  • Patent number: 9881712
    Abstract: Disclosed herein is a composition comprising a regioregular polyalkylthiophene and/or a regioregular poly[2,5-bis(3-alkylthiophen-2-yl)thieno(3,2-b)thiophene]; where the composition is melted and then cooled to a temperature between a melting point and a glass transition temperature of the composition; the composition having an amount of crystallinity that is at least twice the amount of crystallinity of another identical composition that is crystallized by a method that does not involve melting and cooling to a temperature between the melting point and the glass transition temperature of the identical composition.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 30, 2018
    Assignees: ROHM AND HAAS ELECTRONIC MATERIALS LLC, DOW GLOBAL TECHNOLOGIES LLC, THE PENN STATE RESEARCH FOUNDATION
    Inventors: Enrique Daniel Gomez, Kiarash Vakhshouri, III, Seung-Hyun Lee, Thomas Charles Sutter, George Lyles Athens, Krishna Balantrapu, Elissei Iagodkine
  • Patent number: 9856579
    Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapor phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 2, 2018
    Assignee: FREIBERGER COMPOUND MATERIALS GMBH
    Inventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
  • Patent number: 9852833
    Abstract: We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation. In an example embodiment, the magnetic electrodes have a substantially identical footprint that can be approximated by an ellipse, with the short axes of the ellipses being collinear and the edge-to-edge separation between the ellipses being smaller than the size of the short axis. In some embodiments, the magnetic electrodes may have relatively small tapers that extend toward each other from the ellipse edges in the constriction area between the electrodes. Some embodiments may also include an active element inserted into the gap between the tapers and electrical leads connected to the magnetic electrodes for passing electrical current through the active element. When subjected to an appropriate external magnetic field, the magnetic electrodes can advantageously be magnetized to controllably enter parallel and antiparallel magnetization states.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Gavin D. Scott
  • Patent number: 9816200
    Abstract: A silicon carbide powder which, when used as a raw material in a sublimation recrystallization method, enables improvement in productivity of a silicon carbide single crystal by exhibiting a high sublimation rate and allowing a small amount of silicon carbide to remain without being sublimated, and enables an increase in size of the silicon carbide single crystal (for example, a single crystal wafer). The silicon carbide powder has a Blaine specific surface area of from 250 cm2/g to 1,000 cm2/g and a ratio of a silicon carbide powder having a particle size of more than 0.70 mm and 3.00 mm or less of 50 vol % or more with respect to a total amount of the silicon carbide powder. When a silicon carbide powder accommodated in a crucible is heated to be sublimated, a silicon carbide single crystal is formed on a seed crystal provided on an undersurface of a lid.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 14, 2017
    Assignees: TAIHEIYO CEMENT CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kenta Masuda, Kouki Ichitsubo, Masakazu Suzuki, Kiyoshi Nonaka, Tomohisa Kato, Hideaki Tanaka
  • Patent number: 9809879
    Abstract: A laminate (1) provided with: a substrate (2); an undercoat layer (3), which is formed on at least a portion of the outer surface of the substrate (2), contains an organic polymer with a functional group, and is formed in a membrane form or film form; and an atomic layer deposition film (4), which contains a precursor (6) that serves as a starting material, is formed so as to cover the surface of the undercoat layer (3), and in which at least some of the precursor (6) are bonded to the functional groups. The linear expansion coefficient of a layered film provided with the substrate (2) and the undercoat layer (3) is from about 1.0×10?5/K to about 8.0×10?5/K.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 7, 2017
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Jin Sato, Mitsuru Kano
  • Patent number: 9793123
    Abstract: Provided are a nano structure, a fabrication method thereof, and an application device thereof. The method for fabricating a nano structure includes: forming a substrate; forming a plurality of linkers over the substrate; forming a plurality of metal ions over the linkers; and forming one or more metallic nanoparticles over the linkers.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 17, 2017
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim
  • Patent number: 9738526
    Abstract: Graphene-carbon nanotube multi-stack three-dimensional architectures (graphene-CNT stacks) are formed by a “popcorn-like” growth method, in which carbon nanotubes are grown throughout the architecture in a continuous step. Alternating layers of graphene and a transition metal are grown by a vapor deposition process. The metal is fragmented and etched to form an array of catalytic sites. Carbon nanotubes grow from the catalytic sites in a vapor-solid-liquid process. The graphene-CNT stacks have applications in electrical energy storage devices, such as supercapacitors and batteries. The directly grown carbon nanotube array between graphene layers provides ease of ion diffusion and electron transfer, in addition to being an active material, spacer and electron pathway.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 22, 2017
    Assignee: THE TRUSTEES OF THE STEVENS INSTITUTE OF TECHNOLOGY
    Inventors: Youn-su Kim, Kitu Kumar, Eui-Hyeok Yang, Frank Fisher
  • Patent number: 9735008
    Abstract: Methods of controlling island size and density on an OMVPE growth film may comprise adding a surfactant at a critical concentration level, allowing a growth phase for a first period of time, and ending the growth phase when desired island size and density are achieved. For example, the island size and density of an OMVPE grown InGaN thin film may be controlled by adding an antimony surfactant at a critical concentration level.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 15, 2017
    Assignee: University of Utah Research Foundation
    Inventors: Jason Merrell, Feng Liu, Gerald B. Stringfellow
  • Patent number: 9707660
    Abstract: Predictive modeling based focus error prediction method and system are disclosed. The method includes obtaining wafer geometry measurements of a plurality of training wafers and grouping the plurality of training wafers to provide at least one training group based on relative homogeneity of wafer geometry measurements among the plurality of training wafers. For each particular training group of the at least one training group, a predictive model is develop utilizing non-linear predictive modeling. The predictive model establishes correlations between wafer geometry parameters and focus error measurements obtained for each wafer within that particular training group, and the predictive model can be utilized to provide focus error prediction for an incoming wafer belonging to that particular training group.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: July 18, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Pradeep Vukkadala, Jaydeep Sinha, Wei Chang, Krishna Rao
  • Patent number: 9698698
    Abstract: A circuit arrangement for igniting thin rods composed of electrically conductive material at are thin silicon rods, wherein a three-phase AC system forming a three-phase system is used to feed electrical energy to the thin rods, wherein the three-phase AC system forms the three-phase system or a three-phase transformer having a secondary-side three-phase winding system forms the three-phase system, and wherein the three phases of the three-phase system or of the secondary-side three-phase winding system are interconnected or controlled such that voltages comprising voltage vectors of the three phases cancel one another out in a three-phase closed vector triangle system.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: July 4, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventor: Günter Heid
  • Patent number: 9698311
    Abstract: The present invention relates to colloidal quantum dots, to a process for producing such colloidal quantum dots, to the use thereof and to optoelectronic components comprising colloidal quantum dots.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: July 4, 2017
    Assignees: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSHUNG E.V., KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Tonino Greco, Christian Ippen, Armin Wedel
  • Patent number: 9631296
    Abstract: A method of manufacturing a silicon carbide substrate has the following steps. A silicon carbide source material is partially sublimated. After partially sublimating the silicon carbide source material, a seed substrate having a main surface is placed in a growth container. By sublimating the remainder of the silicon carbide source material in the growth container, a silicon carbide crystal grows on the main surface of the seed substrate. In this way, an increase of dislocations in the main surface of the seed substrate can be suppressed, thereby providing a method of manufacturing a silicon carbide substrate having few dislocations.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 25, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Taro Nishiguchi, Tsutomu Hori, Naoki Ooi, Shunsaku Ueta
  • Patent number: 9613802
    Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 4, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9583340
    Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Youn Kim, Jae-Kyun Kim, Joo-Sung Kim, Young-Soo Park, Young-Jo Tak
  • Patent number: 9558943
    Abstract: A method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and the resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of the Si wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9546437
    Abstract: An ingot in which generation of crack is sufficiently suppressed is obtained. The ingot includes: a seed substrate formed of silicon carbide; and a silicon carbide layer grown on the seed substrate and containing nitrogen atoms. The silicon carbide layer has a thickness of 15 mm or more in a growth direction. In the silicon carbide layer, a concentration gradient of the nitrogen atoms in the growth direction is 5×1017 atoms/cm4 or less.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 17, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tsutomu Hori, Makoto Sasaki, Tomohiro Kawase
  • Patent number: 9505624
    Abstract: A catalyst-free CVD method for forming graphene. The method involves placing a substrate within a reaction chamber, heating the substrate to a temperature between 600° C. and 1100° C., and introducing a carbon precursor into the chamber to form a graphene layer on a surface of the substrate. The method does not use plasma or a metal catalyst to form the graphene.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 29, 2016
    Assignee: Corning Incorporated
    Inventors: Xinyuan Liu, Robert George Manley, Robert Michael Morena, Zhen Song
  • Patent number: 9484191
    Abstract: A system and method for providing pulsed excited species from a remote plasma unit to a reaction chamber are disclosed. The system includes a pressure control device to control a pressure at the remote plasma unit as reactive species from the remote plasma unit are pulsed to the reaction chamber.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 1, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: Jereld Lee Winkler
  • Patent number: 9472468
    Abstract: A method includes growing a nanowire from a substrate, forming a sacrificial layer surrounding the nanowire, removing the nanowire from the sacrificial layer to form an opening in the sacrificial layer, and growing a replacement semiconductor nanowire in the opening.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mark van Dal, Aryan Afzalian, Gerben Doornbos
  • Patent number: 9449818
    Abstract: One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 20, 2016
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang Hyouk Choi
  • Patent number: 9379183
    Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 28, 2016
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 9362477
    Abstract: Provided is a method of forming a ceramic wire. In the method, a ceramic precursor film is deposited on a wire substrate. Then, the wire substrate on which the ceramic precursor film is deposited is treated by heating. For treating the wire substrate by heating, a temperature of the wire substrate and/or an oxygen partial pressure of the wire substrate are controlled such that the ceramic precursor film is in a liquid state and an epitaxy ceramic film is formed from the liquid ceramic precursor film on the wire substrate.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: June 7, 2016
    Assignee: SUNAM CO., LTD.
    Inventors: Seung-Hyun Moon, Hun-Ju Lee, Sang-Im Yoo, Hong-Soo Ha
  • Patent number: 9297093
    Abstract: A layered body having a single crystal layer including a group III nitride having a composition AlxGayInzN (wherein, X, Y and Z are rational numbers respectively satisfying 0.9?X?1.0, 0.0?Y?0.1, 0.0?Z?0.1, and X+Y+Z=1.0) on a sapphire substrate. The layered body includes an initial single crystal layer that includes the group III nitride composition, an oxygen concentration of 1×1020 cm?3 or more and 5×1021 cm?3 or less and a thickness of 15 nm or more and 40 nm or less on the sapphire substrate and a second group III nitride single crystal layer including the group III nitride composition and having a reduced oxygen concentration than the initial single crystal layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 29, 2016
    Assignee: Tokuyama Corporation
    Inventors: Toru Kinoshita, Kazuya Takada
  • Patent number: 9260653
    Abstract: Photoluminescent nanodiamond particles of dynamic synthesis have enhanced photoluminescent properties produced as a result of minimizing the nitrogen content of impurities or imperfections in the nanodiamond lattice and by location of photoluminescent structures on the outer surface of the nanodiamond particles. This inhibits suppression (i.e. inactivity) of emission and enhances the intensity of the emission. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 16, 2016
    Assignee: International Technology Center
    Inventors: Olga Shenderova, Igor Vlasov, Suzanne Ani Ciftan Hens, Vesna Borjanovic
  • Patent number: 9257524
    Abstract: Semiconductors of different types are formed by a crystal growth technique and joined at the interface at which rapid atomic-layer-level compositional changes occur while maintaining high crystallinity of the semiconductor layers so as to form a heterogeneous PN junction. A layered film that includes a PN junction oxide thin film is formed on a single crystal substrate. The PN junction oxide thin film is constituted by an N-type semiconductor oxide thin film and a P-type semiconductor oxide thin film that are epitaxially grown to have c-axis orientation represented by (00k).
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 9, 2016
    Assignee: TDK CORPORATION
    Inventors: Kazuya Maekawa, Kunihiro Ueda
  • Patent number: 9249505
    Abstract: A first compound having an atom in an oxidized state is reacted with a bis(trimethylsilyl) six-membered ring system or related compound to form a second compound having the atom in a reduced state relative to the first compound. The atom in an oxidized state is selected from the group consisting of Groups 2-12 of the Periodic Table, the lanthanides, As, Sb, Bi, Te, Si, Ge, Sn, and Al.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 2, 2016
    Assignee: Wayne State University
    Inventors: Charles H. Winter, Joseph Peter Klesko
  • Patent number: 9224817
    Abstract: The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of GaxAlyIn1-x-yN (0?x?1, 0?x+y?1) and the second layer composed of metal oxide wherein the second layer can be removed with in-situ etching at elevated temperature. The metal oxide layer is designed to act as a protective layer of the first layer until the fabrication of devices. The metal oxide layer is designed so that it can be removed in a fabrication reactor of the devices through gas-phase etching by reactive gas such as ammonia.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 29, 2015
    Assignees: SixPoint Materials, Inc., Seoul Semiconductor Co., Ltd.
    Inventor: Tadao Hashimoto
  • Patent number: 9190267
    Abstract: Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: November 17, 2015
    Assignee: SUMCO Corporation
    Inventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
  • Patent number: 9157149
    Abstract: A first compound having an atom in an oxidized state is reacted with a bis(trimethylsilyl) six-membered ring system or related compound to form a second compound having the atom in a reduced state relative to the first compound. The atom in an oxidized state is selected from the group consisting of Groups 2 to 12 of the Periodic Table, As, Sb, Bi, Se, and Te.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 13, 2015
    Assignee: Wayne State University
    Inventors: Charles H. Winter, Joseph Peter Klesko
  • Patent number: 9145622
    Abstract: In a manufacturing method of a silicon carbide single crystal, a seed crystal made of silicon carbide is prepared. The seed crystal has a growth surface and a stacking fault generation region and includes a threading dislocation that reaches the growth surface. The growth surface is inclined at a predetermined angle from a (0001) plane. The stacking fault generation region is configured to cause a stacking fault in the silicon carbide single crystal when the silicon carbide single crystal is grown. The stacking fault generation region is located at an end portion of the growth surface in an offset direction that is a direction of a vector defined by projecting a normal vector of the (0001) plane onto the growth surface. The seed crystal is joined to a pedestal, and the silicon carbide single crystal is grown on the growth surface of the seed crystal.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: September 29, 2015
    Assignee: DENSO CORPORATION
    Inventors: Yasushi Urakami, Ayumu Adachi, Itaru Gunjishima
  • Patent number: 9112066
    Abstract: Method of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 18, 2015
    Assignee: SunPower Corporation
    Inventors: Tim Dennis, Scott Harrington, Jane Manning, David D. Smith, Ann Waldhauer
  • Patent number: 9099308
    Abstract: An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 4, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Giuseppe Abbondanza
  • Patent number: 9090989
    Abstract: In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 28, 2015
    Assignee: II-VI Incorporated
    Inventors: Ilya Zwieback, Ping Wu, Varatharajan Rengarajan, Avinash K. Gupta, Thomas E. Anderson, Gary E. Ruland, Andrew E. Souzis, Xueping Xu
  • Patent number: 9087542
    Abstract: A method for fabricating a structure in a magnetic recording transducer is described. A trench having sidewalls converging in a corner and a depth is formed. A dielectric layer is deposited using physical vapor deposit (PVD). The dielectric layer thickness is not more than one-half of the trench depth. A remaining portion of the trench is unfilled by the dielectric layer and has a top and a bottom. A portion of the dielectric layer is plasma etched. The plasma etch removes the portion of the dielectric layer at the top of the trench at a first rate and removes the portion of the dielectric layer at the bottom of the remaining portion of the trench at a second rate less than the first rate. An additional dielectric layer is deposited, also using PVD. The plasma etch and additional dielectric layer depositing steps are optionally repeated until the trench is filled.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 21, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yufeng Hu, Ut Tran, Shawn M. Tanner, Jerome S. Marcelino, Jikou Zhou
  • Patent number: 9064709
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Gerhard Schrom, Valluri R. Rao, Robert S. Chau
  • Patent number: 9054233
    Abstract: A device includes a support including at least a first area and a second area, and a plurality of first light emitting devices located over the first area of the support, each first light emitting device containing a first growth template including a first nanostructure, and each first light emitting device has a first peak emission wavelength. The device also includes a plurality of second light emitting devices located over the second area of the support, each second light emitting device containing a second growth template including a second nanostructure, and each second light emitting device has a second peak emission wavelength different from the first peak emission wavelength. Each first growth template differs from each second growth template.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: June 9, 2015
    Assignee: GLO AB
    Inventors: Jonas Ohlsson, Carl Patrik Theodor Svensson
  • Patent number: 9039834
    Abstract: Non-polar (11 20) a-plane gallium nitride (GaN) films with planar surfaces are grown on (1 102) r-plane sapphire substrates by employing a low temperature nucleation layer as a buffer layer prior to a high temperature growth of the non-polar (11 20) a-plane GaN thin films.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, James Stephen Speck
  • Patent number: 9034104
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A single-component oxide semiconductor layer is formed over a substrate; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a single-component oxide semiconductor layer including single crystal regions is formed; and a multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 9034103
    Abstract: In various embodiments, methods of forming single-crystal AlN include providing a substantially undoped polycrystalline AlN ceramic having an oxygen concentration less than approximately 100 ppm, forming a single-crystal bulk AlN crystal by a sublimation-recondensation process at a temperature greater than approximately 2000° C., and cooling the bulk AlN crystal to a first temperature between approximately 1500° C. and approximately 1800° C. at a first rate less than approximately 250° C./hour.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 19, 2015
    Assignee: CRYSTAL IS, INC.
    Inventors: Sandra B. Schujman, Shailaja P. Rao, Robert T. Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 9028612
    Abstract: In various embodiments, non-zero thermal gradients are formed within a growth chamber both substantially parallel and substantially perpendicular to the growth direction during formation of semiconductor crystals, where the ratio of the two thermal gradients (parallel to perpendicular) is less than 10, by, e.g., arrangement of thermal shields outside of the growth chamber.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 12, 2015
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Shailaja P. Rao, Shawn Robert Gibb, Leo J. Schowalter
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov