Forming From Vapor Or Gaseous State (e.g., Vpe, Sublimation) Patents (Class 117/84)
  • Patent number: 11279620
    Abstract: The present invention relates to a carbon material coated with tantalum carbide and, more specifically, to a carbon material coated with tantalum carbide, comprising: a carbon substrate; and a tantalum carbide coated surface formed on the carbon substrate, wherein the carbon material coated with tantalum carbide has, as main peaks, X-ray diffraction peaks of the (111) plane, the (200) plane, the (220) plane and the (311) plane, of the tantalum carbide coated surface, and the peak of the (111) plane among the peaks has the maximum diffraction intensity. The present invention can provide the carbon material coated with tantalum carbide, having excellent chemical and physical resistance and extended lifespan.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 22, 2022
    Assignee: Tokai Carbon Korea Co., LTD
    Inventor: Dong Won Jo
  • Patent number: 11277114
    Abstract: An elastic wave device includes an interdigital transducer electrode and a wiring electrode made of metal and provided on a first main surface of a piezoelectric substrate. Via hole electrodes penetrate the piezoelectric substrate. Each via hole electrode is connected to an external connection terminal. A cover member defines a hollow space in which the interdigital transducer electrode is sealed, together with the first main surface of the piezoelectric substrate. A heat dissipating member is provided on the wiring electrode to extend from the wiring electrode toward the cover member and penetrate the cover member.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 15, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Taku Kikuchi, Daisuke Sekiya
  • Patent number: 11261541
    Abstract: A shielding member placed between a SiC source loading portion and a crystal installation portion in an apparatus for single crystal growth, including a crystal growth container including the loading portion which accommodates a SiC source in an inner bottom portion; a crystal installation portion facing the loading portion, and a heating unit configured to heat the crystal growth container. The device grows a single crystal of the SiC source on a crystal installed on the crystal installation portion by sublimating the SiC source from the loading portion. The shielding member includes a plurality of shielding plates, wherein each area of the plurality of shielding plates is 40% or less of a base area of the crystal growth container. When the SiC source loading portion is filled with a SiC source, a shielding ratio provided by a projection surface of the plurality of shielding plates is 0.5 or more.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 1, 2022
    Assignee: SHOWA DENKO K.K.
    Inventor: Yohei Fujikawa
  • Patent number: 11236426
    Abstract: Methods of forming plasmonic diamond films are provided. In an embodiment, such a method comprises forming a first layer of diamond on a substrate; depositing a layer of a metal on a surface of the first layer of diamond to form an as-deposited layer of metal; exposing the as-deposited layer of metal to a plasma treatment to convert the as-deposited layer of metal to a plurality of discrete regions of the metal on the surface of the first layer of diamond; and forming a second layer of diamond on the plurality of discrete regions of metal to form the plasmonic diamond film comprising a plurality of plasmonic nanoparticles.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 1, 2022
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert John Hamers, Shuo Li
  • Patent number: 11236417
    Abstract: A method for producing a waveguide including a germanium-based core and a cladding is provided, the method including a step of “low temperature” depositing of a shell after forming the core by engraving, such that the deposition temperature is less than 780° C., followed by a step of “high temperature” depositing of a thick encapsulation layer. The shell and the encapsulation layer at least partially form the cladding of the waveguide. Optionally, a step of annealing under hydrogen at a “low temperature”, less than 750° C., precedes the deposition of the shell. These “low temperature” annealing and depositing steps advantageously make it possible to avoid a post-engraving alteration of the free surfaces of the core during the forming of the cladding which is less germanium-rich.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 1, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Michel Hartmann, Mickael Brun, Jean-Marc Fedeli, Maryse Fournier
  • Patent number: 11177123
    Abstract: A compound semiconductor laminate substrate comprising two single-crystalline compound semiconductor substrates directly bonded together and laminated, the single-crystalline compound semiconductor substrates having the same composition including A and B as constituent elements and having the same atomic arrangement, characterized in that the front and back surfaces of the laminate substrate are polar faces comprising the same kind of atoms of A or B, and that a laminate interface comprises a bond of atoms of either B or A and is a unipolar anti-phase region boundary plane in which the crystal lattices of the atoms are matched. In this way, the polar faces of the front and rear surfaces of the compound semiconductor laminate substrate are made monopolar, thereby facilitating semiconductor element process designing, and making it possible to manufacture a low-cost, high-performance, and stable semiconductor element without implementing complex substrate processing.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: November 16, 2021
    Assignees: SHIN-ETSU CHEMICAL CO., LTD., CUSIC INC.
    Inventors: Hiroyuki Nagasawa, Yoshihiro Kubota, Shoji Akiyama
  • Patent number: 11171211
    Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A <001> direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Hyun Park, Zhengping Jiang, Hesameddin Ilatikhameneh, Woosung Choi, Chihak Ahn
  • Patent number: 11164986
    Abstract: An n-type semiconductor layer (102), a multiplication layer (103), an electric field control layer (104), a light absorption layer (105), and a p-type semiconductor layer (106) are formed on a growth substrate (101), and the p-type semiconductor layer (106) is adhered on a transfer substrate (107). After that, the growth substrate (101) is removed, and the n-type semiconductor layer (102) is processed to have an area smaller than that of the multiplication layer (103).
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 2, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Masahiro Nada, Hideaki Matsuzaki
  • Patent number: 11155931
    Abstract: A method of manufacturing a group-III nitride crystal includes: preparing a seed substrate; and supplying a group-III element oxide gas and a nitrogen element-containing gas at a supersaturation ratio (Po/Pe) greater than 1 and equal to or less than 5, then, growing a group-III nitride crystal on the seed substrate, wherein the Po is a supply partial pressure of the group-III element oxide gas, and the Pe is an equilibrium partial pressure of the group-III element oxide gas.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 26, 2021
    Assignees: OSAKA UNIVERSITY, PANASONIC CORPORATION
    Inventors: Yusuke Mori, Masashi Yoshimura, Masayuki Imanishi, Akira Kitamoto, Junichi Takino, Tomoaki Sumi
  • Patent number: 11142821
    Abstract: A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a <110> direction, and an angle formed by the first crystal face and the second crystal face is more than 70.6°. Further, it is preferred that the angle formed by the first crystal face and the second crystal face is 100° or more and 176° or less.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 12, 2021
    Inventors: Yukimune Watanabe, Noriyasu Kawana
  • Patent number: 11111599
    Abstract: The present invention provides a single crystal growth method capable of suppressing the recrystallization of the raw material gas subjected to sublimation on the surface of the raw material, and suppressing the generation of different polytypes in the crystal growing single crystal. The single crystal growth method is carried out in a crucible comprising an inner bottom for providing a raw material and a crystal mounting part facing the inner bottom. The method comprises in the following order: providing the raw material in the inner bottom; covering at least a part of a surface of the raw material with a metal carbide powder in a plan view from the crystal mounting part; and growing a single crystal disposed in the crystal mounting part by sublimating the raw material by heating.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 7, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Yohei Fujikawa
  • Patent number: 11112354
    Abstract: A method for measuring carbon concentration in silicon single crystal according to the present invention includes a step of measuring a carbon concentration of a sample of silicon single crystal using FT-IR, a step of measuring a temperature of the sample during, prior to, or after the measurement of the carbon concentration of the sample, and steps of correcting a measured value Ycs of the carbon concentration of the sample based on the measuring temperature of the sample when the measured Ycs value of the carbon concentration of the sample is at or below 0.5×1016 atoms/cm3.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 7, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Shogo Kobayashi
  • Patent number: 11104102
    Abstract: A heat-resistant member includes a base member composed of an isotropic graphite and a film with a single layer or multiple layers formed on the entire or partial surface of the base member. The film includes a dense WC layer with a single layer or multiple layers, and the dense WC layer includes WC as a main component and has a porosity of less than 3%. The film may further include a porous WC layer with a single layer or multiple layers formed on an entire or partial surface of the dense WC layer. In this case, the porous WC layer preferably includes WC as a main component and has a porosity larger than that of the dense WC layer.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 31, 2021
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventor: Daisuke Nakamura
  • Patent number: 11107892
    Abstract: A method for producing a SiC epitaxial wafer according to the present embodiment includes: an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by feeding an Si-based raw material gas, a C-based raw material gas, and a gas including a Cl element to a surface of a SiC single crystal substrate, in which the epitaxial growth step is performed under growth conditions that a film deposition pressure is 30 torr or less, a Cl/Si ratio is in a range of 8 to 12, a C/Si ratio is in a range of 0.8 to 1.2, and a growth rate is 50 ?m/h or more from an initial growth stage.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 31, 2021
    Assignees: SHOWA DENKO K.K., Central Research Institute Of Electric Power Industry, DENSO CORPORATION
    Inventors: Keisuke Fukada, Naoto Ishibashi, Akira Bando, Masahiko Ito, Isaho Kamata, Hidekazu Tsuchida, Kazukuni Hara, Masami Naito, Hideyuki Uehigashi, Hiroaki Fujibayashi, Hirofumi Aoki, Toshikazu Sugiura, Katsumi Suzuki
  • Patent number: 11066757
    Abstract: A method for manufacturing a diamond substrate, including: a first step of preparing patterned diamond on a foundation surface, a second step of growing diamond from the patterned diamond prepared in the first step to form the diamond in a pattern gap of the patterned diamond prepared in the first step, a third step of removing the patterned diamond prepared in the first step to form a patterned diamond composed of the diamond formed in the second step, and a fourth step of growing diamond from the patterned diamond formed in the third step to form the diamond in a pattern gap of the patterned diamond formed in the third step. There can be provided a method for manufacturing a diamond substrate which can sufficiently suppress dislocation defects, a high-quality diamond substrate, and a freestanding diamond substrate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 20, 2021
    Assignees: Shin-Etsu Chemical Co., Ltd., National Institute of Advanced Industrial Science and Technology, National University Corporation Kanazawa University
    Inventors: Hitoshi Noguchi, Shozo Shirai, Toshiharu Makino, Masahiko Ogura, Hiromitsu Kato, Hiroyuki Kawashima, Daisuke Kuwabara, Satoshi Yamasaki, Daisuke Takeuchi, Norio Tokuda, Takao Inokuma, Tsubasa Matsumoto
  • Patent number: 11041255
    Abstract: A silicon carbide crystal and a manufacturing method thereof are provided. The silicon carbide crystal includes an N-type seed layer, a barrier layer, and a semi-insulating ingot, which are sequentially stacked and are made of silicon carbide. The N-type seed layer has a resistivity within a range of 0.01-0.03 ?·cm. The barrier layer includes a plurality of epitaxial layers sequentially formed on the N-type seed layer by an epitaxial process. The C/Si ratios of the epitaxial layers gradually increase in a growth direction away from the N-type seed layer. A nitrogen concentration of the silicon carbide crystal gradually decreases from the N-type seed layer toward the semi-insulating ingot by a diffusion phenomenon, so that the semi-insulating crystal has a resistivity larger than 107 ?·cm.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 22, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, I-Ching Li
  • Patent number: 11041257
    Abstract: A shielding member includes a plurality of shielding plates, in which the plurality of shielding plates are arranged without gaps therebetween in a plan view from a crystal installation part, and the shielding member is disposed between a source material accommodation part and the crystal installation part, in an apparatus for growing single crystals, wherein the apparatus includes a container for crystal growth that has the source material accommodation part at an inner bottom part, and has the crystal installation part that faces the source material accommodation part, and includes a heating part that is configured to heat the container for crystal growth, in which a single crystal of the source material is grown on a crystal installed in the crystal installation part by subliming the source material from the source material accommodation part.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 22, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshiteru Hosaka, Yohei Fujikawa
  • Patent number: 11004681
    Abstract: In example implementations of a heterogeneous substrate, the heterogeneous substrate includes a first material having an air trench, a second material coupled to the first material, a dielectric mask on a first portion of the second material and an active region that is grown on a remaining portion of the second material. An air gap may be formed in the air trench by the second material coupled to the first material. Defects in the second material may be contained to an area below the dielectric mask and the active region may remain defect free.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 11, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Di Liang
  • Patent number: 10995418
    Abstract: A shielding member, wherein the shielding member is formed of at least one of structure which has a non-flat plate shape having an inclined surface, and the inclined surface is located on a side of a substrate support part when the shielding member is disposed in a single crystal growth device, wherein the single crystal growth device comprising: a crystal growth container; a source storage part that is positioned at a lower inner part of the crystal growth container; the substrate support part, wherein the support part is disposed above the source storage part and supports a substrate to make the substrate face the source storage part; and a heating device that is disposed on an outer circumference of the crystal growth container, wherein the shielding member is disposed between the source storage part and the substrate support part, and wherein a single crystal of a source is grown on the substrate by sublimating the source from the source storage part.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 4, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Yohei Fujikawa
  • Patent number: 10991614
    Abstract: A susceptor for holding a semiconductor wafer with an orientation notch during deposition of a layer on the wafer comprises a susceptor ring having a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area. The susceptor has four positions at which the structure differs from the structure at four further positions, the spacing from one of the four positions to the next of the four positions being 90°, the spacing from one of the four positions to the next further position being 45°, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other positions of the four positions of the susceptor.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: April 27, 2021
    Assignee: Siltronic AG
    Inventor: Reinhard Schauer
  • Patent number: 10964879
    Abstract: A method of manufacturing a dielectric device includes epitaxially growing a metal film on a substrate, forming a dielectric film on the metal film such that the dielectric film has a preferentially oriented structure, forming a first electrode film having a non-oriented or amorphous structure on the dielectric film, removing the substrate and the metal film from the dielectric film or removing the substrate from the metal film, and forming a second electrode film having a non-oriented or amorphous structure on the dielectric film or the metal film.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 30, 2021
    Assignee: TDK CORPORATION
    Inventors: Katsuyuki Kurachi, Hitoshi Sakuma, Yasuhiro Aida, Kazuhiko Maejima, Mayumi Nakajima
  • Patent number: 10889886
    Abstract: A crucible. The crucible includes a crucible body having an opening formed at the top thereof. The crucible further includes a sealing cover and an elastic element. The sealing cover is configured to seal the crucible in a first position and open the crucible in a second position. In the first position, the sealing cover forms a detachable sealed connection with the crucible body. The elastic element is arranged between the sealing cover and the crucible body, where the elastic element is in a compressed state when the crucible is sealed by the sealing cover in the first position. Correspondingly, the present disclosure also provides an evaporation preparation device, evaporation equipment and an evaporation method. The present disclosure can reduce the deterioration of the material to be evaporated and the direct contact between human body and the material.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 12, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yongqi Shen
  • Patent number: 10867791
    Abstract: A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 m?·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5? to 0°25? with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Naoya Nonaka, Tadashi Kawashima, Kenichi Mizogami
  • Patent number: 10844512
    Abstract: Provided is a method for manufacturing a synthetic gemstone, which manufactures a synthetic gemstone from a body tissue separated from a person or an animal, the method including: extracting a biological material from the body tissue; preparing a mixed material by mixing the biological material with a gemstone material; and growing a synthetic gemstone on a crystal seed as a single crystal by melting the mixed material.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 24, 2020
    Inventors: Chul-Hong Choi, Dong-Wook Shin, In-Sang Yoon, Jung-Min Kim
  • Patent number: 10822718
    Abstract: A method for producing an AlN single crystal substrate, the method including: i) preparing a first base substrate consisting of a first AlN single crystal; ii) growing a first AlN single crystal layer over a main face of the first base substrate, to obtain a layered body; iii) cutting the first MN single crystal layer of the layered body, to separate the layered body into a second base substrate and a first part of the first AlN single crystal layer, the second base substrate including the first base substrate and a thin film layered thereon, the thin film being a second part of the first AlN single crystal layer; iv) polishing a surface of the thin film, to obtain a third base substrate consisting of a second AlN single crystal; and v) growing a second AlN single crystal layer over the polished surface of the third base substrate.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 3, 2020
    Assignee: TOKUYAMA CORPORATION
    Inventors: Toru Nagashima, Reiko Okayama, Masayuki Fukuda, Hiroyuki Yanagi
  • Patent number: 10734384
    Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Gengming Tao
  • Patent number: 10714788
    Abstract: Solid-state lithium ion electrolytes of lithium silicate based composites are provided which contain an anionic framework capable of conducting lithium ions. An activation energy for lithium ion migration in the solid state lithium ion electrolytes is 0.5 eV or less and room temperature conductivities are greater than 10?5 S/cm. Composites of specific formulae are provided and methods to alter the composite materials with inclusion of aliovalent ions shown. Lithium batteries containing the composite lithium ion electrolytes are also provided.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: July 14, 2020
    Assignees: UNIVERSITY OF MARYLAND, COLLEGE PARK, TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Yifei Mo, Xingfeng He, Chen Ling, Ying Zhang
  • Patent number: 10714345
    Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 14, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Yunsang Kim, Hyuk-Jun Kwon
  • Patent number: 10662058
    Abstract: A method of manufacturing a patterned aluminum nitride layer includes growing an amorphous patterned layer on a seed layer, which promotes growth of a first type aluminum nitride layer that has a disordered crystallographic structure. The seed layer promotes growth of a second type aluminum nitride layer with a vertically oriented columnar crystal structure. The method also includes depositing an aluminum nitride layer over the amorphous patterned layer and the seed layer to form the first type aluminum nitride layer with the disordered crystallographic structure over the amorphous patterned layer and the second type aluminum nitride layer with the vertically oriented columnar crystal structure over the seed layer. The method also includes depositing a masking layer over the second type aluminum nitride layer and etching away the first type aluminum nitride layer.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 26, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventor: Dosi Dosev
  • Patent number: 10619267
    Abstract: The crystal plane in the interior of the diamond substrate has a curvature higher than 0 km?1 and equal to or lower than 1500 km1 by preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 14, 2020
    Assignee: ADAMANT NAMIKI PRECISION JEWEL CO., LTD.
    Inventors: Hideo Aida, Koji Koyama, Kenjiro Ikejiri, Seongwoo Kim
  • Patent number: 10566655
    Abstract: There are provided a solid electrolyte material having high density and ion conductivity, and an all solid lithium ion secondary battery using the solid electrolyte material. The solid electrolyte material has a garnet-related structure which has a chemical composition represented by Li7-x-yLa3Zr2-x-yTaxNbyO12 (0?x?0.8, 0.2?y?1, and 0.2?x+y?1) and relative density of 99% or greater, and belongs to a cubic system. The solid electrolyte material has lithium ion conductivity which is equal to or greater than 1.0×10?3 S/cm. The solid electrolyte material has a lattice constant a which satisfies 1.28 nm?a?1.30 nm, and has a lithium ion which occupies only two or more 96h sites in a crystal structure. The all solid lithium ion secondary battery includes a positive electrode, a negative electrode, and a solid electrolyte. The solid electrolyte includes the solid electrolyte material.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: February 18, 2020
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kunimitsu Kataoka, Chika Takamori, Haruo Ishizaki, Junji Akimoto
  • Patent number: 10497562
    Abstract: Disclosed a method of fabricating a gallium nitride substrate using hydride vapor phase epitaxy (HVPE), including a step of injecting ammonia (NH3) gas to perform first surface treatment on a sapphire substrate; a step of injecting ammonia gas and hydrogen chloride (HCl) gas to form a buffer layer on the sapphire substrate; a step of injecting ammonia gas to perform second surface treatment on the sapphire substrate; and a step of allowing gallium nitride (GaN) to grow on the sapphire substrate while lowering the flow rate ratio of ammonia gas to hydrogen chloride gas stepwise.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 3, 2019
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Jae Hyoung Shim, Tae Hun Shim
  • Patent number: 10464273
    Abstract: Embodiments disclosed herein relate to cell assemblies for fabricating superhard materials (e.g., used in a high-pressure cubic press) and methods of using the same. The disclosed cell assemblies include a plurality of internal anvils, at least some of which are positioned internally relative to a cell pressure medium of the cell assembly. Such a configuration for the cell assemblies may enable one or more of intensifying cell pressure, reducing processing time, or reducing costs for fabricating such superhard materials.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 5, 2019
    Assignee: US SYNTHETIC CORPORATION
    Inventors: Kenneth E. Bertagnolli, Michael A. Vail, Jiang Qian, Jason K. Wiggins, Mark P. Chapman, Arnold D. Cooper, Debkumar Mukhopadhyay, Amy Leigh Rodriguez, Stephen Rudger Adams
  • Patent number: 10458043
    Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: October 29, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto Kiyama, Ryu Hirota, Seiji Nakahata
  • Patent number: 10361077
    Abstract: The invention relates to a method for producing a semiconductor structure, characterized in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, ??) and (0, ??) between the central line (0, 0) and the integer order line (0, ?1), and two fractional order diffraction lines (0, ?) and (0, ?) between the central line (0, 0) and the integer order line (0, 1).
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 23, 2019
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: Fabrice Semond, Eric Frayssinet, Jean Massies
  • Patent number: 10332974
    Abstract: A method of making a semiconductor device includes: (a) providing a semiconductor substrate that is made from a material containing an element of boron group; (b) forming on the semiconductor substrate a buffer structure that includes an aluminum nitride buffer film formed using a physical vapor deposition technique; and (c) forming on the buffer structure a semiconductor unit that includes a GaN-based epitaxial layer, the GaN-based epitaxial layer having a hexagonal crystal structure and being formed using a chemical vapor deposition technique.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 25, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chun-Yen Chang, Chen-Yu Li, Hao-Chung Kuo
  • Patent number: 10309009
    Abstract: Disclosed is a carbon thin-film device and method for manufacturing the same. The method includes forming a functional group on a surface of a substrate and functionalizing the substrate, and depositing a carbon thin film through ALD on the substrate in which the functional group is formed.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyungjun Kim, Taejin Choi, Jeong-Gyu Song
  • Patent number: 10302864
    Abstract: An example method of forming a deterministic thin film from a crystal substrate is described herein. The method can include implanting ions into a surface of the crystal substrate to form a thin film crystal layer, and bonding the crystal substrate and a handle substrate to form a bilayer bonding interface between the crystal substrate and the handle substrate. The method can also include exfoliating the thin film crystal layer from the crystal substrate, patterning the thin film crystal layer to define a deterministic thin film, etching one or more trenches in the thin film crystal layer, etching the bilayer bonding interface via the one or more trenches, and releasing the deterministic thin film from the handle substrate.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Ohio State Innovation Foundation
    Inventors: Ronald M. Reano, Li Chen
  • Patent number: 10297463
    Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Katsuyoshi Suzuki, Hiroshi Takeno, Koji Ebara
  • Patent number: 10262863
    Abstract: A method for manufacturing a SiC epitaxial wafer according to one aspect of the present invention includes separately introducing, into a reaction space for SiC epitaxial growth, a basic N-based gas composed of molecules containing an N atom within the molecular structure but having neither a double bond nor a triple bond between nitrogen atoms, and a Cl-based gas composed of molecules containing a Cl atom within the molecular structure, and mixing the N-based gas and the Cl-based gas at a temperature equal to or higher than the boiling point or sublimation temperature of a solid product generated by mixing the N-based gas and the Cl-based gas.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 16, 2019
    Assignees: SHOWA DENKO K.K., Central Research Institute Of Electric Power Industry
    Inventors: Keisuke Fukada, Masahiko Ito, Isaho Kamata, Hidekazu Tsuchida, Hideyuki Uehigashi, Hiroaki Fujibayashi, Masami Naito, Kazukuni Hara, Takahiro Kozawa, Hirofumi Aoki
  • Patent number: 10229831
    Abstract: A method of fabricating a nitride semiconductor substrate including forming a buffer layer on a surface of a growth substrate, growing a first nitride semiconductor layer on the buffer layer, growing a second nitride semiconductor layer on the first nitride semiconductor layer, and removing the growth substrate may be provided. The forming a buffer layer may deform the surface of the growth substrate to have a convex shape. The forming a buffer layer and the growing a first nitride semiconductor layer may be performed within a first process chamber. The growing a second nitride semiconductor layer and the removing the growth substrate may be performed within a second process chamber.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjo Tak, Sammook Kang, Mihyun Kim, Junyoun Kim
  • Patent number: 10105687
    Abstract: A photocatalyst in the form of chloroplast-like heterostructures of Bi2S3—ZnS is disclosed. Additionally, methods for producing the chloroplast-like heterostructures of Bi2S3—ZnS with controlled morphology, as well as methods for the photocatalytic production of hydrogen gas under visible light irradiation employing the chloroplast-like heterostructures of Bi2S3—ZnS are disclosed.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 23, 2018
    Assignee: Imam Abdulrahman Bin Faisal University
    Inventor: Muhammad Nawaz
  • Patent number: 10020203
    Abstract: An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1×1012?1×1013 atoms/cm3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 1×108?3×109 atoms/cm3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 8×1017 atoms/cm3 or more.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 10, 2018
    Assignee: SUMCO CORPORATION
    Inventors: Yasuo Koike, Tomokazu Katano, Toshiaki Ono
  • Patent number: 9966261
    Abstract: Described herein is a technique capable of improving the uniformity of device characteristics. A method of manufacturing a semiconductor device may include: (a) accommodating in a process chamber a substrate having an organic film thereon; (b) supplying a metal-containing gas to the substrate; (c) supplying a first oxygen-containing gas and a dilute gas to the substrate, the dilute gas containing at least one of a second oxygen-containing gas and an inert gas; (d) performing a cycle a predetermined number of time, the cycle including (b) and (c), wherein a flow rate of the first oxygen-containing gas is equal to or greater than a flow rate of the dilute gas in one of the cycle performed the predetermined number of time.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Katsuhiko Yamamoto, Naofumi Ohashi
  • Patent number: 9881712
    Abstract: Disclosed herein is a composition comprising a regioregular polyalkylthiophene and/or a regioregular poly[2,5-bis(3-alkylthiophen-2-yl)thieno(3,2-b)thiophene]; where the composition is melted and then cooled to a temperature between a melting point and a glass transition temperature of the composition; the composition having an amount of crystallinity that is at least twice the amount of crystallinity of another identical composition that is crystallized by a method that does not involve melting and cooling to a temperature between the melting point and the glass transition temperature of the identical composition.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 30, 2018
    Assignees: ROHM AND HAAS ELECTRONIC MATERIALS LLC, DOW GLOBAL TECHNOLOGIES LLC, THE PENN STATE RESEARCH FOUNDATION
    Inventors: Enrique Daniel Gomez, Kiarash Vakhshouri, III, Seung-Hyun Lee, Thomas Charles Sutter, George Lyles Athens, Krishna Balantrapu, Elissei Iagodkine
  • Patent number: 9856579
    Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapor phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 2, 2018
    Assignee: FREIBERGER COMPOUND MATERIALS GMBH
    Inventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
  • Patent number: 9852833
    Abstract: We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation. In an example embodiment, the magnetic electrodes have a substantially identical footprint that can be approximated by an ellipse, with the short axes of the ellipses being collinear and the edge-to-edge separation between the ellipses being smaller than the size of the short axis. In some embodiments, the magnetic electrodes may have relatively small tapers that extend toward each other from the ellipse edges in the constriction area between the electrodes. Some embodiments may also include an active element inserted into the gap between the tapers and electrical leads connected to the magnetic electrodes for passing electrical current through the active element. When subjected to an appropriate external magnetic field, the magnetic electrodes can advantageously be magnetized to controllably enter parallel and antiparallel magnetization states.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Gavin D. Scott
  • Patent number: 9816200
    Abstract: A silicon carbide powder which, when used as a raw material in a sublimation recrystallization method, enables improvement in productivity of a silicon carbide single crystal by exhibiting a high sublimation rate and allowing a small amount of silicon carbide to remain without being sublimated, and enables an increase in size of the silicon carbide single crystal (for example, a single crystal wafer). The silicon carbide powder has a Blaine specific surface area of from 250 cm2/g to 1,000 cm2/g and a ratio of a silicon carbide powder having a particle size of more than 0.70 mm and 3.00 mm or less of 50 vol % or more with respect to a total amount of the silicon carbide powder. When a silicon carbide powder accommodated in a crucible is heated to be sublimated, a silicon carbide single crystal is formed on a seed crystal provided on an undersurface of a lid.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 14, 2017
    Assignees: TAIHEIYO CEMENT CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kenta Masuda, Kouki Ichitsubo, Masakazu Suzuki, Kiyoshi Nonaka, Tomohisa Kato, Hideaki Tanaka
  • Patent number: 9809879
    Abstract: A laminate (1) provided with: a substrate (2); an undercoat layer (3), which is formed on at least a portion of the outer surface of the substrate (2), contains an organic polymer with a functional group, and is formed in a membrane form or film form; and an atomic layer deposition film (4), which contains a precursor (6) that serves as a starting material, is formed so as to cover the surface of the undercoat layer (3), and in which at least some of the precursor (6) are bonded to the functional groups. The linear expansion coefficient of a layered film provided with the substrate (2) and the undercoat layer (3) is from about 1.0×10?5/K to about 8.0×10?5/K.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 7, 2017
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Jin Sato, Mitsuru Kano
  • Patent number: 9793123
    Abstract: Provided are a nano structure, a fabrication method thereof, and an application device thereof. The method for fabricating a nano structure includes: forming a substrate; forming a plurality of linkers over the substrate; forming a plurality of metal ions over the linkers; and forming one or more metallic nanoparticles over the linkers.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 17, 2017
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim