Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
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Patent number: 7169227Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm?2.Type: GrantFiled: March 25, 2003Date of Patent: January 30, 2007Assignee: Crystal Photonics, IncorporatedInventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou, David W. Hill
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Patent number: 7153363Abstract: Substrates are charged with a material by introducing the substrates into an evacuated vacuum container and exposing the surface of the substrates to a reactive gas which is adsorbed on the surface. The exposure is then terminated and the reactive gas adsorbed on the surface is allowed to react. The surface with the adsorbed reactive gas is exposed to a low-energy plasma discharge with ion energy E10 on the surface of the substrate of 0<E10?20 eV and an electron energy Eeo of 0 eV<Eeo?100 eV. The adsorbed reactive gas is allowed to react at least with the cooperation of plasma-generated ions and electrons and wherein the density of the resulting material charging on the substrate surface is controlled to have a predetermined density ranging from isolated atoms, to forming a continuous monolayer.Type: GrantFiled: May 21, 2004Date of Patent: December 26, 2006Assignee: OC Oerlikon Balzers AGInventor: Jurgen Ramm
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Patent number: 7147715Abstract: A method is disclosed for producing semi-insulating silicon carbide crystal with a controlled nitrogen content.Type: GrantFiled: July 28, 2003Date of Patent: December 12, 2006Assignee: Cree, Inc.Inventors: David Phillip Malta, Jason Ronald Jenny, Hudson McDonald Hobgood, Valeri F. Tsvetkov
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Patent number: 7141117Abstract: A method of fixing a seed crystal to be used for growing a silicon carbide single crystal from the seed crystal that has been fixed to a graphite base, wherein the method includes: forming a layered product by placing a metallic material whose melting point is not higher than growth temperature of the single crystal on the graphite base, disposing the seed crystal on the metallic material, and then further placing a pressing member for imposing a load on the seed crystal thereon; heat-treating the layered product at a temperature to fix the graphite base, the metallic material, and the seed crystal to each other to form one body, with the temperature being not lower than the melting point of the metallic material but not higher than the growth temperature of the single crystal; cooling the layered product; and then removing the pressing member from the layered product.Type: GrantFiled: January 27, 2005Date of Patent: November 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Norikane, Hiroaki Hoshikawa
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Patent number: 7141115Abstract: A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.Type: GrantFiled: September 2, 2004Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7135073Abstract: What is described here is a method and a temperature management and reaction chamber system for the production of nitrogenous semiconductor crystal materials of the form AXBYCZNVMW, wherein A, B, C represent elements of group II or III, N represents nitrogen, M represents an element of group V or VI, and X, Y, Z, V, W represent the mol fraction of each element in this compound, operating on the basis of gas phase compositions and gas phase successions. The invention excels itself by the provisions that for the production of the semiconductor crystal materials the production process is controlled by the precise temperature control of defined positions in the reaction chamber system under predetermined conditions.Type: GrantFiled: June 1, 2001Date of Patent: November 14, 2006Assignee: Aixtron AGInventors: Michael Heuken, Gert Strauch, Harry Protzmann, Holger Jürgensen, Oliver Schön, Dietmar Schmitz
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Patent number: 7115167Abstract: The invention provides a method of growing an (In, Ga)N multiplayer structure by molecular beam epitaxy. Each GaN or InGaN layer in the multilayer structure is grown at a substrate temperature of at least 650° C., and this provides improved material quality. Ammonia gas is used as the source of nitrogen for the growth process. Ammonia and gallium are supplied to the growth chamber at substantially constant rates, and the supply rate of indium to the growth chamber is varied to select the desired composition for the layer being grown. This allows the structure to be grown at a substantially constant growth rate. The substrate temperature is preferably kept constant during the growth process, to avoid the need to interrupt the growth process to vary the substrate temperature between the growth of one layer and the growth of another layer.Type: GrantFiled: February 19, 2002Date of Patent: October 3, 2006Assignee: Sharp Kabushiki KaishaInventors: Stewart Edward Hooper, Jennifer Mary Barnes, Valerie Bousquet, Jonathan Heffernan
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Patent number: 7108745Abstract: After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.Type: GrantFiled: April 16, 2003Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiaki Hasegawa, Ayumu Tsujimura, Isao Kidoguchi, Yuzaburo Ban
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Patent number: 7084049Abstract: A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130 of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.Type: GrantFiled: January 27, 2003Date of Patent: August 1, 2006Assignees: Osaka Prefecture, Hosiden CorporationInventors: Katsutoshi Izumi, Motoi Nakao, Yoshiaki Ohbayashi, Keiji Mine, Seisaku Hirai, Fumihiko Jobe, Tomoyuki Tanaka
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Patent number: 7083679Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.Type: GrantFiled: November 8, 2001Date of Patent: August 1, 2006Assignee: Nichia CorporationInventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
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Patent number: 7077904Abstract: The present invention relates to a method for forming silicon oxide films on substrates using an atomic layer deposition process. Specifically, the silicon oxide films are formed at low temperature and high deposition rate via the atomic layer deposition process using a Si2Cl6 source unlike a conventional atomic layer deposition process using a SiCl4 source. The atomic layer deposition apparatus used in the above process can be in-situ cleaned effectively at low temperature using a HF gas or a mixture gas of HF gas and gas containing —OH group.Type: GrantFiled: April 23, 2003Date of Patent: July 18, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung Ha Cho, Yong Il Kim, Cheol Ho Shin, Won Hyung Lee, Jung Soo Kim, Sang Tae Sim
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Patent number: 7077902Abstract: An aluminum-containing material deposition method includes depositing a first precursor on a substrate in the substantial absence of a second precursor. The first precursor can contain a chelate of Al(NR1R2)x(NR3(CH2)zNR4R5)y or Al(NR1R2)x(NR3(CH2)zOR4)y; where x is 0, 1, or 2; y is 3?x; z is an integer 2 to 8; and R1 to R5 are independently selected from among hydrocarbyl groups containing 1 to 10 carbon atoms with silicon optionally substituted for one or more carbon atoms. The method includes depositing the second precursor on the first deposited precursor, the second precursor containing a nitrogen source or an oxidant. A deposition product of the first and second precursors includes at least one of an aluminum nitride or an aluminum oxide. The deposition method can be atomic layer deposition where the first and second precursors are chemisorbed or reacted as monolayers. The first precursor can further be non-pyrophoric.Type: GrantFiled: April 13, 2004Date of Patent: July 18, 2006Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7060132Abstract: A method and apparatus for growing a thin film onto a substrate is disclosed. According to one embodiment, a plurality of substrates, each having a width and a length, are placed in a reaction space and the substrates are subjected to surface reactions of vapor-phase reactants according to the ALD method to form a thin film on the surfaces of the substrates. The reaction space comprises an elongated gas channel having a cross-section with a width greater that the height and which has a length which is at least 2 times greater than the length of one substrate in the direction of the gas flow in the channel, the channel having a folded configuration with at least one approximately 180 degree turn in the direction of the gas flow.Type: GrantFiled: October 11, 2002Date of Patent: June 13, 2006Assignee: ASM International N.V.Inventors: Sven Lindfors, Ivo Raaijmakers
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Patent number: 7048798Abstract: A method of producing a silicon carbide single crystal in which a sublimation raw material 40 is accommodated at the side of vessel body 12 in a graphite crucible 10, placing a seed crystal of a silicon carbide single crystal at the side of cover body 11 of the graphite crucible 10, the sublimation raw material 40 is sublimated by a first induction heating coil 21 placed at the side of sublimation raw material 40, a re-crystallization atmosphere is form by a second induction heating coil 20 placed at the side of cover body 11 so that the sublimation raw material 40 sublimated by the first induction heating coil 21 is re-crystallizable only in the vicinity of the seed crystal of a silicon carbide single crystal, and the sublimation raw material 40 is re-crystallized on the seed crystal of a silicon carbide single crystal, and a silicon carbide single crystal 60 is grown while keeping the whole surface of its growth surface in convex shape through the all growth processes.Type: GrantFiled: December 21, 2001Date of Patent: May 23, 2006Assignee: Bridgestone CorporationInventors: Takayuki Maruyama, Shigeki Endo
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Patent number: 7045009Abstract: A method for manufacturing a single crystal includes the steps of: flowing a raw material gas toward a seed crystal in a reactive chamber so that the single crystal grows from the seed crystal; controlling the raw material gas by a gas flow control member having a cylindrical shape; passing the raw material gas through a clearance between the seed crystal and an inner wall of the gas flow control member; and flowing a part of the raw material gas to bypass the seed crystal. The method provides the single crystal having good quality.Type: GrantFiled: August 3, 2004Date of Patent: May 16, 2006Assignees: Denso Corporation, National Institute of Advanced Industrial Science and TechnologyInventors: Tomohisa Kato, Shinichi Nishizawa, Fusao Hirose
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Patent number: 7041170Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.Type: GrantFiled: March 19, 2003Date of Patent: May 9, 2006Assignee: AmberWave Systems CorporationInventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
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Patent number: 7037372Abstract: The present invention relates to the production of thin films. In particular, the invention concerns a method of growing a thin film onto a substrate, in which method the substrate is placed in a reaction chamber and is subjected to surface reactions of a plurality of vapor-phase reactants according to the ALD method. The present invention is based on replacing the mechanical valves conventionally used for regulating the pulsing of the reactants, which valves tend to wear and intrude metallic particles into the process flow, with an improved precursor dosing system. The invention is characterized by choking the reactant flow between the vapour-phase pulses while still allowing a minimum flow of said reactant, and redirecting the reactant at these times to an other destination than the reaction chamber. The redirection is performed with an inactive gas, which is also used for ventilating the reaction chamber between the vapour-phase pulses.Type: GrantFiled: October 28, 2004Date of Patent: May 2, 2006Assignee: ASM International N.V.Inventors: Sven Lindfors, Pekka T. Soininen
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Patent number: 7033858Abstract: A method is for making at least one semiconductor device including providing a sacrificial growth substrate of Lithium Aluminate (LiAlO2); forming at least one semiconductor layer including a Group III nitride adjacent the sacrificial growth substrate; attaching a mounting substrate adjacent the at least one semiconductor layer opposite the sacrificial growth substrate; and removing the sacrificial growth substrate. The method may further include adding at least one contact onto a surface of the at least one semiconductor layer opposite the mounting substrate, and dividing the mounting substrate and at least one semiconductor layer into a plurality of individual semiconductor devices. To make the final devices, the method may further include bonding the mounting substrate of each individual semiconductor device to a heat sink. The step of removing the sacrificial substrate may include wet etching the sacrificial growth substrate.Type: GrantFiled: March 18, 2004Date of Patent: April 25, 2006Assignee: Crystal Photonics, IncorporatedInventors: Bruce H. T. Chai, John Joseph Gallagher, David Wayne Hill
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Patent number: 7033436Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.Type: GrantFiled: April 11, 2002Date of Patent: April 25, 2006Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
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Patent number: 7018597Abstract: The purpose of the invention is to provide a high resistivity silicon carbide substrate with electrical properties and structural quality suitable for subsequent device manufacturing, such as for example high frequency devices, so that the devices can exhibit stable and linear characteristics and to provide a high resistivity silicon carbide substrate having a low density of structural defects and a substantially controlled uniform radial distribution of its resistivity.Type: GrantFiled: October 28, 2002Date of Patent: March 28, 2006Assignee: Norstel ABInventors: Alexandre Ellison, Nguyen Tien Son, Björn Magnusson, Erik Janzén
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Patent number: 6994750Abstract: Reference infrared-absorption spectrum patterns are prepared in advance as a database. The infrared-absorption spectrum pattern of a film targeted for measurement is measured using FT-IR spectroscopy. Subsequently, multivariate analysis is performed using PLS regression, based on the reference infrared-absorption spectrum patterns and the infrared-absorption spectrum pattern of the target film. The film-growing temperature and other factors are then computed in accordance with the analysis results.Type: GrantFiled: September 10, 2002Date of Patent: February 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshitaka Tatsunari
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Patent number: 6953703Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.Type: GrantFiled: June 30, 2003Date of Patent: October 11, 2005Assignee: The Trustees of Boston UniversityInventor: Theodore D. Moustakas
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Patent number: 6939579Abstract: The present invention relates to improved methods and apparatus for atomic layer deposition (ALD) of thin films on substrates such as wafers and flat panel displays. The invention provides an ALD reactor comprising a first temperature regulating system to control the temperature of the substrate and a second temperature regulating system to independently control the temperature of the reaction chamber walls. The invention also provides a method for ALD of a film onto a substrate in a reaction chamber, in which the temperature of the substrate is maintained to maximize ALD on the substrate while the temperature of the reaction chamber walls is set to minimize film growth thereon, whether by ALD, condensation, physisorption or thermal decomposition. The temperature of the walls may be maintained at the same temperature as the substrate, or higher or lower than the substrate temperature, depending upon the particular reaction being used.Type: GrantFiled: March 7, 2001Date of Patent: September 6, 2005Assignee: ASM International N.V.Inventors: Niklas Bondestam, Sven Lindfors
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Patent number: 6936103Abstract: A method of suppression of Indium carry-over in the MOCVD growth of thin InGaAsP quantum wells, with low Indium content, on top of thick GaInAsP, with high Indium content. These quantum wells are essential in the stimulated emission of 808 to 880 nm phosphorous-based laser structures. The Indium carryover effect is larger in large multi wafer reactors and therefore is this invention focused on large multiwafer MOCVD reactors. This invention improves the quality of the quantum well, as measured by photo-luminescence spectra and uniformity of wavelength radiation.Type: GrantFiled: April 11, 2003Date of Patent: August 30, 2005Assignee: Spectra-Physics, Inc.Inventor: Frank Reinhardt
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Patent number: 6923859Abstract: Disclosed are an apparatus for manufacturing GaN substrate and a manufacturing method thereof enabling to prevent micro-cracks or bending of a GaN substrate by separating a substrate and a GaN layer from each other after growing the GaN layer on the substrate in the same chamber. The present invention includes a chamber for loading a substrate therein, a heating means heating the chamber, a Ga boat installed inside the chamber to receive a Ga molecule producing material, an injection pipe injecting a nitrogen molecule producing gas in the chamber, the nitrogen molecule producing gas reacting chemically on the Ga molecule producing material to form a GaN layer on the substrate, and a transparent window at a circumference of the chamber to apply a laser beam to the substrate.Type: GrantFiled: December 13, 2002Date of Patent: August 2, 2005Assignee: LG Electronics Inc.Inventor: Chin Kyo Kim
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Patent number: 6916374Abstract: An atomic layer deposition method includes positioning a plurality of semiconductor wafers into an atomic layer deposition chamber. Deposition precursor is emitted from individual gas inlets associated with individual of the wafers received within the chamber effective to form a respective monolayer onto said individual wafers received within the chamber. After forming the monolayer, purge gas is emitted from individual gas inlets associated with individual of the wafers received within the chamber. An atomic layer deposition tool includes a subatmospheric load chamber, a subatmospheric transfer chamber and a plurality of atomic layer deposition chambers. Other aspects and implementations are disclosed.Type: GrantFiled: October 8, 2002Date of Patent: July 12, 2005Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Trung Tri Doan
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Patent number: 6905544Abstract: The invention has as an object proving a carbon nanomaterial fabrication method that can continuously mass-produce a high purity carbon a nanomaterial. The tube-shaped or fiber-shaped carbon nanomaterial having carbon as the main constituent is fabricated with a compound that includes carbon (raw material) and an additive that includes a metal by using a fluidized bed reactor.Type: GrantFiled: February 21, 2003Date of Patent: June 14, 2005Assignees: Mitsubishi Heavy Industries, Ltd., Osaka Gas Co., Ltd.Inventors: Toshihiko Setoguchi, Yuichi Fujioka, Yoshihiko Tsuchiyama, Akinori Yasutake, Matsuhei Noda, Norihisa Kobayashi, Ryoichi Nishida, Hitoshi Nishino, Katsuhide Okimi, Akihiro Hachiya
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Patent number: 6905541Abstract: A precursor and method for filling a feature in a substrate. The method generally includes depositing a barrier layer, the barrier layer being formed from pentakis(dimethylamido)tantalum having less than about 5 ppm of chlorine. The method additionally may include depositing a seed layer over the barrier layer and depositing a conductive layer over the seed layer. The precursor generally includes pentakis(dimethylamido)tantalum having less than about 5 ppm of chlorine. The precursor is generated in a canister having a surrounding heating element configured to reduce formation of impurities.Type: GrantFiled: May 27, 2003Date of Patent: June 14, 2005Assignee: Applied Materials, Inc.Inventors: Ling Chen, Vincent W. Ku, Hua Chung, Christophe Marcadal, Seshadri Ganguli, Jenny Lin, Dien-Yeh Wu, Alan Ouye, Mei Chang
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Patent number: 6902620Abstract: Atomic layer deposition systems and methods are disclosed utilizing a multi-wafer sequential processing chamber. The process gases are sequentially rotated among the wafer stations to deposit a portion of a total deposition thickness on each wafer at each station. A rapid rotary switching of the process gases eliminates having to divert the process gases to a system vent and provides for atomic layer film growth sufficient for high-volume production applications. Conventional chemical vapor deposition can also be performed concurrently with atomic layer deposition within the multi-wafer sequential processing chamber.Type: GrantFiled: December 19, 2001Date of Patent: June 7, 2005Assignee: Novellus Systems, Inc.Inventors: Thomas R. Omstead, Karl B. Levy
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Patent number: 6884291Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layers each having a thickness of about 2 molecular layers or less.Type: GrantFiled: September 8, 1999Date of Patent: April 26, 2005Assignee: Ricoh Company, Ltd.Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
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Patent number: 6881263Abstract: The present invention relates to the production of thin films. In particular, the invention concerns a method of growing a thin film onto a substrate, in which method the substrate is placed in a reaction chamber and is subjected to surface reactions of a plurality of vapor-phase reactants according to the ALD method. The present invention is based on replacing the mechanical valves conventionally used for regulating the pulsing of the reactants, which valves tend to wear and intrude metallic particles into the process flow, with an improved precursor dosing system. The invention is characterized by choking the reactant flow between the vapour-phase pulses while still allowing a minimum flow of said reactant, and redirecting the reactant at these times to an other destination than the reaction chamber. The redirection is performed with an inactive gas, which is also used for ventilating the reaction chamber between the vapour-phase pulses.Type: GrantFiled: July 20, 2001Date of Patent: April 19, 2005Assignee: ASM Microchemistry OyInventors: Sven Lindfors, Pekka T. Soininen
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Patent number: 6881260Abstract: The present invention provides methods of performing atomic layer deposition to form conductive, oxidation-resistant rhodium oxide films and films comprising metals, such as platinum, alloyed with rhodium oxide. The present invention also provides memory devices and processors comprising films deposited by the above methods.Type: GrantFiled: June 25, 2002Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventors: Eugene P. Marsh, Stefan Uhlenbrock
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Patent number: 6881262Abstract: A method of forming a component is disclosed. The method includes: providing a core containing a porous material; infiltrating the core with silicon carbide; and removing the porous material of the core, thereby forming a porous substrate containing silicon carbide.Type: GrantFiled: December 23, 2002Date of Patent: April 19, 2005Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventors: Andrew G. Haerle, Han C. Chang
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Patent number: 6875271Abstract: A method for simultaneous deposition of multiple compounds on a substrate is provided. In one aspect, a gas stream is introduced into a processing chamber and flows across a substrate surface disposed therein. The gas stream includes at least one dose of a first compound and at least one dose of a second compound. The doses of the first and second compounds are separated by a time delay, and the at least one dose of the first compound and the at least one dose of the second compound are simultaneously in fluid communication with the substrate surface.Type: GrantFiled: April 9, 2002Date of Patent: April 5, 2005Assignee: Applied Materials, Inc.Inventors: W. Benjamin Glenn, Donald J. Verplancken
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Patent number: 6875274Abstract: The present invention provides a heterostructure which includes a carbon nanotube covalently linked to at least one nanocrystal. Methods for making such heterostructures, and methods for modifying the physical properties of nanotubes are also provided.Type: GrantFiled: January 13, 2003Date of Patent: April 5, 2005Assignee: The Research Foundation of State University of New YorkInventors: Stanislaus S. Wong, Sarbajit Banerjee
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Patent number: 6875272Abstract: In a method for growing a GaN based compound semiconductor on a front surface of a substrate to obtain the GaN based compound semiconductor crystal in one body, because the gas for reducing and decomposing the substrate is supplied to the rear surface of the substrate and a heat treatment is carried out in a gas atmosphere in which the nitrogen partial pressure is not less than a predetermined value, in order to remove the substrate, it can be prevented that cracks are caused in the crystal, or fracture or warp is caused by causing strain of the GaN based compound semiconductor crystal in a cooling step.Type: GrantFiled: June 14, 2002Date of Patent: April 5, 2005Assignee: Nikko Materials Co., Ltd.Inventors: Keiji Kainosho, Shinichi Sasaki
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Patent number: 6872636Abstract: A semiconductor device fabricating method includes the step of supplying BCl3 as a doping gas, SiH4 as a film forming gas, and H2 as a carrier gas to a reaction chamber of a semiconductor device fabricating apparatus, wherein SiH4, BCl3 and H2 flow in the reaction chamber on the condition that the film forming pressure ranges from about 0.1 to 100 Pa and the film forming temperature ranges from about 400 to 700° C.Type: GrantFiled: March 20, 2002Date of Patent: March 29, 2005Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Takaaki Noda, Yasuo Kunii
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Patent number: 6869481Abstract: A method and a device for regulating a pressure in an epitaxy reactor, wherein the epitaxy reactor has a wafer handling chamber WHC, a process chamber PC, and a gate valve GV connecting the two chambers. The wafer handling chamber is continuously purged with inert gas. The pressure difference between the wafer handling chamber and the process chamber is measured, and the resulting measurement signal is used in a control circuit to regulate the pressure in the wafer handling chamber. In this case the pressure in the wafer handling chamber is reduced if the pressure difference is above a predetermined value and the pressure in the wafer handling chamber is increased if the pressure difference is below a predetermined value. The predetermined pressure difference is defined as a pressure being between 5 and 500 PA. The WHC and the PC each have a gas discharge line and a gas input line.Type: GrantFiled: December 27, 2002Date of Patent: March 22, 2005Assignee: Siltronic AGInventors: Anton Schatzeder, Georg Brenninger
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Patent number: 6863726Abstract: A vapor phase growth method of an oxide dielectric film for forming an oxide dielectric film having a perovskite crystal structure expressed by ABO3 on a substrate according to the present invention includes a first step of sequentially and alternately supplying an A-site layer element material and a B-site layer element material to grow an atomic layer on the substrate to form an early layer or early core, at a first substrate temperature, and a second step of raising the temperature to a second substrate temperature that is higher than the first substrate temperature to crystallize the early layer or early core formed in the first step and simultaneously supplying both the A-site layer element material and the B-site layer element material to form an ABO3 film.Type: GrantFiled: April 22, 2003Date of Patent: March 8, 2005Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Patent number: 6860943Abstract: Disclosed is a method for producing a Group III nitride compound semiconductor including a pit formation step in which a portion of an uppermost layer of a first Group III nitride compound semiconductor layer containing one or more sub-layers, the portion containing lattice defects, is subjected to treatment by use of a solution or vapor which corrodes the portion more easily than it corrodes a portion of the uppermost layer containing no lattice defects, the first Group III nitride compound semiconductor layer not being accompanied by a substrate therefor as a result of removal therefrom, or being accompanied by a substrate such that the semiconductor layer is formed with or without intervention of a buffer layer provided on the substrate; and a lateral growth step of growing a second Group III nitride compound semiconductor layer through vertical and lateral epitaxial overgrowth around nuclei as seeds for crystal growth which are on flat portions of the uppermost layer of the first Group III nitride compounType: GrantFiled: October 11, 2002Date of Patent: March 1, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Hiroshi Watanabe
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Patent number: 6849123Abstract: To plasma-process a substrate having a large area uniformly at a high process speed to form a deposition film with uniform thickness and quality and favorable characteristics. A first high frequency power (with a frequency f1 and a power P1) and a second high frequency power (with a frequency f2 and a power P2) supplied to an electrode from a first high frequency power supply and a second high frequency power supply, respectively, are set so that the frequencies are equal to or higher than 10 MHz and equal to or lower than 250 MHz, a ratio of the frequency f2 to the frequency f1 (f2/f1) is equal to or higher than 0.1 and equal to or lower than 0.9, and a ratio of the power P2 to a total power (P1+P2) is equal to or higher than 0.1 and equal to or lower than 0.9. The frequency f2 is changed during processing the substrate.Type: GrantFiled: July 16, 2002Date of Patent: February 1, 2005Assignee: Canon Kabushiki KaishaInventors: Hiroaki Niino, Toshiyasu Shirasuna, Hitoshi Murayama, Makoto Aoki
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Patent number: 6841001Abstract: Semiconductor structure and method of fabricating a semiconductor structure are provided that include a substrate having a first in-plane unstrained lattice constant, a first layer comprising a first semiconductor material on the substrate and having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer. The variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate. The variable mismatch layer may be a layer having a strained in-plane lattice constant that substantially matches the unstrained lattice constant of the first layer.Type: GrantFiled: July 19, 2002Date of Patent: January 11, 2005Assignee: Cree, Inc.Inventor: Adam William Saxler
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Patent number: 6833027Abstract: A method of making a Schottky diode comprising the steps of: providing a single crystal diamond comprising a surface; placing the single crystal diamond in a CVD system; heating the diamond to a temperature of at least about 950° C.; providing a gas mixture capable of growing diamond film and comprising a sulfur compound through the CVD system; growing an epitaxial diamond film on the surface of the single crystal diamond; baking the diamond at a temperature of at least about 650° C. in air for a period of time that minimizes oxidation of the diamond; and fabricating a Schottky diode comprising the diamond film. A Schottky diode comprising an epitaxial diamond film and capable of blocking at least about 6 kV in a distance of no more than about 300 &mgr;m.Type: GrantFiled: September 26, 2002Date of Patent: December 21, 2004Assignee: The United States of America as represented by the Secretary of the NavyInventors: James E. Butler, Michael W. Geis, Donald D. Flechtner, Robert L. Wright
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Patent number: 6824611Abstract: A method and apparatus for controlled, extended and repeatable growth of high quality silicon carbide boules of a desired polytype is disclosed which utilizes graphite crucibles coated with a thin coating of a metal carbide and in particular carbides selected from the group consisting of tantalum carbide, hafnium carbide, niobium carbide, titanium carbide, zirconium carbide, tungsten carbide and vanadium carbide.Type: GrantFiled: October 8, 1999Date of Patent: November 30, 2004Assignee: Cree, Inc.Inventors: Olle Claes Erik Kordina, Michael James Paisley
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Patent number: 6821340Abstract: To provide a method of manufacturing silicon carbide by forming silicon carbide on a substrate surface from an atmosphere containing a silicon carbide feedstock gas comprising at least a silicon source gas and a carbon source gas under condition 1 or 2 below: Condition 1: the partial pressure ps of silicon source gas is constant (with ps>0), the partial pressure of carbon source gas consists of a state pc1 and a state pc2 that are repeated in alternating fashion, wherein pc1 and pc2 denote partial pressures of carbon source gas, pc1>pc2, and pc1/ps falls within a range of 1-10 times the attachment coefficient ratio (Ss/Sc), pc2/ps falls within a range of less than one time Ss/Sc; Condition 2: the partial pressure pc of carbon source gas is constant (with pc>0), the partial pressure of silicon source gas consists of a state ps1 and a state ps2 that are repeated in alternating fashion, wherein ps1 and ps2 denote partial pressures of silicon source gas, ps1<ps2, and pc/ps1 falls within a range of 1Type: GrantFiled: May 31, 2001Date of Patent: November 23, 2004Assignee: Hoya CorporationInventors: Hiroyuki Nagasawa, Takamitsu Kawahara, Kuniaki Yagi
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Patent number: 6808758Abstract: A process for producing thin layers in electronic devices such as integrated circuit chips, is provided. The process includes the steps of injecting a precursor fluid into a thermal processing chamber containing a substrate, such as a semiconductor wafer. The precursor fluid is converted into a solid which forms a layer on the substrate. In accordance with the present invention, the precursor fluid is pulsed into the process chamber in a manner such that the fluid is completly exhausted or removed from the chamber in between each pulse. Light energy can be used in forming the solid layers.Type: GrantFiled: June 9, 2000Date of Patent: October 26, 2004Assignee: Mattson Technology, Inc.Inventor: Randhir P. S. Thakur
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Patent number: 6805745Abstract: Disclosed is a method for reproducibly producing large size, single crystals in a crystal growth chamber. The method includes the steps of: (a) forming a plurality of smaller size tiles of single crystals of substantially the same crystal orientation as the desired large size, single crystal; (b) assembling the plurality of smaller tiles into a structure having a larger size while minimizing gapping between adjacent tiles; (c) placing the assembly of smaller tiles formed in step (b) into a growth chamber; and (d) through a growth reaction carried out in the growth chamber, forming a large size single crystal using the assembly of smaller tiles formed in step (b) as a seed crystal for the growth reaction.Type: GrantFiled: September 11, 2002Date of Patent: October 19, 2004Assignee: II-VI IncorporatedInventors: David W. Snyder, William J. Everson
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Patent number: 6790278Abstract: The present invention provides a method for preparing a novel low-resistance p-type SrTiO3 capable of opening the way for oxide electronics in combination with an already developed low-resistance n-type SrTiO3. The method is characterized in that an acceptor and a donor are co-doped into a perovskite-type transition-metal oxide SrTiO3 during crystal growth.Type: GrantFiled: December 23, 2002Date of Patent: September 14, 2004Assignee: Japan Science and Technology AgencyInventors: Hiroshi Yoshida, Kiyoshi Betsuyaku, Tomoji Kawai, Hidekazu Tanaka
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Patent number: 6790279Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.Type: GrantFiled: July 2, 2002Date of Patent: September 14, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Seiji Nagai
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Patent number: 6783590Abstract: A method of growing a thin film onto a substrate placed in a reaction chamber according to the ALD method by subjecting the substrate to alternate and successive surface reactions. The method includes providing a first reactant source and providing an inactive gas source. A first reactant is fed from the first reactant source in the form of repeated alternating pulses to a reaction chamber via a first conduit. The first reactant is allowed to react with the surface of the substrate in the reaction chamber. Inactive gas is fed from the inactive gas source into the first conduit via a second conduit that is connected to the first conduit at a first connection point so as to create a gas phase barrier between the repeated alternating pulses of the first reactant entering the reaction chamber. The inactive gas is withdrawn from said first conduit via a third conduit connected to the first conduit at a second connection point.Type: GrantFiled: April 16, 2001Date of Patent: August 31, 2004Assignee: ASM International N.V.Inventors: Sven Lindfors, Pekka T. Soininen