Processes Of Growth With A Subsequent Step Acting On The Crystal To Adjust The Impurity Amount (e.g., Diffusing, Doping, Gettering, Implanting) Patents (Class 117/2)
  • Patent number: 6056817
    Abstract: A process for producing a semi-insulating InP single crystal and a semi-insulating InP single crystal are disclosed. The process comprises: a first step heat-treatment for heating an undoped InP single crystal having a concentration of a residual impurity of 0.05 ppmw or less containing at least one of Fe, Co and Cr, at a temperature of not less than 930.degree. C. and less than 1000.degree. C. in an atmosphere of phosphorous vapor pressure in the ampoule which is not less than a dissociation pressure of InP in equilibrium at the temperature and which is not more than 15 atm; and a second step heat-treatment for thereafter heating the InP single crystal at a temperature of not less than 662.degree. C. and less than 900.degree. C. in an atmosphere of phosphorous vapor pressure in the ampoule which is not less than 5 atm nor more than 50 atm. The semi-insulating InP single crystal substrate has a uniformity of mobility not more than 10% on the surface of the substrate.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: May 2, 2000
    Assignee: Japan Energy Corporation
    Inventors: Masayuki Uchida, Osamu Oda
  • Patent number: 6048394
    Abstract: A method is disclosed for forming a single crystal relaxor based material, including the following steps: providing a seed single crystal plate, providing a first and second polycrystalline structure, bonding the top surface of the seed crystal plate to the outer surface of the first polycrystalline structure, bonding the bottom surface of the seed crystal plate to the outer surface of the second polycrystalline structure, and annealing the bonded structure.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: April 11, 2000
    Assignee: Competitive Technologies of PA, Inc.
    Inventors: Martin P. Harmer, Helen M. Chan, Ho-Yong Lee, Adam M. Scotch, Tao Li, Frank Meschke, Ajmal Khan
  • Patent number: 6036769
    Abstract: An indium phosphate semiconductor substrate is prepared for subsequent growth of epitaxial layers to form a semiconductor device. In the preparation, the substrate is first annealed to promote any tendency for surface accumulation of impurity atoms by diffusion from the substrate and to promote impurity atom removal from the surface of the substrate. The substrate is then surface etched to remove further impurities and to provide a clean, flat surface for subsequent epitaxial layer growth. The final stage of preparation involves growing a semi-insulating buffer layer on the substrate to isolate the device epitaxial layers from the substrate.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: March 14, 2000
    Assignee: British Telecommunications Public Limited Company
    Inventors: Paul C. Spurdens, Mark A. Salter, Michael J. Harlow, David J. Newson
  • Patent number: 6036770
    Abstract: Methods are described for the depositing of a plurality of films, preferably mercury cadmium telluride (HgCdTe), whose compositions vary in a controlled manner to provide unique infrared spectral absorption and detection properties. HgCdTe films 64 and 70 are deposited on opposite sides of electrically insulating, IR transmissive film 42. Initially these HgCdTe films may be of uniform composition laterally from 62 to 66 and 68 to 72. However the interdiffusion and segregation coefficients of Hg and Cd are different and vary differently with respect to temperature. By placing film 70 in contact with heater 9, a controlled lateral gradient in composition of the film may be effected because 44 is hotter than 45 and will produce higher Cd concentration at 68 than 72. Similarly 62 will be higher in Cd than 66, however, the gradient will be much less because 64 is cooler than 70. Through the use of a heater 60, the lateral compositional gradient of 64 may be varied with respect to film 70.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: March 14, 2000
    Assignee: Raytheon Company
    Inventors: Dipankar Chandra, Donald F. Weirauch, Thomas C. Penn
  • Patent number: 6015459
    Abstract: Method is provided for controlling the concentration of a dopant introduced into an epitaxial film during CVD or sublimation growth by controlling the energy of dopant atoms impinging on the film in a supersonic beam. Precursor materials may also be introduced by supersonic beam. Energy of the dopant atoms may be changed by changing flow conditions in the supersonic beam or changing carrier gases. Flow may be continuous or pulsed. Examples of silicon carbide doping are provided.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: January 18, 2000
    Assignee: Extreme Devices, Inc.
    Inventors: Keith D. Jamison, Mike L. Kempel
  • Patent number: 5997634
    Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO.sub.2 and Si.sub.3 N.sub.4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: December 7, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sujit Sharan
  • Patent number: 5968259
    Abstract: Provided are high-purity quartz glass having a high purity, in particular, with little zirconium (Zr) and manufactured at low costs from natural quartz as the starting material and a method for the preparation thereof.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: October 19, 1999
    Assignee: Shin-Etsu Quartz Products Co., Ltd.
    Inventors: Katsuhiko Kemmochi, Hiroyuki Miyazawa, Hiroyuki Watanabe, Kiyotaka Maekawa, Chuzaemon Tsuji, Manabu Saitou
  • Patent number: 5964944
    Abstract: An easy and low-cost method of producing a large-size and high-purity silicon carbide (SiC) single crystal includes reacting silicon vapor directly with a carbon-containing compound gas under a heated atmosphere (growth space 14) to grow a silicon carbide single crystal (15) on a silicon carbide seed crystal (12), in which the silicon vapor generated from molten silicon (13) is used as a silicon vapor source, and a hydrocarbon gas (9) (e.g., propane gas) is used as the carbon-containing compound gas.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 12, 1999
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Naohiro Sugiyama, Atsuto Okamoto, Toshihiko Tani, Nobuo Kamiya
  • Patent number: 5961713
    Abstract: A semiconductor silicon wafer (10) useful as a calibration standard for measurement of a thickness (18) of a microdefect-free layer (16) is formed by depositing an epitaxial layer onto a substrate (12) having an interstitial oxygen concentration suitable for precipitating oxide. Large, uniform oxide microdefects (14) are formed in the substrate by maintaining the semiconductor silicon wafer at between 600.degree. C. and 900.degree. C. to nucleate oxide precipitates that are then grown at between 800.degree. C. and 1,200.degree. C. Because the epitaxial layer contains no oxide precipitate nuclei to form microdefects, the epitaxial layer remains a microdefect-free layer and has a relatively sharp, easily detectable boundary with the substrate. The epitaxial layer can be polished to a reduced thickness, if desired.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: October 5, 1999
    Assignee: SEH America, Inc.
    Inventor: Witawat Wijaranakula
  • Patent number: 5948159
    Abstract: When the silicon single crystal is pulled up, the nucleation rate of the void cluster is obtained from the forming energy of the cluster of the vacancies in the silicon single crystal. The growth shrinkage of the cluster is obtained basing on the deviation of the flowing-into amount to the cluster of the vacancies and the self-interstitials, and the pulling-up speed or the temperature distribution of the furnace is modified to inhibit the growth of the cluster so as to inhibit the grown-in defects of the silicon single crystal.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: September 7, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kozo Nakamura, Toshiaki Saishoji, Toshimichi Kubota
  • Patent number: 5935320
    Abstract: A process for producing silicon wafers with low defect density is one wherein a) a silicon single crystal having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 is produced by molten material being solidified to form a single crystal and is then cooled, and the holding time of the single crystal during cooling in the temperature range of from 850.degree. C. to 1100.degree. C. is less than 80 minutes; b) the single crystal is processed to form silicon wafers; and c) the silicon wafers are annealed at a temperature of at least 1000.degree. C. for at least one hour. Also, it is possible to prepare a silicon single crystal based upon having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 and a nitrogen doping concentration of at least 1*10.sup.14 /cm.sup.3 for (a) above.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: August 10, 1999
    Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AG
    Inventors: Dieter Graef, Wilfried Von Ammon, Reinhold Wahlich, Peter Krottenthaler, Ulrich Lambert
  • Patent number: 5913974
    Abstract: A heat treating method in which the ultimate temperature of semiconductor single crystal substrates being heat treated is made constant. The method includes heating at least the back surface of the substrate directly with radiant heat. The heating output is controlled according to the reflectivity of the back surfaces of the semiconductor single crystal substrates. In particular, the heating output is increased or decreased in proportion to the increase or decrease in the reflectivity of the back surface of the substrates from one substrate to the next. The method makes its possible to keep a uniform crystal quality throughout the heat treated semiconductor single crystal substrates.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: June 22, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Hitoshi Habuka
  • Patent number: 5904766
    Abstract: Provided is a process for preparing a bismuth compound at a heat treatment temperature lower than conventional. A bismuth compound is prepared by the steps of heating under vacuum to form a reduced phase and heating under oxidizing environment of normal or lower pressure.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: May 18, 1999
    Assignee: Sony Corporation
    Inventors: Takaaki Ami, Katsuyuki Hironaka, Koji Watanabe, Akio Machida
  • Patent number: 5902393
    Abstract: Disclosed is a method of growing 4 gallium nitride-based crystal by vapor phase epitaxy, suitable for mass production, without the necessity of thermal processing after completion of the crystal growth. The temperature of the substrate crystal immediately after completion of the crystal growth is 700.degree. C. or higher, and cooling of the substrate crystal at 700.degree. C. or lower after completion of the crystal growth is performed in an atmosphere of a hydrogen-fee carrier gas.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: May 11, 1999
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Akira Usui, Yasunori Mochizuki
  • Patent number: 5891244
    Abstract: The present invention provides a process for preparing SOI wafer, more specifically, a process for preparing a large-sized SOI wafer of high quality of crystallization employing an apparatus for the manufacture of the SOI wafer in a simple and efficient manner. The apparatus for the manufacture of SOI wafer of the invention comprises electric furnace for heating polycrystalline silicon filled in a heat-resistant container; means for moving up and down of an insulating substrate whose one side is accompanied with silicon single crystalline seed, and immersing the substrate in the molten silicon filled in the heat-resistant container to form a thin single crystalline film on the substrate; and, shapers to keep a constant thickness of the thin single crystalline film which is formed on the insulating substrate by the moving means.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Do-Hyun Kim, Jong-Hoe Wang
  • Patent number: 5891242
    Abstract: An apparatus for and a method of determining the epitaxial layer thickness and transition width in epitaxial single crystal silicon wafers are provided. The apparatus provides an epitaxial single crystal silicon wafer comprising an isotopically enriched doped substrate. The method involves a process of applying Second Ion Mass Spectrometry (SIMS) to the isotopically enriched doped wafer for determining its epitaxial layer thickness and transition width.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 6, 1999
    Assignee: Seh America, Inc.
    Inventors: William Charles Pesklak, Bruce Laurence Colburn
  • Patent number: 5855668
    Abstract: A surface treating method of single crystals by which single crystals for substrates having finished surfaces showing pit-free and atomic scale step structures are obtained by treating the {100}-plane surfaces of single-crystal SrTiO.sub.3 substrates by dissolving two-dimensional-lattice atomic layers forming the surfaces one layer by one layer by using a fluorine-based acidic solution (maintained at >35.degree. C. in temperature and <4 in pH) as a solution A and water as a solution B by alternately immersing the substrates in the substrates in the solution A and B.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: January 5, 1999
    Assignee: Kabushiki Kaisha Shinkosha
    Inventors: Masashi Kawasaki, Hideomi Koinuma, Kazuhiro Takahashi, Takuzo Yonezawa
  • Patent number: 5837929
    Abstract: A method of making a microelectronic thermoelectric device comprises the steps of providing a substrate of a predetermined material, creating thermally isolated, alternating P-type and N-type semiconductor materials on the substrate, electrically connecting the P-type areas to adjacent N-type areas on opposite sides of each P-type area so that each side of a P-type area is connected to an adjacent different N-type area and leaving a free P-type end and a free N-type end, and providing an electrical lead on the free end of the P-type area and an electrical lead on the free end of said N-type area for connection to a source of electrical power. Further, a microelectronic thermoelectric device comprises a plurality of sections of semiconductor material of a first conductivity type and a plurality of sections of second conductivity type opposite to the first type. The sections are arranged to alternate from one type to the other and are thermally isolated from one another.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: November 17, 1998
    Assignee: Mantron, Inc.
    Inventor: Lonnie W. Adelman
  • Patent number: 5830268
    Abstract: The invention relates to the growth of nickel manganese oxide monocrystals having a cubic spinel geometry. Methods of their growth and sensors constructed with same are also described.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 3, 1998
    Assignee: Thermometrics, Inc.
    Inventors: Carol Zwick Rosen, Donald G. Wickham
  • Patent number: 5817170
    Abstract: A process for producing a ferroelectric lead zirconate titanate dielectric for a semiconductor device by applying a lead titanate seeding layer to a substrate before applying the lead zirconate titanate film, and a semiconductor device produced in accordance with the process. The lead titanate seeding layer allows the subsequent lead zirconate titanate to be annealed at a significantly lower seeding temperature, to lessen interdiffusion among the films, electrodes and substrate and to lessen thermal stresses.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: October 6, 1998
    Assignees: Ceram Incorporated, Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.
    Inventors: Seshu B. Desu, Chi Kong Kwok
  • Patent number: 5792253
    Abstract: A cylindrical alkali halide single-crystal-type ingot having an axis generally coinciding with the ?001! crystallographic direction is compressed in a heated dual platen press. To produce an approximately rectangular compressed ingot that is devoid of cracks and fissures at and adjacent the periphery, the surface of the ingot is flatted. For crystals having a face-centered lattice (e.g. NaI), the flat is parallel to the (100) crystallographic plane. For crystals having a body-centered lattice (e.g. CsI), the flat is parallel to the (110) crystallographic plane. The flat is placed on the lower platen of the press to properly orient the crystallographic structure of the ingot with respect to the direction of compression.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: August 11, 1998
    Assignee: Siemens Medical Systems, Inc.
    Inventors: Lev G. Eidelman, Olexy V. Radkevich
  • Patent number: 5788763
    Abstract: In a heat history initializing step, a heat treatment in performed in an atmosphere including at least one of hydrogen, helium, and argon while the temperature is increased in a range of 700.degree. C. to 1,000.degree. C. at a rate of 15.degree.-1,000.degree. C./min. In a controlled nuclei growing step, a heat treatment is performed in the above atmosphere while the temperature is kept constant in a range of 850.degree. C. to 980.degree. C. for 0.5-60 minutes.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: August 4, 1998
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Kenro Hayashi, Ryuji Takeda, Katsuhiro Chaki, Ping Xin, Jun Yoshikawa, Hiroyuki Saito
  • Patent number: 5769941
    Abstract: A seed (22) is formed to have a ?110! direction (24) that is at an angle (26) to the pull direction (23) used for growing a semiconductor ingot (36). Dislocations (34) in the ingot (36) terminate on the surface of the neck (37) of the ingot, and do not propagate into the body (38) of the ingot (36).
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: June 23, 1998
    Assignee: Motorola, Inc.
    Inventor: Herng-Der Chiou
  • Patent number: 5766340
    Abstract: A method for poling a ferroelectric crystal includes heating the crystal to a temperature above its Curie temperature and applying a first selected voltage to the electrodes to apply an electric field to the crystal. The temperature of the crystal is then reduced to a temperature below the Curie temperature of the crystal, and a second electric field having polarity opposite to the polarity of the first electric field is applied to the crystal. Application of the second electric field reduces nonuniformity in ion concentration across the crystal.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: June 16, 1998
    Assignee: Litton Systems, Inc.
    Inventor: Christine E. Geosling
  • Patent number: 5743955
    Abstract: A method for generating well-crystallized photo- and cathodoluminescent oxide phosphor powders. The method of this invention uses hydrothermal synthesis and annealing to produce nearly monosized (RE.sub.1-x Ln.sub.x)(P.sub.1-y V.sub.y)O.sub.4 (Ln.dbd.Ce.fwdarw.Lu) phosphor grains with crystallite sizes from 0.04 to 5 .mu.m. Such phosphors find application in cathode-ray tube, flat-panel, and projection displays.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: April 28, 1998
    Inventor: Mark L. F. Phillips
  • Patent number: 5728212
    Abstract: A compound semiconductor crystal has a reduced dislocation density. The compound semiconductor crystal doped with an impurity satisfies the following relations, wherein c.c. represents its carrier concentration and .eta. represents its activation factor:.eta..ltoreq.c.c./(7.8.times.10.sup.15) (1).eta..ltoreq.(10/19).times.(197-2.54.times.10.sup.-17 .times.c.c.) (2).eta..gtoreq.c.c./(3.6.times.10.sup.16) (3)A method which can prepare a compound semiconductor crystal doped with an impurity and having a prescribed carrier concentration with excellent reproducibility comprises the steps of melting a raw material for the compound semiconductor crystal in a crucible, and controlledly cooling the obtained raw material melt, thereby growing a crystal. The time required for cooling the raw material melt from the melting point T of the raw material to 2/3T is so controlled as to adjust the carrier concentration to a prescribed level.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: March 17, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tetsuya Inoue, Yoshiaki Hagi
  • Patent number: 5702522
    Abstract: A crystal puller cell (18) provides a low particulate environment for an individual crystal puller (28). The airflow within each cell is adjustable so that a particulate level appropriate to the activity within the cell is maintained, thereby avoiding the cost of maintaining an entire growing hall (10) at a constant high level of cleanliness. Each cell includes a multi-level floor (46) that includes an operator floor (48) and a maintenance floor (52). A door (62) at the maintenance floor level opens onto a maintenance aisle used to service the machines. A door (64), at the operator floor level, opens onto a clean aisle for transporting raw material and finished product. The cell walls can include magnetic shielding if a magnetic growing process is used to reduce exposure of operators and other machines to intense magnetic fields.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: December 30, 1997
    Assignee: SEH America, Inc.
    Inventors: Kazuo Sakauchi, Yoshihiro Hirano, Akira Uchikawa
  • Patent number: 5695557
    Abstract: A bonded substrate and a process for its production is provided to solve the problem involved in the heat treatment which tends to cause troubles such as break, separation and warpage of the substrates bonded. A single-crystal semiconductor epitaxially grown on a porous semiconductor substrate is bonded to an insulator substrate, and the semiconductor substrate is removed by etching, grinding, or a combination of the both, where no heat treatment is carried out or, even if carried out, only once.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: December 9, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara
  • Patent number: 5653801
    Abstract: Contamination of aluminum-containing compound semiconductors is greatly reduced by an improved method for manufacturing the semiconductors, wherein the growing semiconductor crystal is doped with a predetermined concentration of selenium. The method of the present invention can be used to reduce contaminants in both p-type and n-type semiconductors.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: August 5, 1997
    Assignee: University of Maryland Baltimore County
    Inventors: Jyh-Chia Chen, Zhenchun Huang
  • Patent number: 5653798
    Abstract: A substrate for the growth of monocrystalline .beta.-SiC is formed by providing a body of monocrystalline hexagonal material having a planar surface with a lattice parameter that is within .+-.5% of the lattice parameter of 6H.alpha.-SiC in the basal plane and growing a body of monocrystalline cubic material on the surface to provide a planar cubic material surface that is without grain boundaries, subgrain boundaries, double positioning boundaries, and pits. The cubic material, for example TiC, ZrC, HfC, or TiN, has a rock salt structure and a lattice parameter within .+-.5% of the lattice parameter of .beta.-SiC. Monocrystalline .beta.-SiC can be nucleated and grown on the surface of the cubic material.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Oregon Graduate Institute of Science and Technology
    Inventors: James D. Parsons, Ajay Kumar Chaddha, Her Song Chen, Jin Wu
  • Patent number: 5650007
    Abstract: Spinel single crystal filaments are produced by a method which consists essentially of solidifying in one direction a melt consisting essentially of 30 to 70% by weight of magnesium oxide, 10 to 45% by weight of aluminum oxide, and 15 to 45% by weight of silicon dioxide, thereby forming a composite texture containing a matrix of forsterite and filaments of spinel dispersed in the matrix, and then separating the filaments of spinel from the composite texture.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: July 22, 1997
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Shoji Kawakami, Hideyo Tabata, Toyoaki Yamada, Shunsaku Sakakibara
  • Patent number: 5641353
    Abstract: The present invention is to manufacture a low hydrogen-concentration silicon crystal having less micro defects caused from oxygen precipitation generated during an annealing process. Particularly, a silicon crystal including hydrogen concentration lower than 0.55.times.10.sup.11 cm.sup.-3, where the hydrogen concentration dependency is small and the micro defect density is less, may be used for a substrate of semiconductor devices. The low hydrogen-concentration silicon substrate is manufactured by measuring the hydrogen concentrations in a silicon crystal and in a hydrogen-doped silicon crystal having a known hydrogen concentration, where both the silicon crystals have been annealed at an equal condition so as to generate thermal donors therein, and by comparing thus measured hydrogen concentrations.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: June 24, 1997
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Masaaki Koizuka
  • Patent number: 5639299
    Abstract: The disclosed method of making a compound semiconductor single-crystalline substrate for liquid phase epitaxial growth has a relatively low cost and excellent practicality. The compound semiconductor single-crystalline substrate is prepared to have a surface roughness of at least 1 .mu.m and not more than 10 .mu.m as measured over a line of 1 mm length. This substrate is employed as a substrate for an epitaxial wafer for an infrared- or visible light-emitting diode. Due to its particular roughness, the substrate can be prevented from slipping or falling while it is transported during processing. Furthermore, no lapping and polishing are required for manufacturing the substrate. Thus, the substrate for liquid phase epitaxial growth can be provided at a relatively low cost.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: June 17, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tetsuya Inoue, Makoto Otsuki, Tetsuichi Yokota
  • Patent number: 5632811
    Abstract: In order to stably retain an oxide-based melt consisting essentially of yttrium or a lanthanoid element, barium, copper and oxygen at a prescribed temperature with no impurity contamination thereby preparing a large oxide crystal of high quality from the melt, an oxide melt consisting essentially of yttrium or a lanthanoid element, barium, copper and oxygen is stored in a first crucible, which in turn is held in a second crucible. The first crucible is made of a material which is an oxide of at least one element forming the melt having a melting point higher by at least 10.degree. C. than a melt retention temperature and causing no structural phase transition up to a temperature higher by 10.degree. C. than the aforementioned prescribed temperature, with solubility of not more than 5 atomic percent with respect to the melt in a temperature range from the room temperature to a temperature higher by 10.degree. C. than the melt retention temperature.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: May 27, 1997
    Assignees: Sumitomo Electric Industries, Ltd., International Superconductivity Technology Center
    Inventors: Yasuo Namikawa, Yasuji Yamada, Satoshi Koyama, Yuh Shiohara, Shoji Tanaka
  • Patent number: 5618345
    Abstract: A self-supporting thin film of silicon single crystal is produced essentially by the steps of implanting boron ions in a silicon single crystal substrate from one major surface thereof to form a high impurity concentration layer having a high boron concentration in the substrate; heating the silicon single crystal substrate formed with the high impurity concentration layer in an atmosphere containing oxygen to form an oxide film on the surface of the single crystal substrate and make the high impurity concentration layer resistant to etching; masking all of the oxide film surface other than that at the center region on the surface opposite from that implanted with boron ions and then exposing the high impurity concentration layer by high-speed mask etching followed by selective etching; and removing the oxide film.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: April 8, 1997
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Kazuo Saitoh, Hiroaki Niwa, Setsuo Nakao, Soji Miyagawa
  • Patent number: 5612014
    Abstract: A compound semiconductor crystal has a reduced dislocation density reduced. The compound semiconductor crystal doped with an impurity satisfies the following relations, wherein c.c. represents its carrier concentration and .eta. represents its activation factor:.eta..ltoreq.c.c./(7.8.times.10.sup.15) (1).eta..ltoreq.(10/19).times.(197-2.54.times.10.sup.-17 .times.c.c.) (2).eta..gtoreq.c.c./(3.6.times.10.sup.16) (3)A method which can prepare a compound semiconductor crystal doped with an impurity and having a prescribed carrier concentration with excellent reproducibility comprises the steps of melting a raw material for the compound semiconductor crystal in a crucible, and controllably cooling raw material melt, making thereby growing a crystal. The time required for cooling the raw material melt from the melting point T of the raw material to 2/3T is so controlled as to adjust the carrier concentration to a prescribed level.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: March 18, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tetsuya Inoue, Yoshiaki Hagi
  • Patent number: 5611855
    Abstract: A semiconductor silicon wafer (10) useful as a calibration standard for measurement of a thickness (18) of a microdefect-free layer (16) is formed by depositing an epitaxial layer onto a substrate (12) having an interstitial oxygen concentration suitable for precipitating oxide. Large, uniform oxide microdefects (14) are formed in the substrate by maintaining the semiconductor silicon wafer at between 600.degree. C. and 900.degree. C. to nucleate oxide precipitates that are then grown at between 800.degree. C. and 1,200.degree. C. Because the epitaxial layer contains no oxide precipitate nuclei to form microdefects, the epitaxial layer remains a microdefect-free layer and has a relatively sharp, easily detectable boundary with the substrate. The epitaxial layer can be polished to a reduced thickness, if desired.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: March 18, 1997
    Assignee: SEH America, Inc.
    Inventor: Witawat Wijaranakula
  • Patent number: 5609682
    Abstract: An improved method is proposed for the preparation of a semiconductor silicon single crystal of N-type by the Czochralski process, which is free from the problem of occurrence of delayed OSFs as defects in the single crystal even after prolonged storage at room temperature based on the discovery that presence of a certain amount of aluminum in the melt of silicon contained in a fused silica glass crucible acts to suppress occurrence of delayed OSFs as a type of defects in the single crystal while copper as an impurity acts adversely in this regard. With a known fact that an about 30 .mu.m thick inner surface layer of the crucible is melted down into the silicon melt during the single crystal pulling-up process, namely, the invention proposes use of a crucible of which the inner surface layer of 30 .mu.m thickness contains aluminum in an average concentration of 40 to 500 ppm by weight while the content of copper is as low as possible not to exceed 0.5 ppb by weight.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: March 11, 1997
    Assignees: Shin-Etsu Handotai Co., Ltd., Shin-Etsu Quartz Co., Ltd.
    Inventors: Wataru Sato, Masahiro Sakurada, Ohta Tomohiko, Katsuhiko Kemmochi
  • Patent number: 5603763
    Abstract: A single crystal growing method for producing a high-quality and large-diameter single crystal of a compound semiconductor with a good yield, is disclosed.A volatile element 2 is first put into a reservoir portion 1A of a quartz ampule 1. Further, a crucible 4 made of pBN, which contains a raw material 3A of a compound semiconductor, is placed in the quartz ampule 1, the vacuum sealing of which is then performed. While a vapor pressure controlling operation is performed, a furnace temperature distribution is controlled in such a manner that a vertical first temperature gradient .alpha. .degree. C./cm) in the vicinity of an outside wall of the quartz ampule corresponding to a raw melt 3B is smaller than a vertical second temperature gradient (.beta. .degree. C./cm) in a range above the top end of the crucible 4 and simultaneously, the temperature is gradually lowered. Furthermore, .alpha. ranges from 51/D.sup.2 to 102/D.sup.2 .degree. C./cm, and preferably ranges from 58/D.sup.2 to 83/D.sup.2 .degree. C.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: February 18, 1997
    Assignee: Japan Energy Corporation
    Inventors: Yoshiteru Taniguchi, Toshiaki Asahi
  • Patent number: 5593494
    Abstract: Process for controlling the density of oxygen precipitate nucleation centers in single crystal silicon. In the process, the single crystal silicon is annealed at a temperature of at least about 350.degree. C. to cause the formation of oxygen precipitate nucleation centers in the single crystal silicon. During the annealing step, the single crystal silicon is heated (or cooled) to achieve a first temperature, T.sub.1, which is between about 350.degree. C. and about 500.degree. C. The temperature is then increased from T.sub.1 to a second temperature, T.sub.2, which is between about 500.degree. C. and about 750.degree. C. with the average rate of temperature increase from T.sub.1 to T.sub.2 being less than about 25.degree. C. per minute. The annealing is terminated at a point in time when the oxygen precipitate nucleation centers are capable of being dissolved by heat-treating the silicon at a temperature not in excess of about 1150.degree. C.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: January 14, 1997
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert Falster
  • Patent number: 5588992
    Abstract: A solid state method of converting a polycrystalline ceramic body to a single crystal body includes the steps of doping the polycrystalline ceramic material with a conversion-enhancing dopant and then heating the polycrystalline body at a selected temperature for a selected time sufficient to convert the polycrystalline body to a single crystal. The selected temperature is less than the melting temperature of the polycrystalline material and greater than about one-half the melting temperature of the material. In the conversion of polycrystalline alumina to single crystal alumina (sapphire), examples of conversion-enhancing dopants include cations having a +3 valence, such as chromium, gallium, and titanium.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: December 31, 1996
    Assignee: General Electric Company
    Inventors: Curtis E. Scott, Mary Sue Kaliszewski, Lionel M. Levinson
  • Patent number: 5588991
    Abstract: In a process for producing a chlorogallium phthalocyanine crystal comprising mechanically dry-grinding chlorogallium phthalocyanine and subjected to crystal conversion, the weight ratio of chlorogallium phthalocyanine to the grinding media is set at a range of from 1/5 to 1/1000. The resulting chlorogallium phthalocyanine crystal excels in the dispersibility in a binding resin and the stability in the dispersion.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: December 31, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Kazuya Hongo, Hitoshi Takimoto
  • Patent number: 5553566
    Abstract: A method for fabricating semiconductor substrates with resistivity below 0.02 ohm-cm is provided. This low resistivity is achieved by doping a silicon melt with a phosphorus concentrations above 1.times.10.sup.18. The silicon melt is also doped with a germanium concentration that is 1.5 to 2.5 times that of the phosphorus concentration and a stress and dislocation free crystalline boule is grown. Phosphorus in high concentrations will induce stress in the crystal lattice due to the difference in the atomic radius of silicon atoms versus phosphorus atoms. Germanium compensates for the atomic radius mismatch and also retards the diffusion of the phosphorus as the diffusion coefficient remains relatively constant with a doping of 1.times.10.sup.18 to 1.times.10.sup.21 atoms per cm.sup.3. This will retard phosphorus from diffusing into an overlying epitaxial layer and retard other layers formed on the substrate from being auto-doped.
    Type: Grant
    Filed: June 22, 1995
    Date of Patent: September 10, 1996
    Assignee: Motorola Inc.
    Inventors: Hering-Der Chiou, Geoffrey J. Crabtree
  • Patent number: 5505157
    Abstract: The present invention is to manufacture a low hydrogen-concentration silicon crystal having less micro defects caused from oxygen precipitation generated during an annealing process. Particularly, a silicon crystal including hydrogen concentration lower than 0.55.times.10.sup.11 cm.sup.-3, where the hydrogen concentration dependency is small and the micro defect density is less, may be used for a substrate of semiconductor devices. The low hydrogen-concentration silicon substrate is manufactured by measuring the hydrogen concentrations in a silicon crystal and in a hydrogen-doped silicon crystal having a known hydrogen concentration, where both the silicon crystals have been annealed at an equal condition so as to generated thermal donors therein, and by comparing thus measured hydrogen concentrations.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: April 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Masaaki Koizuka
  • Patent number: 5498595
    Abstract: A method for activating superconducting material comprises generating a species of oxygen ions, heating the material and introducing the oxygen ions to said material by the application of a low-gradient drift field between the source of oxygen ions and a substrate including the superconducting material.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: March 12, 1996
    Assignee: British Technology Group Limited
    Inventor: William Eccleston
  • Patent number: 5477807
    Abstract: There has been provided by the present invention a process for producing a single crystal of potassium niobate which comprises disposing a positive electrode directly or via a semi-insulating substance layer on one c-plane of a single crystal of potassium niobate and also a negative electrode via a semi-insulating substance layer on the other c-plane of the single crystal of potassium niobate, said positive and negative electrodes being disposed in mutually facing relationship, and applying voltage between the positive and negative electrodes so as to pole (convert to the single-domain state) the single crystal of potassium niobate, and which enables to pole the entire region of the single crystal of potassium niobate without quality deterioration.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: December 26, 1995
    Assignee: Mitsui Petrochemical Industries, Ltd.
    Inventors: Kazuhiro Yamada, Shuji Takemura, Hiroshi Mori
  • Patent number: 5462008
    Abstract: Semiconductor films of the formula (InP).sub.1-x (TlP.sub.3).sub.x on InP substrates which cover the bandgap of 2-12 .mu.m for use with long wavelength infrared detector and laser applications are disclosed.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: October 31, 1995
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5453153
    Abstract: An improved method of zone-melting recrystallizing of a silicon film on an insulator in which the film is implanted and annealed to achieve a reduction of the density of defects within the film.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: September 26, 1995
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu, Ngwe K. Cheong
  • Patent number: 5411723
    Abstract: A process is disclosed for treating a crystal of MTiOXO.sub.4 which has crystal structure deficiencies of M and O, wherein M is selected from the group consisting of K, Rb, Tl and NH.sub.4 and mixtures thereof and X is selected from the group consisting of P, As and mixtures thereof, which includes the step of heating said crystal in the presence of a mixture of MTiOXO.sub.4 and at least one inorganic compound of one or more monovalent cations selected from the group consisting of Rb+, K+, Cs+ and Ti+ (said inorganic compound(s) being selected to provide a source of vapor phase monovalent cation and being present in an amount sufficient to provide at least a 0.1 mole % excess of the monovalent cation in relation to the M in the MTiOXO.sub.4 in said mixture) at a temperature of from about 400.degree. C. to 950.degree. C. and a pressure of at least 14 psi, and in the presence of a gaseous source of oxygen for a time sufficient to decrease the optical damage susceptibility of said crystal.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: May 2, 1995
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Patricia A. Morris
  • Patent number: 5403406
    Abstract: A silicon wafer containing oxygen precipitate nucleation centers (or oxygen precipitates) and having a first face, a second face, and a central plane equidistant between the first and second faces. The nucleation centers (or oxygen precipitates) have a non-uniform distribution between the first and second faces with a maximum density of the nucleation centers (or oxygen precipitates) being in a region which is between the first face and the central plane and nearer to the first face than the central plane. The density of the nucleation centers (or oxygen precipitates) increases from the first face to the region of maximum density and decreasing from the region of maximum density to the central plane.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: April 4, 1995
    Assignee: MEMC Electronic Materials, SpA
    Inventors: Robert Falster, Giancarlo Ferrero, Graham Fisher, Massimiliano Olmo, Marco Pagani