Processes Of Growth With A Subsequent Step Of Heat Treating Or Deliberate Controlled Cooling Of The Single-crystal Patents (Class 117/3)
  • Patent number: 11101428
    Abstract: A method of manufacturing a monocrystalline layer, comprises the following successive steps: providing a donor substrate comprising a piezoelectric material of composition ABO3, where A consists of at least one element from among Li, Na, K, H, Ca; and B consists of at least one element from among Nb, Ta, Sb, V; providing a receiver substrate, transferring a layer called the “seed layer” from the donor substrate on to the receiver substrate, such that the seed layer is at the bonding interface, followed by thinning of the donor substrate layer; and growing a monocrystalline layer of composition A?B?O3 on piezoelectric material ABO3 of the seed layer where A? consists of a least one of the following elements Li, Na, K, H; B? consists of a least one of the following elements Nb, Ta, Sb, V; and A? is different from A or B? is different from B.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 24, 2021
    Assignee: SOITEC
    Inventors: Bruno Ghyselen, Jean-Marc Bethoux
  • Patent number: 10698292
    Abstract: An object is to provide, for example, a method for manufacturing an optical wavelength conversion device having a structure that enables efficient formation of crystal regions on the surface of, or inside, an amorphous material. An amorphous main body is intermittently irradiated with a first laser beam for generating a high-density excited electron region inside the main body and a second laser beam for heating the high-density excited electron region, with respective focus regions of the first and second laser beams overlapping each other. During the intermittent irradiation with the first and second laser beams, the relative position of the main body and the overlapping focus region of the first and second laser beams are varied. This enables part of the main body where the overlapping focus region moves to serve as a heat source for forming a crystal region.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 30, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Shigehiro Nagano
  • Patent number: 10634622
    Abstract: A method of identifying a wafer defect region is disclosed. The method includes preparing a sample wafer, forming a primary oxide film on the sample wafer at a temperature of 800° C. to 1000° C., forming a secondary oxide film on the primary oxide film at a temperature of 1000° C. to 1100° C., forming a tertiary oxide film on the secondary oxide film at a temperature of 1100° C. to 1200° C., removing the primary to tertiary oxide films, etching one surface of the sample wafer from which the primary to tertiary oxide films are removed to form haze on one surface of the sample wafer, and identifying a defect region of the sample wafer based on the haze.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 28, 2020
    Assignee: SK SILTRON CO., LTD.
    Inventor: Jae Hyeong Lee
  • Patent number: 10564514
    Abstract: A nonlinear optical crystal of cesium fluorooxoborate, and a method of preparation and use thereof. The crystal has a chemical formula of CsB4O6F and a molecular weight of 291.15. It belongs to an orthorhombic crystal system, with a space group of Pna21, crystal cell parameters of a=7.9241 ?, b=11.3996 ?, c=6.6638 ?, and ?=?=?=90°, and a unit cell volume of 601.95 ?3. A melt method, high temperature solution method, vacuum encapsulation method, hydrothermal method or room temperature solution method is used to grow the crystal of CsB4O6F.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: February 18, 2020
    Assignee: XINJIANG TECHNICAL INSTITUTE OF PHYSICS & CHEMISTRY, CHINESE ACADEMY OF SCIENCES
    Inventors: Shilie Pan, Xuefei Wang, Fangfang Zhang, Ying Wang
  • Patent number: 10513798
    Abstract: A method for determining a defect region of a silicon wafer which is sliced off from a silicon single crystal manufactured by a CZ method, the method including: (1) mirror-surface processing the silicon wafer in such a manner that a haze level of a surface thereof in haze measurement performed by a particle counter which uses a laser having a wavelength of 266 nm becomes 0.06 ppm or less; (2) measuring the number of defects and/or a defect density distribution on the mirror-surface-processed surface of the silicon wafer by using a particle counter capable of measuring defects having a size of 15 nm or less; and (3) determining the defect region of the silicon wafer from the measured number of the defects and/or defect density distribution.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 24, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazuya Tomii, Hiroyasu Kikuchi
  • Patent number: 10246797
    Abstract: A method for manufacturing a silicon carbide single crystal includes: packing a silicon carbide source material into a crucible, the silicon carbide source material having a flowability index of not less than 70 and not more than 100; and sublimating the silicon carbide source material by heating the silicon carbide source material.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 2, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Sho Sasaki, Shin Harada, Tsutomu Hori
  • Patent number: 10202709
    Abstract: A method for manufacturing a silicon carbide single crystal includes: packing a silicon carbide source material into a crucible, the silicon carbide source material having a flowability index of not less than 70 and not more than 100; and sublimating the silicon carbide source material by heating the silicon carbide source material.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 12, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Sho Sasaki, Shin Harada, Tsutomu Hori
  • Patent number: 10199429
    Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10159112
    Abstract: An apparatus, a system and a method are disclosed. An exemplary method includes providing a wafer process chamber and a plurality of radiant heat elements under the wafer process chamber, receiving a wafer holder configured to be used in the wafer process chamber, and processing a wafer located on the wafer holder in the wafer process chamber. The wafer holder includes: a wafer contact portion including an upper surface and a lower surface, an exterior portion including an upper surface and a lower surface, and a tapered region formed in the wafer contact portion.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Patent number: 10138571
    Abstract: The disclosure relates to a method for making semimetal compound of Pt. The semimetal compound is a single crystal material of PtTe2. The method comprises: placing pure Pt and pure Te in a reacting chamber as reacting materials; evacuating the reacting chamber to be vacuum less than 10 Pa; heating the reacting chamber to a first temperature from 600 degree Celsius to 800 degree Celsius and keeping for 24 hours to 100 hours; cooling the reacting chamber to a second temperature from 400 degree Celsius to 500 degree Celsius and keeping for 24 hours to 100 hours at a cooling rate from 1 degree Celsius per hour to 10 degree Celsius per hour to obtain a crystal material of PtTe2; and separating the excessive reacting materials from the crystal material of PtTe2.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 27, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke-Nan Zhang, Ming-Zhe Yan, Shu-Yun Zhou, Yang Wu, Shou-Shan Fan
  • Patent number: 10082687
    Abstract: The present invention relates to an Electro-Optical (E-O) crystal elements, their applications and the processes for the preparation thereof more specifically, the present invention relates to the E-O crystal elements (which can be made from doped or un-doped PMN-PT, PIN-PMN-PT or PZN-PT ferroelectric crystals) showing super-high linear E-O coefficient ?c, e.g., transverse effective linear E-O coefficient ?Tc, more than 1100 pm/V and longitudinal effective linear E-O coefficient ?lc up to 527 pm/V, which results in a very low half-wavelength voltage Vl? below 200V and VT? below about 87V in a wide number of modulation, communication, laser, and industrial uses.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: September 25, 2018
    Inventor: Pengdi Han
  • Patent number: 10038328
    Abstract: A digital temperature control method for power supply integrated circuits (ICs) is disclosed. The method acts on one or more system variables. For each system variable, the method comprises measuring a temperature of a power supply IC; converting the measured temperature to a digitized temperature; comparing the digitized temperature to at least one temperature threshold; selecting a digital control algorithm from a plurality of digital control algorithms and applying the selected digital control algorithm on a controlled system variable associated with the selected digital control algorithm, thereby obtaining a control value; verifying the obtained control value; and applying the verified control value to control the power supply IC to an external device.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 31, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Marco Tonarelli, Andrea Lazzeri
  • Patent number: 9997669
    Abstract: Disclosed herein are a light emitting device and a method of making the same. The light emitting device includes: a substrate including a first lead and a second lead; a light emitting diode disposed over the first lead of the substrate, including a second conductive-type semiconductor layer, an active layer, and a first conductive-type semiconductor layer, and emit near ultraviolet light; and a wavelength conversion unit disposed over the light emitting diode and spaced apart from the light emitting diode, wherein the light emitting structure has semi-polar or non-polar characteristics, the wavelength conversion unit has a multi-layered structure including a first phosphor layer and a second phosphor layer, and the light emitting diode is driven at a current density which is equal to or greater than 350 mA/mm2.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: June 12, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Ik Im, Motonobu Takeya, Chung Hoon Lee, Michael Lim
  • Patent number: 9988741
    Abstract: Provided is a sapphire single crystal heat treatment method comprising the steps of: charging a sapphire single crystal into a chamber; raising the temperature in the chamber to a target temperature by heating the chamber; holding the temperature in the chamber at a constant temperature; and cooling the inside of the chamber to room temperature, wherein the temperature raising step comprises: a first temperature raising step of raising the temperature to a first set temperature at a temperature raising rate of 4° C./min to 5° C./min; and a second temperature raising step of raising the temperature to a second set temperature at a temperature raising rate of 1° C./min or less after the first temperature raising step has been completed. The temperature raising process is executed in a multi-stage, to reduce the temperature raising time and prevent a sapphire single crystal from being affected by heat.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 5, 2018
    Assignee: SAPPHIRE TECHNOLOGY CO., LTD.
    Inventors: Hee Choon Lee, Yi Sik Choi, Sung Hwan Moon, Gye Won Jang, Bok Kee Na
  • Patent number: 9923060
    Abstract: A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 20, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Shrenik Deliwala, James Fiorenza, Donghyun Jin
  • Patent number: 9561615
    Abstract: A polymer opal material comprises a three dimensionally periodic arrangement of core particles in a matrix material and exhibits structural color via Bragg reflection. IN a process for manufacturing such a material, a sandwich structure is provided, of a precursor composite material held between first and second sandwiching layers. A relative shear strain of at least 10% is imposed on the precursor composite material by curling the sandwich structure around a roller. The shear strain is cycled, in order to promote the formation of the three dimensional periodic arrangement.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 7, 2017
    Assignees: CAMBRIDGE ENTERPRISE LIMITED, FRAUNHOFER-GESELLSCHAFT ZUR FORDERGUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Jeremy John Baumberg, David Snoswell, Christopher Finlayson, Qibin Zhao, Gotz Peter Hellmann, Peter Wolfgang Andreas Spahn, Christian Gerhard Schafer
  • Patent number: 9553221
    Abstract: Disclosed is an electromagnetic casting method of polycrystalline silicon which is characterized in that polycrystalline silicon is continuously cast by charging silicon raw materials into a bottomless cold mold, melting the silicon raw materials using electromagnetic induction heating, and pulling down the molten silicon to solidify it, wherein the depth of solid-liquid interface before the start of the final solidification process is decreased by reducing a pull down rate of ingot in a final phase of steady-state casting. By adopting the method, the region of precipitation of foreign substances in the finally solidified portion of ingot can be reduced and cracking generation can be prevented upon production of a polycrystalline silicon as a substrate material for a solar cell.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 24, 2017
    Assignee: SUMCO CORPORATION
    Inventors: Koichi Maegawa, Tomohiro Onizuka, Mitsuo Yoshihara
  • Patent number: 9390905
    Abstract: A method for manufacturing a silicon substrate, including: performing a rapid heat treatment to a silicon substrate with a rapid-heating and rapid-cooling apparatus by maintaining the silicon substrate at a temperature that is higher than 1300° C. and not greater than a silicon melting point for 1 to 60 seconds, the silicon substrate being sliced from a silicon single crystal ingot grown by the Czochralski method; performing a first temperature decrease process down to a temperature in the range of 600 to 800° C. at a temperature decrease rate of 5 to 150° C./sec; and performing a second temperature decrease process in such a manner that a cooling time of X seconds and a temperature decrease rate of Y° C./sec meet Y?0.15X-4.5 when X<100 and meet Y?10 when X?100.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: July 12, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tetsuya Oka, Koji Ebara, Shuji Takahashi
  • Patent number: 9362116
    Abstract: Provided are a method of forming an oxide thin film and an electrical device and thin film transistor using the method. The method includes forming an oxide thin film on a substrate by applying a precursor solution; and performing a thermal treatment process on the substrate under a pressurized atmosphere using a gas at about 100° C. to about 400° C.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 7, 2016
    Assignee: Indystry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Hyun Soo Shin, You Seung Rim
  • Patent number: 9335426
    Abstract: A radiation sensor may include a scintillator, a reflector, and a sensor. The scintillator may be capable of converting non-visible radiation into scintillation light. The reflector may be formed from material of outside surfaces of the scintillator, to reflect the scintillation light. The sensor may be positioned in proximity to the scintillator, to detect the scintillation light from the scintillator. A method of manufacturing a scintillator with an intrinsic reflector may include heating the scintillator in an oxygen-deficient environment at a first temperature for a first predetermined time period, and optionally annealing the scintillator in an oxygenated environment at a second temperature for a second predetermined time period.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 10, 2016
    Assignee: University of Tennessee Research Foundation
    Inventors: Merry Koschan, Mohit Tyagi
  • Patent number: 9234297
    Abstract: Provided are a method for manufacturing a SiC single crystal having high crystal quality and, in particular, extremely low screw dislocation density and a SiC single crystal ingot obtained by the method. In particular, provided is a silicon carbide single crystal substrate that is a substrate cut from a bulk silicon carbide single crystal grown by the Physical Vapior Transport (PVT) method, in which the screw dislocation density is smaller in the peripheral region than in the center region, so that screw dislocations are partially reduced. The method is a method for manufacturing a SiC single crystal by the PVT method using a seed crystal and the ingot is a SiC single crystal ingot obtained by the method. Particularly, the silicon carbide single crystal substrate is a silicon carbide single crystal substrate in which when, by representing the diameter of the substrate as R, a center circle region having a diameter of 0.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 12, 2016
    Assignee: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Shinya Sato, Tatsuo Fujimoto, Hiroshi Tsuge, Masakazu Katsuno
  • Patent number: 9209285
    Abstract: A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature (500 degrees Centigrade) molecular beam epitaxy.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: December 8, 2015
    Assignee: THE OHIO STATE UNIVERSITY
    Inventor: Paul R. Berger
  • Patent number: 9059287
    Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita
  • Patent number: 9011598
    Abstract: The present invention provides methods for fabricating a composite substrate including a supporting substrate and a layer of a binary or ternary material having a crystal form that is non-cubic and semi-polar or non-polar. The methods comprise transferring the layer of a binary or ternary material from a donor substrate to a receiving substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 21, 2015
    Assignee: Soitec
    Inventors: Alice Boussagol, Frédéric Dupont, Bruce Faure
  • Publication number: 20150069298
    Abstract: The scintillator single crystal of the invention comprises a cerium-activated orthosilicate compound represented by the following formula (1). Gd2?(a+x+y+z)LnaLuxCeyLmzSiO5??(1) (In formula (1), Lm represents at least one element selected from among Pr, Tb and Tm, Ln represents at least one element selected from among lanthanoid elements excluding Pr, Tb and Tm, and Sc, and Y, a represents a value of at least 0 and less than 1, x represents a value of greater than 1 and less than 2, y represents a value of greater than 0 and no greater than 0.01, and z represents a value of greater than 0 and no greater than 0.01. The value of a+x+y+z is no greater than 2.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Yasushi Kurata, Tatsuya Usui, Naoaki Shimura
  • Patent number: 8961685
    Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8961920
    Abstract: Embodiments of methods of altering the color of diamonds are disclosed. In an embodiment, a method for altering the color of diamonds includes identifying and selecting a diamond having a suitable nitrogen content, HPHT processing the selected diamond under diamond-stable conditions to alter the color of the selected diamond from a first color to a second color, irradiating the HPHT-processed diamond with an electron source having an energy between about 1 MeV and about 20 MeV so as to alter the color of the selected diamond from the second color to a third color, and annealing the irradiated diamond either under partial vacuum conditions, or under HPHT diamond-stable conditions so as to alter the color from the third color to a fourth color (e.g., pink, red, or purple, depending on the nitrogen content of the selected diamond).
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 24, 2015
    Assignee: US Synthetic Corporation
    Inventor: Louis McConkie Pope, II
  • Patent number: 8945301
    Abstract: A method for producing a diamond material by contacting a fluorinated precursor with a hydrocarbon in a reactor and forming a combination in the absence of a metal catalyst; increasing the pressure of the reactor to a first pressure; heating the combination under pressure to form a material precursor; cooling the material precursor; and forming a diamond material.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 3, 2015
    Assignee: University of Houston System
    Inventors: Valery N. Khabashesku, Valery A. Davydov, Alexandra V. Rakhmanina
  • Patent number: 8940093
    Abstract: A method of controlling an epitaxial growth process in an epitaxial reactor. The method includes optimizing the thermocouple offset parameter for a second run by setting up a modeled output parameter value as a linear function of the actual output parameter value, and a second thermocouple offset parameter value.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Schiekofer, Pietro Foglietti, Robert Maier
  • Patent number: 8920560
    Abstract: A method for manufacturing an epitaxial wafer includes: a step of pulling a single crystal from a boron-doped silicon melt in a chamber based on a Czochralski process; and a step of forming an epitaxial layer on a surface of a silicon wafer sliced from the single crystal. The single crystal is allowed to grow while passed through a temperature region of 800 to 600° C. in the chamber in 250 to 180 minutes during the pulling step. The grown single crystal has an oxygen concentration of 10×1017 to 12×1017 atoms/cm3 and a resistivity of 0.03 to 0.01 ?cm. The silicon wafer is subjected to pre-annealing prior to the step of forming the epitaxial layer on the surface of the silicon wafer, for 10 minutes to 4 hours at a predetermined temperature within a temperature region of 650 to 900° C. in an inert gas atmosphere. The method is to fabricate an epitaxial wafer that has a diameter of 300 mm or more, and that attains a high IG effect, and involves few epitaxial defects.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumco Corporation
    Inventors: Yasuo Koike, Toshiaki Ono, Naoki Ikeda, Tomokazu Katano
  • Patent number: 8916953
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 23, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
  • Patent number: 8864907
    Abstract: A condition of a single crystal manufacturing step subjected to the Czochralski method applying an initial oxygen concentration, a dopant concentration or resistivity, and a heat treatment condition is determined simply and clearly on the basis of the conditions of a wafer manufacturing step and a device step so as to obtain a silicon wafer having a desired gettering capability. A manufacturing method of a silicon substrate which is manufactured from a silicon single crystal grown by the CZ method and provided for manufacturing a solid-state imaging device is provided. The internal state of the silicon substrate, which depends on the initial oxygen concentration, the carbon concentration, the resistivity, and the pulling condition of the silicon substrate, is determined by comparing a white spot condition representing upper and lower limits of the density of white spots as device characteristics with the measured density of white spots.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 21, 2014
    Assignee: Sumco Corporation
    Inventors: Kazunari Kurita, Shuichi Omote
  • Patent number: 8865572
    Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8865571
    Abstract: A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Publication number: 20140305367
    Abstract: The passivation of a nonlinear optical crystal for use in an inspection tool includes growing a nonlinear optical crystal in the presence of at least one of fluorine, a fluoride ion and a fluoride-containing compound, mechanically preparing the nonlinear optical crystal, performing an annealing process on the nonlinear optical crystal and exposing the nonlinear optical crystal to a hydrogen-containing or deuterium-containing passivating gas.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 16, 2014
    Applicant: KLA-Tencor Corporation
    Inventors: Yung-Ho Alex Chuang, Vladimir Dribinski
  • Publication number: 20140308590
    Abstract: Provided is a solid electrolyte including an epitaxial thin film crystal made of an electrolyte containing at least lithium.
    Type: Application
    Filed: November 5, 2012
    Publication date: October 16, 2014
    Applicant: Sony Corporation
    Inventors: Hiromichi Ohta, Noriyuki Aoki
  • Patent number: 8828138
    Abstract: A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Christopher D'Emic, Hongbo Peng, Sufi Zafar
  • Patent number: 8758505
    Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: June 24, 2014
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
  • Publication number: 20140137793
    Abstract: A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.
    Type: Application
    Filed: June 22, 2012
    Publication date: May 22, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Seok Min Kang, Moo Seong Kim
  • Patent number: 8728232
    Abstract: A single crystal heat treatment method having a step of heating a single crystal of a specific cerium-doped silicate compound in an oxygen-poor atmosphere at a temperature T1 (units: ° C.) that satisfies the conditions represented by formula (3) below 800?T1<(Tm1?550)??(3) (wherein Tm1 (units: ° C.) represents the melting point of the single crystal).
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: May 20, 2014
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Tatsuya Usui, Naoaki Shimura, Yasushi Kurata, Kazuhisa Kurashige
  • Publication number: 20140134491
    Abstract: Provided is a lithium containing composite oxide powder suitable for the positive electrode active material of the non-aqueous electrolysis solution secondary battery such as the lithium ion secondary battery, and a manufacturing process for the same. A lithium containing composite oxide powder includes a single crystal particle containing a lithium containing composite oxide that is manufactured by a molten salt method and that includes at least lithium and another one or more metal elements and in which a crystal structure belongs to a lamellar rock salt structure, wherein an average primary particle diameter is greater than or equal to 200 nm and smaller than or equal to 30 ?m. The lithium containing composite oxide powder is grown by reacting the metal containing ingredient in the molten salt of the lithium hydroxide at a reaction temperature of higher than or equal to 650° C. and lower than or equal to 900° C.
    Type: Application
    Filed: June 22, 2012
    Publication date: May 15, 2014
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yuki Sugimoto, Naoto Yasuda, Fumiya Kanetake, Hideaki Shinoda, Manabu Miyoshi, Kyoichi Kinoshita, Toru Abe
  • Publication number: 20140116323
    Abstract: A method and apparatus for the production of C-plane single crystal sapphire is disclosed. The method and apparatus may use edge defined film-fed growth techniques for the production of single crystal material exhibiting low polycrystallinity and/or low dislocation density.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: Saint-Gobain Ceramics & Plastics, Inc.
    Inventors: Vitali Tatartchenko, Christopher D. Jones, Stephen Anthony Zanella, John Walter Locher, Fery Pranadi
  • Publication number: 20140117513
    Abstract: Technologies are described effective to implement systems and methods of producing a material. The methods comprise receiving a tertiary semiconductor sample with a dilute species. The sample has two ends. The first end of the sample includes a first concentration of the dilute species lower than a second concentration of the dilute species in the second end of the sample. The method further comprises heating the sample in a chamber. The chamber has a first zone and a second zone. The first zone having a first temperature higher than a second temperature in the second zone. The sample is orientated such that the first end is in the first zone and the second end is in the second zone.
    Type: Application
    Filed: October 25, 2013
    Publication date: May 1, 2014
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Ralph B. James, Giuseppe Camarda, Aleksey E. Bolotnikov, Ryan Tappero, Yonggang Cui, Anwar Hosaain, Yang Ge, Kihyun Kim
  • Publication number: 20140093671
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104cm?3.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 3, 2014
    Inventors: Robert Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Publication number: 20140044945
    Abstract: The invention relates to a semiconductor wafer of monocrystalline silicon, and to a method for producing it. The semiconductor wafer has a zone, DZ, which is free of BMD defects and extends from a front side of the semiconductor wafer into the bulk of the semiconductor wafer, and a region having BMD defects which extends from the DZ further into the bulk of the semiconductor wafer. A silicon single crystal is pulled by the Czochralski method and processed to form a polished monocrystalline silicon substrate wafer. The substrate wafer is treated by rapidly heating and cooling the substrate wafer, slowly heating the rapidly heated and cooled substrate wafer, and keeping the substrate wafer at a specific temperature and over a specific period.
    Type: Application
    Filed: July 24, 2013
    Publication date: February 13, 2014
    Applicant: Siltronic AG
    Inventors: Timo Mueller, Gudrun Kissinger, Dawid Kot, Andreas Sattler
  • Publication number: 20130313478
    Abstract: The present invention relates generally to the field of synthetic crystal, and more particularly, this invention relates to doped low-temperature phase barium metaborate single crystal, growth method and frequency-converter. Molten salt method was adopted. The single crystal completely overcome the shortcomings of BBO with strong deliquescence, almost no deliquescence; its frequency doubling effect and optical damage threshold has improved greatly compared with the BBO; its hardness increased significantly, the single crystal with Shore hardness of 101.3 and Mohs hardness of 6, however, BBO with Shore hardness of 71.2 and Mohs hardness of 4. From the UV-Vis region transmittance curves tests, the cut-off wavelength of the single crystal is 190 nm, wavelength of absorption onset is 205 nm. BBSAG is widely applied in the fields of laser and nonlinear optics, and in terms of frequency-converter of ultraviolet and deep-ultraviolet due to its excellent properties better than BBO.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 28, 2013
    Applicant: FUJIAN INSTITUTE OF RESEARCH ON THE STRUCTURE OF MATTER, CHINESE ACADEMY OF SCIENCES
    Inventor: FUJIAN INSTITUTE OF RESEARCH ON THE STRUCTURE OF MATTER, CHINESE ACADEMY OF SCIENCES
  • Patent number: 8580031
    Abstract: A method of producing a three-dimensional photonic crystal by laminating a layer having a periodic structure, the method including the steps of forming a first structure and a second structure each including the layer having the periodic structure; and bonding a first bonding layer of the first structure and a second bonding layer of the second structure. The first bonding layer is one layer obtained by dividing a layer constituting the three-dimensional photonic crystal at a cross section perpendicular to a lamination direction, and the second bonding layer is the other layer obtained by dividing the layer constituting the three-dimensional photonic crystal at the cross section perpendicular to the lamination direction.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 12, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aihiko Numata, Hikaru Hoshi, Kenji Tamamori
  • Patent number: 8574361
    Abstract: A method for producing a high-quality group-III element nitride crystal at a high crystal growth rate, and a group-III element nitride crystal are provided. The method includes the steps of placing a group-III element, an alkali metal, and a seed crystal of group-III element nitride in a crystal growth vessel, pressurizing and heating the crystal growth vessel in an atmosphere of nitrogen-containing gas, and causing the group-III element and nitrogen to react with each other in a melt of the group-III element, the alkali metal and the nitrogen so that a group-III element nitride crystal is grown using the seed crystal as a nucleus. A hydrocarbon having a boiling point higher than the melting point of the alkali metal is added before the pressurization and heating of the crystal growth vessel.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 5, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Osamu Yamada, Hisashi Minemoto, Kouichi Hiranaka, Takeshi Hatakeyama, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Yasuo Kitaoka
  • Publication number: 20130266809
    Abstract: A biotemplated nanomaterial can include a crystalline perovskite.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 10, 2013
    Applicant: Massachusetts Institute of Technology
    Inventors: Nuerxiati Nueraji, Angela M. Belcher
  • Patent number: RE45238
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai