Non-planar Crystal Grown (e.g., Elo) Patents (Class 117/45)
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Patent number: 11521989Abstract: A display substrate, a display apparatus, and a manufacturing method of the display substrate are provided. The display substrate includes: a base substrate; and a crystallization induction layer and a polysilicon layer stacked on the base substrate. The crystallization induction layer includes induction layer patterns and intervals between the induction layer patterns. The polysilicon layer includes a portion overlapping the induction layer patterns and a portion overlapping the intervals, a crystallinity of the portion of the polysilicon layer overlapping the induction layer patterns is larger than a crystallinity of the portion of the polysilicon layer overlapping the intervals.Type: GrantFiled: April 30, 2019Date of Patent: December 6, 2022Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.Inventor: Feng Guan
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Patent number: 8840722Abstract: Implementations and techniques for producing graphene are generally disclosed.Type: GrantFiled: July 19, 2013Date of Patent: September 23, 2014Assignee: Empire Technology Development LLCInventor: James Pierre Hauck
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Patent number: 8506705Abstract: A nitride single crystal is produced on a seed crystal substrate 5 in a melt containing a flux and a raw material of the single crystal in a growing vessel 1. The melt 2 in the growing vessel 1 has temperature gradient in a horizontal direction. In growing a nitride single crystal by flux method, adhesion of inferior crystals onto the single crystal is prevented and the film thickness of the single crystal is made constant.Type: GrantFiled: September 9, 2009Date of Patent: August 13, 2013Assignee: NGK Insulators, Ltd.Inventors: Mikiya Ichimura, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Yasuo Kitaoka
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Patent number: 8293009Abstract: A pressure differential is applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted almost exclusively through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet must allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.Type: GrantFiled: November 17, 2011Date of Patent: October 23, 2012Assignee: 1366 Technologies Inc.Inventors: Emanuel M. Sachs, Richard L. Wallace, Eerik T. Hantsoo, Adam M. Lorenz, G. D. Stephen Hudelson, Ralf Jonczyk
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Patent number: 8038794Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.Type: GrantFiled: April 15, 2005Date of Patent: October 18, 2011Assignees: Sumitomo Electric Industries, Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Patent number: 7875115Abstract: This disclosure is aimed at providing a method for producing an epitaxial wafer allowing uniform occurrence of oxygen precipitate in a substrate plane in the radial direction in a base plate and excelling in the crystal quality of an epi-layer. A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the production of silicon single crystal in a range in which the whole surface of substrate becomes an OSF region, and being pulled at a cooling speed of not less than 4° C./minute between 1100 and 1000° C. during the growth of crystal, and depositing the silicon single crystal layer on the surface of the substrate by the epitaxial method.Type: GrantFiled: January 12, 2007Date of Patent: January 25, 2011Assignee: Siltronic AGInventors: Katsuhiko Nakai, Koji Fukuhara
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Patent number: 7828895Abstract: The invention relates to a method of producing an optical element using a garnet single crystal for the purpose of providing an optical element with a reduced Pb content or from which Pb can preliminarily be removed completely. By growing a garnet single crystal by using a solution containing Na, Bi and B by the LPE process and thermally treating the garnet single crystal in reducing atmosphere prepared by using nitrogen gas and/or hydrogen gas, the resulting thermally treated garnet single crystal is used to prepare an optical element.Type: GrantFiled: January 19, 2007Date of Patent: November 9, 2010Assignee: TDK CorporationInventor: Atsushi Ohido
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Patent number: 7645337Abstract: In accordance with one aspect, the present invention provides a method for providing polycrystalline films having a controlled microstructure as well as a crystallographic texture. The methods provide elongated grains or single-crystal islands of a specified crystallographic orientation. In particular, a method of processing a film on a substrate includes generating a textured film having crystal grains oriented predominantly in one preferred crystallographic orientation; and then generating a microstructure using sequential lateral solidification crystallization that provides a location-controlled growth of the grains orientated in the preferred crystallographic orientation.Type: GrantFiled: November 18, 2004Date of Patent: January 12, 2010Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul Christian van der Wilt
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Patent number: 7591897Abstract: A process for the rapid synthesis of metal oxide nanoparticles at low temperatures and methods which facilitate the fabrication of long metal oxide nanowires. The method is based on treatment of metals with oxygen plasma. Using oxygen plasma at low temperatures allows for rapid growth unlike other synthesis methods where nanomaterials take a long time to grow. Density of neutral oxygen atoms in plasma is a controlling factor for the yield of nanowires. The oxygen atom density window differs for different materials. By selecting the optimal oxygen atom density for various materials the yield can be maximized for nanowire synthesis of the metal.Type: GrantFiled: March 20, 2006Date of Patent: September 22, 2009Assignee: University of Louisville Research Foundation, Inc.Inventors: Mahendra Kumar Sunkara, Sreeram Vaddiraju, Miran Mozetic, Uros Cvelbar
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Patent number: 7445671Abstract: A method of producing networks of low melting metal oxides such as crystalline gallium oxide comprised of one-dimensional nanostructures. Because of the unique arrangement of wires, these crystalline networks defined as “nanowebs”, “nanowire networks”, and/or “two-dimensional nanowires”. Nanowebs contain wire densities on the order of 109/cm2. A possible mechanism for the fast self-assembly of crystalline metal oxide nanowires involves multiple nucleation and coalescence via oxidation-reduction reactions at the molecular level. The preferential growth of nanowires parallel to the substrate enables them to coalesce into regular polygonal networks. The individual segments of the polygonal network consist of both nanowires and nanotubules of ?-gallium oxide. The synthesis of highly crystalline noncatalytic low melting metals such as ?-gallium oxide tubes, nanowires, and nanopaintbrushes is accomplished using molten gallium and microwave plasma containing a mixture of monoatomic oxygen and hydrogen.Type: GrantFiled: June 16, 2004Date of Patent: November 4, 2008Assignees: University of Louisville, University of KentuckyInventors: Mahendra Kumar Sunkara, Shashank Sharma, Burtron H. Davis, Uschi M. Graham
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Patent number: 7431766Abstract: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, mechanical devices. Processing is laser-performed in relation to a selected material whose internal crystalline structure becomes appropriately changed thereby to establish the desired mechanical properties for a created device.Type: GrantFiled: September 14, 2005Date of Patent: October 7, 2008Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7422632Abstract: The features with size at least in one direction 1 ?m growth method was developed by modifying liquid phase epitaxy. Number of processes was developed where duration and amplitude of the cooling pulse at the substrate interface were chosen in order to form low-dimensional features before system return to the equilibrium condition. This method allows obtaining low-dimensional features with observed quantum effect such as quantum layers, dots and superlattices. The shape of the features strongly depends on substrate orientation, stress and growth conditions.Type: GrantFiled: June 7, 2006Date of Patent: September 9, 2008Inventors: Ihor Evgenievich Maronchuk, Tamara Fatyhovna Kulyutkina, Aleksander Igorevich Maronchuk, Maria Vladimirovna Naidenkova
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Patent number: 7384476Abstract: A method for crystallizing silicon is provided. The method includes: forming an amorphous silicon layer on a substrate; aligning a mask above the substrate, the mask being divided into a plurality of blocks, each block having at least two transmission patterns, the transmission patterns of one block and the transmission patterns of another adjacent block being complimentary with each other and the mask including at least two diffraction patterns disposed between the transmission patterns; forming a first crystallization region on the amorphous silicon layer by irradiating a laser beam through the transmission patterns of the mask; and displacing the substrate or the mask by a predetermined distance and irradiating a laser beam onto the substrate to recrystallize the crystallization region using the laser beam that passes through the diffraction patterns, and forming a second crystallization region using the laser beam that passes through the transmission patterns.Type: GrantFiled: May 24, 2004Date of Patent: June 10, 2008Assignee: LG Display Co., Ltd.Inventor: JaeSung You
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Patent number: 7326294Abstract: Small crystals are made by mixing a solution of a desired substance with an anti-solvent in a fluidic vortex mixer in which the residence time is less than 1s, for example 10 ms. The liquid within the fluidic vortex mixer (12) is subjected to high intensity ultrasound from a transducer (20, 22). The solution very rapidly becomes supersaturated, and the ultrasound can induce a very large number of nuclei for crystal growth. Small crystals, for example less than 5 ?m, are formed. The resulting suspension is treated so as to add or remove ingredients, and then spray dried using an atomizer tuned to create small droplets in such a way that each droplet should contain not more than one crystal. Crystal agglomeration is hence prevented.Type: GrantFiled: April 8, 2003Date of Patent: February 5, 2008Assignee: Accentus PLCInventors: Linda Jane McCausland, David Reay
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Publication number: 20070277728Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.Type: ApplicationFiled: May 30, 2006Publication date: December 6, 2007Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
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Patent number: 7300518Abstract: The invention provides an apparatus for producing a single crystal, and a method for producing a silicon single crystal using the same. An apparatus for producing a single crystal includes a heating device which heats polycrystalline silicon raw material held in a crucible to form silicon melt, and a pulling up device which grows a silicon single crystal while pulling it up from the silicon melt accompanied with rotation. By providing the apparatus with a magnetic field generation unit which applies to the silicon melt a cusp magnetic field a shape of neutral plane of which is symmetric around the rotation axis of the silicon single crystal and is curved in the upward direction, various conditions for producing a silicon single crystal having a defect free region is relaxed, and a silicon single crystal having a defect free region is produced at high efficiency.Type: GrantFiled: May 18, 2005Date of Patent: November 27, 2007Assignee: Sumco CorporationInventors: Norihito Fukatsu, Kazuyuki Egashira, Senrin Fu
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Patent number: 7288152Abstract: The present invention provides a manufacturing method in which high quality GaN crystals and GaN crystal substrates can be manufactured under mild conditions of low pressure and low temperature. In a method of manufacturing GaN crystals in which in a gas atmosphere containing nitrogen, gallium and the nitrogen are allowed to react with each other to generate GaN crystals in a mixed melt of the gallium and sodium, the gallium and the nitrogen are allowed to react with each other under a pressurizing condition that exceeds atmospheric pressure, and pressure P1 (atm(×1.013×105 Pa)) of the pressurizing condition is set so as to satisfy the condition that is expressed by the following conditional expression (I): P?P1<(P+45),??(I) where in the expression (I), P (atm(×1.013×105 Pa)) denotes the minimum pressure that is required for generating GaN crystals at a temperature T° C. of the mixed melt.Type: GrantFiled: July 2, 2004Date of Patent: October 30, 2007Assignees: Matsushita Electric Industrial Co., Ltd., Yusuke MORIInventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Masanori Morishita
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Patent number: 7223305Abstract: A method of manufacturing a potassium niobate (KNbO3) single crystal thin film, includes the steps of maintaining the substrate under a predetermined oxygen partial pressure; maintaining the substrate within a temperature region which is equal to or higher than an eutectic temperature of KNbO3 and 3K2O.Nb2O5 and is equal to or lower than complete melting temperature of KNbO3 and 3K2O.Nb2O5 so that a solid phase of KNbO3 and a liquid phase can coexist on the substrate; depositing a vapor phase material on the substrate in a state in which a solid phase and a liquid phase coexist; and precipitating KNbO3 on the substrate from the liquid phase as a solid phase to grow a KNbO3 single crystal thin film. The composition of a starting material to be vaporized to generate the vapor phase material is from K2O.Nb2O5=50:50 to K2O.Nb2O5=65:35.Type: GrantFiled: January 20, 2004Date of Patent: May 29, 2007Assignee: Seiko Epson CorporationInventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa
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Patent number: 7192481Abstract: A radiation detector made from a compound, or alloy, comprising CdxZn1?xTe (0=x=1), Pb in a concentration between 10 and 10,000 atomic parts per billion and at least one element selected from the group consisting of (i) Cl and (ii) elements in column III of the periodic table in a concentration between 10 and 10,000 atomic parts per billion. The radiation detector exhibits full electrical compensation, high-resistivity, full depletion under an applied electrical bias and excellent charge transport.Type: GrantFiled: June 10, 2003Date of Patent: March 20, 2007Assignee: II-VI IncorporatedInventors: Csaba Szeles, Kelvin G. Lynn
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Patent number: 7153359Abstract: A crystalline semiconductor film, the crystalline semiconductor film being formed over an insulative substrate, and including semiconductor crystal grains laterally grown along a surface of the insulative substrate, wherein the laterally-grown semiconductor crystal grains are in contact with each other at grain boundaries, and a distance between adjacent grain boundaries is equal to or smaller than two times a lateral growth distance of the semiconductor crystal grains.Type: GrantFiled: September 25, 2002Date of Patent: December 26, 2006Assignee: Sharp Kabushiki KaishaInventors: Masashi Maekawa, Keiichi Fukuyama, Michinori Iwai, Kohei Tanaka
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Patent number: 7135070Abstract: Monolithic stacked/layered room-temperature-processed materials whose internal crystalline structures are laser modification to create arrays of mechanical, and combined mechanical and electrical, devices with precision-established properties, such as important mechanical properties. Methodology and system configurations are disclosed.Type: GrantFiled: April 23, 2002Date of Patent: November 14, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7128783Abstract: Thin-film laser-effected internal crystalline structure modified materials suitable for the creation of various small-dimension mechanical devices, either singly or in monolithic arrays, such as MEMS devices. Processing is carried out at room temperature and atmospheric pressure.Type: GrantFiled: April 23, 2002Date of Patent: October 31, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7125451Abstract: Laser processing of various materials to create mechanical devices whose internal mechanical properties are provided in final useable form by adjustments made in internal crystalline structure.Type: GrantFiled: April 23, 2002Date of Patent: October 24, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7105048Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.Type: GrantFiled: November 27, 2002Date of Patent: September 12, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
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Patent number: 6860939Abstract: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure becomes appropriately changed to establish the desired mechanical properties for a created device.Type: GrantFiled: April 23, 2002Date of Patent: March 1, 2005Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 6113685Abstract: An improved method for growing a first layer on a second layer in which the first and second layers have different thermal indices of expansion and/or a mismatch of the lattice constants and the deposition being carried out at a temperature above ambient. The first layer includes a material that decomposes upon beating above a decomposition temperature. One of the first and second layers absorbs light in a first frequency range and the other of the first and second layers is transparent to the light in the first frequency range. In the method of the present invention, the one of the first and second layers that absorbs light in the first frequency range is exposed to light in the first frequency range by passing the light through the other of the first and second layers. This exposure heats the first layer to a temperature above the decomposition temperature at the interface of the first and second layers after the first layer has been deposited on the second layer.Type: GrantFiled: September 14, 1998Date of Patent: September 5, 2000Assignee: Hewlett-Packard CompanyInventors: Shih-Yuan Wang, Yong Chen
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Patent number: 5893948Abstract: The invention provides a method for forming a plurality of single silicon crystals over a substrate. The method forms a plurality of nucleation sites over the substrate. An amorphous silicon layer is formed over the substrate covering the plurality of silicon nucleation sites. The amorphous silicon layer is melted by using a laser beam and then crystallized to form the plurality of single silicon crystals. Each of the plurality of single silicon crystals correspond to one of the plurality of nucleation sites.Type: GrantFiled: April 5, 1996Date of Patent: April 13, 1999Assignee: Xerox CorporationInventors: Norbert H. Nickel, Gregory B. Anderson, Steven E. Ready, James B. Boyce, Ping Mei
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Patent number: 5741359Abstract: An apparatus for zone-melting recrystallization of a semiconductor layer includes a first heater, on which a semiconductor wafer including the semiconductor layer and upper and lower insulating films sandwiching the semiconductor layer is mounted, for radiantly heating a rear surface of the semiconductor wafer to a temperature at which the semiconductor layer and the insulating layers are not melted; and a second heater disposed above the semiconductor wafer and radiantly heating a front surface of the semiconductor wafer. The second heater has a heat generating point that produces a heated spot in the semiconductor layer and moves spirally while maintaining a fixed distance from the semiconductor wafer, thereby producing a large-area monocrystalline region in the semiconductor layer. In this zone-melting recrystallization, a single crystalline nucleus is produced in the semiconductor layer, and the entire semiconductor layer is recrystallized with the crystalline nucleus as a seed crystal.Type: GrantFiled: September 7, 1995Date of Patent: April 21, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Motoda, Manabu Kato
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Patent number: 5733641Abstract: The invention provides a buffered substrate that includes a substrate, a buffer layer and a silicon layer. The buffer layer is disposed between the substrate and the silicon layer. The buffer layer has a melting point higher than a melting point of the substrate. A polycrystalline silicon layer is formed by crystallizing the silicon layer using a laser beam.Type: GrantFiled: May 31, 1996Date of Patent: March 31, 1998Assignee: Xerox CorporationInventors: David K. Fork, James B. Boyce, Ping Mei, Steve Ready, Richard I. Johnson, Greg B. Anderson
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Patent number: 5549747Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: April 14, 1994Date of Patent: August 27, 1996Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
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Patent number: 5467731Abstract: A method for producing a semiconductor structure including a semiconductor film formed on a semiconductor substrate body via an insulating film includes: laminating a first insulating film, a first semiconductor film, and a second insulating film on the semiconductor substrate successively; forming stripe-shaped second semiconductor films of predetermined width on the second insulating film arranged periodically at a predetermined interval and covering these second semiconductor films with a third insulating film; performing zone melting recrystallization of the first semiconductor film from one end of the substrate to the opposite end along the stripe direction of the stripe-shaped second semiconductor film; etching the third insulating film and portions of the second insulating film not sandwiched by the first and second semiconductor films; oxidizing portions of the second semiconductor film and the first semiconductor film exposed in the etching step and etching and removing the second insulating film remType: GrantFiled: October 13, 1994Date of Patent: November 21, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Arimoto, Norio Hayafuji, Mikio Deguchi, Satoshi Hamamoto
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Patent number: 5431126Abstract: A thin semiconductor film having at least one an edge is formed on a base whose material is different from the material of the thin semiconductor film. A laser beam, for example, is applied to the semiconductor film thereby to melt the semiconductor film including the edge for thereby beading the edge upwardly. The melted semiconductor film including the edge is solidified and hence recrystallized into a semiconductor crystal. A plurality of spaced reflecting films may be formed on the thin semiconductor film before the laser beam is applied. Various semiconductor devices including a thin-film transistor, a solar cell, and a bipolar transistor may be fabricated of the semiconductor crystal.Type: GrantFiled: June 22, 1993Date of Patent: July 11, 1995Assignee: Sony CorporationInventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Gosain D. Pal, Atsushi Kono, Jonathan Westwater, Setsuo Usui
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Patent number: 5417180Abstract: An epitaxially grown layer having a large area and an uniform thickness is formed on an insulating layer. The surface of a silicon substrate (2) is oxidized to form a silicon dioxide layer (4) acting as insulating layer. The silicon dioxide layer (4) is then provided with an opening (10) by etching with the aid of resist (6). After removing the resist (6), a silicon seed crystal layer (11) is selectively grown in the opening (10). Next, the silicon dioxide layer (4) is subjected to etchback using hydrofluoric acid, so that the side face (14) of the seed crystal layer (11) is emerged. The following epitaxial growth on the basis of the seed crystal layer (11) is allowed sufficient growth in the lateral direction. As a result, an epitaxially grown layer having (16) a large area and an uniform thickness is realized.Type: GrantFiled: July 29, 1993Date of Patent: May 23, 1995Assignee: Rohm Co., Ltd.Inventor: Tomofumi Nakamura
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Patent number: 5409867Abstract: After partially crystallizing an amorphous semiconductor deposited on a substrate, the irradition of infrared ray is conducted to grow a polycrystalline semiconductor layer on the crystallized region and the amorphous region by thermal decomposition while the temperature of the crystallized region is kept higher than that of the amorphous region. Since the polycystalline layer is formed of polycystalline grains grown from nuclei of the cystallized region, the crystal grain thereof is large.Type: GrantFiled: June 15, 1994Date of Patent: April 25, 1995Assignee: Fuji Electric Co., Ltd.Inventor: Akihiko Asano