With Pretreatment Of Epitaxy Substrate (e.g., Autodoping Control, Cleaning, Polishing, Leveling, Masking) Patents (Class 117/58)
  • Patent number: 11103960
    Abstract: This invention provides two variations of methods of separating a surface layer of the semiconductor crystal. In the second variation of the method, pulse laser emission is generated; a focused laser beam is directed onto the crystal in such a way that focus is placed in the layer separation plane perpendicular the axis of the beam, a laser beam is moved in such a way that focus is moved in the layer separation plane with forming the non-overlapping local regions with a disturbed topology of the crystal structure and with reduced interatomic bonds, wherein the local regions is distributed over the whole plane, an external action disturbing the reduced interatomic bonds is applied to the separable layer. The invention allows separating flat lateral surface layers from semiconductor crystals, and thin semiconductor washes from cylindrical semiconductor boules.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 31, 2021
    Inventors: Yury Georgievich Shreter, Yury Toomasovich Rebane, Aleksey Vladimirovich Mironov
  • Patent number: 10828727
    Abstract: This invention provides two variations of methods of separating a surface layer of the semiconductor crystal. In the first variation of the method, a focused laser beam is directed onto the crystal in such a way that focus is placed in the layer separation plane perpendicular to the axis of the beam, the laser beam is moved with scanning the layer separation plane with focus in the direction from the open side surface of the crystal deep into the crystal with forming a continuous slit width of which is increased with every pass of the laser beam, the previous operation is performed up to separation of the surface layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 10, 2020
    Inventors: Yury Georgievich Shreter, Yury Toomasovich Rebane, Aleksey Vladimirovich Mironov
  • Patent number: 10199518
    Abstract: A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: February 5, 2019
    Assignee: Solar-Tectic LLC
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 10199529
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on flexible substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films are nearly to entirely free of metal impurities and have widespread application in the manufacture and benefit of photovoltaic and display technologies.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 5, 2019
    Assignee: Solar-Tectic, LLC
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 10056519
    Abstract: A method is provided for depositing textured wide bandgap materials, such as polymers or perovskites, on a textured transparent conducting oxide on inorganic thin-film, which serves as a recombination layer, or interfacial conducting layer (ICL), for tandem or multi junction solar cells.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 21, 2018
    Assignee: Solar-Tectic, LLC
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 9722130
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 1, 2017
    Assignee: Solar-Tectic LLC
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 9460908
    Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 4, 2016
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 9214379
    Abstract: A bonded SOS substrate having a semiconductor film on or above a surface of a sapphire substrate is obtained by a method with the steps of implanting ions from a surface of a semiconductor substrate to form an ion-implanted layer; activating at least a surface from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to form a bonded body; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate for embrittling an interface of the ion-implanted layer, while keeping the bonded body at a temperature higher than the temperature at which the surfaces of the semiconductor substrate and the sapphire substrate were bonded.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 15, 2015
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Atsuo Ito, Yuji Tobisaka, Makoto Kawai
  • Patent number: 9214380
    Abstract: Method of making a bonded SOS substrate with a semiconductor film on or above a sapphire substrate by implanting ions from a surface of the semiconductor substrate to form an ion-implanted layer; activating at least a surface of one of the sapphire substrate and the semiconductor substrate from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature of from 200° C. to 350° C.; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate to make the interface of the ion-implanted layer brittle at a temperature of the bonded body higher than the temperature at which the surfaces were bonded, to transfer the semiconductor film to the sapphire substrate.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 15, 2015
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Atsuo Ito, Yuji Tobisaka, Makoto Kawai
  • Patent number: 9054249
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 9, 2015
    Assignee: Solar—Tectic LLC
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Publication number: 20150064915
    Abstract: A method is disclosed for forming a row of mutually spaced lithography features on a substrate, such as contact electrodes for a NAND device. The method involves forming and/or using a narrow slot over the substrate defined between the edge of a hard mask layer and a side wall of a trench in a resist layer overlying the edge and the substrate. A self-assemblable block copolymer is deposited and ordered in the trench for use as a further resist for patterning the substrate along the slot. The method allows for a sub-resolution contact array to be formed using UV lithography by overlapping the trench with the hard mask edge to provide the narrow slot in which the contact electrodes may be formed.
    Type: Application
    Filed: March 19, 2013
    Publication date: March 5, 2015
    Applicant: ASML Netherlands B.V.
    Inventor: Sander Frederik Wuister
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8940095
    Abstract: An apparatus for growth of uniform multi-component single crystals is provided. The single crystal material has at least three elements and has a diameter of at least 50 mm, a dislocation density of less than 100 cm?2 and a radial compositional variation of less than 1%.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: January 27, 2015
    Assignee: Rensselaer Polytechnic Institute
    Inventor: Partha Dutta
  • Publication number: 20150024223
    Abstract: The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template laye
    Type: Application
    Filed: April 6, 2012
    Publication date: January 22, 2015
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY
    Inventor: Shumin Wang
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Publication number: 20150017466
    Abstract: A self-aligned tunable metamaterial is formed as a wire mesh. Self-aligned channel grids are formed in layers in a silicon substrate using deep trench formation and a high-temperature anneal. Vertical wells at the channels may also be etched. This may result in a three-dimensional mesh grid of metal and other material. In another embodiment, metallic beads are deposited at each intersection of the mesh grid, the grid is encased in a rigid medium, and the mesh grid is removed to form an artificial nanocrystal.
    Type: Application
    Filed: March 11, 2013
    Publication date: January 15, 2015
    Inventors: Arturo A. Ayon, Ramakrishna Kotha, Diana Strickland
  • Publication number: 20140360426
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 11, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20140328742
    Abstract: The present invention provides a method for producing a Group III nitride crystal, capable of producing a Group III nitride crystal in a large size with few defects and high quality.
    Type: Application
    Filed: January 10, 2013
    Publication date: November 6, 2014
    Inventors: Yusuke Mori, Mamoru Imade, Masashi Yoshimura, Mihoko Hirao, Masayuki Imanishi
  • Patent number: 8877542
    Abstract: Disclosed are a nanostructure array substrate, a method for fabricating the same, and a dye-sensitized solar cell by using the same. The nanostructure array substrate includes a plurality of metal oxide nanostructures vertically aligned on the substrate while being separated from each other. The metal oxide nanostructures include nanorods having a ZnO core/TiO2 shell structure or TiO2 nanotubes. The method includes the steps of forming ZnO nanorods vertically aligned from a seed layer formed on a substrate; and coating a TiO2 sol on the ZnO nanorods and sintering the ZnO nanorods to form nanorods having a ZnO core/TiO2 shell structure. The transparency and flexibility of the substrate are ensured. The photoelectric conversion efficiency of the solar cell is improved if the nanostructure array substrate is employed in the photo electrode of the dye-sensitized solar cell.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Gun Young Jung, Hui Song, Ki Seok Kim
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Publication number: 20140158041
    Abstract: The invention concerns a method for fabricating a substrate in semiconductor material characterized in that it comprises the steps of: starting from a donor substrate in a first semiconductor material at an initial temperature, contacting a surface of the donor substrate with a bath of a second semiconductor material held in the liquid state at a temperature higher than the initial temperature, the second semiconductor material being chosen so that its melting point is equal to or lower than the melting point of the first semiconductor material, solidifying the bath material on the surface to thicken the donor substrate with a solidified layer. The invention also concerns a device for implementing the method.
    Type: Application
    Filed: July 25, 2012
    Publication date: June 12, 2014
    Applicant: SOITEC
    Inventor: Michel Bruel
  • Publication number: 20140137794
    Abstract: A method of preparing a directional solidification system (DSS) furnace for use in semiconductor or solar manufacturing includes slicing a plurality of cylindrical rods to produce a plurality of rectangular seed bricks, a plurality of corner portions, and a plurality of quarter sections, and cropping the plurality of rectangular seed bricks into a plurality of rectangular seeds.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)
    Inventors: Dale A. Witte, Jihong John Chen, Travis Hambach, Linda Swiney
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20140048013
    Abstract: Zinc oxide layer, including pure zinc oxide and doped zinc oxide, can be deposited with preferred crystal orientation and improved electrical conductivity by employing a seed layer comprising a metallic element. By selecting metallic elements that can easily crystallized at low temperature on glass substrates, together with possessing preferred crystal orientations and sizes, zinc oxide layer with preferred crystal orientation and large grain size can be formed, leading to potential optimization of transparent conductive oxide layer stacks.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Guowen Ding, Hien Minh Huu Le, Zhi-Wen Sun
  • Publication number: 20140008546
    Abstract: A structured substrate is described which is suitable for forming and hosting a crystal array, as well as associated methods for making and using such a structured substrate. The structured substrate is made by injection molding and has on one side a combination of macro- and micro-structured features. Each macro-structured feature comprises an edge that forms a perimeter around an enclosed area containing a large number of the micro-structured features. When a droplet of a solution containing molecules of interest and a solvent is deposited onto one of the enclosed areas such that it extends somewhat beyond the perimeter, the droplet slowly dries and shrinks through evaporation of the solvent, during which the edge acts to seed crystallization of the molecules, and the micro-structured features act to direct crystal growth from the seed into the enclosed area. The crystal thus forms over the whole of the enclosed area in a shape that conforms to the perimeter.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 9, 2014
    Applicant: Sony DADC Austria AG
    Inventors: Christoph MAURACHER, Werner BALIKA, Andrew NAISBY
  • Patent number: 8623137
    Abstract: A method for slicing a shaped silicon ingot includes providing a single crystal silicon boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in an <100> crystallographic direction substantially vertically extending from the first end-face to the second end-face. The method further includes cutting the single crystal silicon boule substantially through an {110} crystallographic plane in parallel to the axis to separate the single crystal silicon boule into a first portion with a first surface and a second portion with a second surface. Additionally, the method includes exposing either the first surface of the first portion or the second surface of the second portion and performing a layer transfer process to form a single crystal silicon sheet from either the first surface of the first portion or from the second surface of the second portion.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: January 7, 2014
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Publication number: 20130333612
    Abstract: Embodiments described herein relate to compositions, devices, and methods for the alignment of certain materials including liquid crystals. In some cases, a photoresponsive material include a moiety capable of undergoing a di-pi-methane rearrangement. Methods described herein may provide chemically and/or thermally stable alignment materials for use in a various technologies, including transistors, luminescent devices, and liquid crystal devices.
    Type: Application
    Filed: March 6, 2013
    Publication date: December 19, 2013
    Applicant: Massachusetts Institute of Technology
    Inventor: Massachusetts Institute of Technology
  • Publication number: 20130333613
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Application
    Filed: March 4, 2012
    Publication date: December 19, 2013
    Applicant: Mosiac Crystals Ltd.
    Inventor: Moshe Einav
  • Publication number: 20130266727
    Abstract: A method is disclosed involving depositing a neutral orientation template layer onto a substrate after formation of chemical epitaxy or graphoepitaxy features on the substrate, but before deposition and orientation of a self-assemblable polymer. The orientation layer is arranged to bond with the substrate but not with certain features, so that it may be easily removed by vacuum or rinsing with organic solvent. The neutral orientation layer has a chemical affinity to match that of blocks in the self-assemblable polymer so that blocks of differing types wet the neutral orientation layer so that domains in the self-assembled polymer may lie side by side along the substrate surface, with interfaces normal to the substrate surface. The resulting aligned and oriented self-assembled polymer may itself be used as a resist for device lithography of the substrate.
    Type: Application
    Filed: December 9, 2011
    Publication date: October 10, 2013
    Inventors: Emiel Peeters, Wilhelmus Sebastianus Marcus Maria Ketelaars, Johan Frederik Dijksman, Sander Frederik Wuister, Roelof Koole, Christianus Martinus Van Heesch
  • Publication number: 20130255566
    Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.
    Type: Application
    Filed: August 24, 2012
    Publication date: October 3, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Publication number: 20130255565
    Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.
    Type: Application
    Filed: August 24, 2012
    Publication date: October 3, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Publication number: 20130233238
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 12, 2013
    Applicant: IMEC
    Inventors: Benjamin Vincent, Aaron Thean, Liesbeth Witters
  • Publication number: 20130199438
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor single crystal having excellent crystallinity, and a method for producing a GaN substrate having excellent crystallinity, the method including controlling melting back. Specifically, a mask layer is formed on a GaN substrate serving as a growth substrate. Then, a plurality of trenches which penetrate the mask layer and reach the GaN substrate are formed through photolithography. The obtained seed crystal and raw materials of a single crystal are fed to a crucible and subjected to treatment under pressurized and high temperature conditions. Portions of the GaN substrate exposed to the trenches undergo melting back with a flux. Through dissolution of the GaN substrate, the dimensions of the trenches increase, to provide large trenches. The GaN layer is grown from the surface of the mask layer as a starting point.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 8, 2013
    Applicant: TOYODA GOSEI CO., LTD.
    Inventor: TOYODA GOSEI CO., LTD.
  • Publication number: 20130160699
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Application
    Filed: February 8, 2013
    Publication date: June 27, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Publication number: 20130118400
    Abstract: The present invention is directed to a method of forming an epitaxial zinc oxide film on a substrate. The method includes forming an array of nanorods at least substantially perpendicular to the substrate in an aqueous solution; and growing the array of nanorods in an at least substantially lateral direction in the aqueous solution such that adjacent nanorods coalesce to form the epitaxial film. The present invention also relates to the films thus obtained and devices containing said films.
    Type: Application
    Filed: June 3, 2011
    Publication date: May 16, 2013
    Inventor: Kia Liang Gregory Goh
  • Publication number: 20130119518
    Abstract: A method for growing semiconductor wafers by lateral diffusion liquid phase epitaxy is described. Also provided are a refractory device for practicing the disclosed method and semiconductor wafers prepared by the disclosed method and device. The disclosed method and device allow for significant cost and material waste savings over current semiconductor production technologies.
    Type: Application
    Filed: May 17, 2012
    Publication date: May 16, 2013
    Applicant: MCMASTER UNIVERSITY
    Inventors: Adrian Kitai, Haoling Yu, Bo Li
  • Publication number: 20130093290
    Abstract: A ferroelectric device comprising a substrate; a textured layer; a first electrode comprising a thin layer of metallic material having a crystal lattice structure divided into granular regions; a seed layer; the seed layer being epitaxially deposited so as to form a column-like structure on top of the granular regions of the first electrode; at least one ferroelectric material layer exhibiting spontaneous polarization epitaxially deposited on the seed layer; the ferroelectric material layer, the seed layer, and first electrode each having granular regions in which column-like structures produce a high degree of polarization normal to the growth plane and a method of making.
    Type: Application
    Filed: March 30, 2012
    Publication date: April 18, 2013
    Applicant: U.S. Government as represented by the Secretary of the Army
    Inventors: GLEN R. FOX, Ronald G. Polcawich, Daniel M. Potrepka, Luz M. Sanchez
  • Patent number: 8404042
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20130042801
    Abstract: Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process- and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Inventors: Thomas Gmitter, Gang He, Melissa Archer, Siew Neo
  • Publication number: 20120264615
    Abstract: A method for making a superconducting article includes the steps of providing a biaxially textured substrate. A seed layer is then deposited. The seed layer includes a double perovskite of the formula A2B?B?O6, where A is rare earth or alkaline earth metal and B? and B? are different rare earth or transition metal cations. A superconductor layer is grown epitaxially such that the superconductor layer is supported by the seed layer.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Inventors: Amit Goyal, Mariappan Parans Paranthaman, Sung Hun Wee
  • Patent number: 8263483
    Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20120174855
    Abstract: A method for making an epitaxial structure is provided. The method includes following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. An epitaxial layer is epitaxially grown on the buffer layer. The substrate is removed.
    Type: Application
    Filed: October 18, 2011
    Publication date: July 12, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Publication number: 20120174856
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Application
    Filed: October 18, 2011
    Publication date: July 12, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Publication number: 20120168710
    Abstract: In a method of making a monolithic elongated nanowire, a mask polymer layer is applied to a selected crystal surface of a seed crystal. A plurality of spaced apart elongated openings is defined through the mask polymer layer, thereby exposing a corresponding plurality of portions of the crystal surface. The openings are disposed so as to be aligned with and parallel to a selected crystal axis of the seed crystal. The portions of the crystal surface are subjected to a chemical nutrient environment that causes crystalline material to grow from the plurality of portions for at least a period of time so that monocrystalline members grow from the elongated openings and until the monocrystalline members laterally expand so that each monocrystalline member grows into and merges with an adjacent one of the monocrystalline members, thereby forming a monolithic elongated nanowire.
    Type: Application
    Filed: December 29, 2010
    Publication date: July 5, 2012
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Zhong L. Wang, Sheng Xu
  • Publication number: 20120164058
    Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 28, 2012
    Inventors: Tomoki UEMURA, Takashi SAKURADA, Shinsuke FUJIWARA, Takuji OKAHISA, Koji UEMATSU, Hideaki NAKAHATA
  • Publication number: 20120162766
    Abstract: A polarizer is provided comprising: a transparent substrate, on a main surface of which a plurality of grooves in parallel with each other are provided at an interval; a birefringence crystal layer with a single orientation formed on the main surface of the transparent substrate where the grooves are provided, wherein the birefringence crystal layer is at least filled in the grooves so that linearly polarized light incident on a location corresponding to the grooves and passing through the polarizer is converted into first polarized light, and linearly polarized light incident on a location between the grooves and passing through the polarizer is converted into second polarized light, the polarization directions of the first and the second polarized light are different from each other.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 28, 2012
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yun Bok LEE, Ku Hyun PARK
  • Publication number: 20120118222
    Abstract: A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 1.0 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 17, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Koji Uematsu, Yoshiyuki Yamamoto, Issei Satoh
  • Publication number: 20120074403
    Abstract: The present invention is to provide GaN crystal growing method for growing a GaN crystal with few stacking faults on a GaN seed crystal substrate having a main surface inclined at an angle of 20° to 90° from the (0001) plane, and also to provide a GaN crystal substrate with few stacking faults. A method for growing a GaN crystal includes the steps of preparing a GaN seed crystal substrate 10 having a main surface 10m inclined at an angle of 20° to 90° from a (0001) plane 10c and growing a GaN crystal 20 on the GaN seed crystal substrate 10. The GaN seed crystal substrate 10 and the GaN crystal 20 have a difference in impurity concentration of 3×1018 cm?3 or less.
    Type: Application
    Filed: May 19, 2011
    Publication date: March 29, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke Fujiwara, Koji Uematsu, Hideki Osada