Separating From Substrate Patents (Class 117/915)
  • Patent number: 11887912
    Abstract: The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 30, 2024
    Assignees: Fudan University, Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd.
    Inventors: Bao Zhu, Lin Chen, Qingqing Sun, Wei Zhang
  • Patent number: 11335557
    Abstract: A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial layer coupled to the engineered substrate, and a hybrid vapor phase epitaxy (HVPE) III-N-based epitaxial layer coupled to the MOCVD epitaxial layer.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 17, 2022
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 11257955
    Abstract: The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 22, 2022
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Qinghe Wang, Luke Ding, Leilei Cheng, Jun Bao, Tongshang Su, Dongfang Wang, Guangcai Yuan
  • Patent number: 11094536
    Abstract: A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 17, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Haruhiko Nishikage, Yoshinori Miyamoto, Yasunobu Hosokawa
  • Patent number: 11087974
    Abstract: A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 10, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Stephen R. Forrest, Kyusang Lee
  • Patent number: 10960574
    Abstract: A method for producing solid layers includes: providing a solid for separating at least one solid layer; fixing an accommodating layer for holding the solid layer on the solid, wherein the accommodating layer has a multiplicity of holes for conducting a liquid, wherein the accommodating layer is fixed on the solid by means of a connecting layer; and thermal loading of the accommodating layer for mechanical generation of stresses in the solid. A crack in the solid propagates along a detachment plane due to the stresses. The solid layer is separated from the solid by means of the crack. The accommodating layer includes at least one polymer material, and the polymer material undergoes a glass transition at a temperature lower than 0° C.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 30, 2021
    Assignee: Siltectra GmbH
    Inventors: Jan Richter, Christian Beyer, Anas Ajaj
  • Patent number: 10867834
    Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 15, 2020
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Patent number: 10852492
    Abstract: Structures and methods for passively aligning a photonic die with a receiving substrate are described. Three alignment surfaces, having dimensions greater than a desired alignment accuracy, may be formed on the photonic die and used to passively and accurately align the photonic die to a receiving substrate in six degrees of freedom. Two of the three alignment surfaces on the photonic die may be formed in a single mask-and-etch process, while the third alignment surface may require no patterning or etching. Three complementary alignment surfaces on the receiving substrate may be formed in a single mask-and-etch process.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: December 1, 2020
    Assignee: Acacia Communications, Inc.
    Inventors: Diedrik Vermeulen, Christopher Doerr
  • Patent number: 10854801
    Abstract: A method for directly bonding semiconductor devices from multiple carrier substrates to a target substrate using relative alignments of semiconductor contacts to substrate contacts, as well as relative heights of semiconductor contacts to substrate contacts. The method may include directly bonding a subset of semiconductor devices on a first carrier substrate with a first alignment to a subset of substrate contacts, and directly bonding a subset of second semiconductor device on a second carrier substrate with a second alignment to a subset of substrate contacts. The method may include directly bonding a subset of semiconductor devices with a first height on a first carrier substrate to a first subset of substrate contacts, followed by directly bonding a second subset of second semiconductor devices with a second height on a second carrier substrate to a second subset of substrate contacts.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 1, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: William Padraic Henry, John Michael Goward
  • Patent number: 10679852
    Abstract: A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial layer coupled to the engineered substrate, and a hybrid vapor phase epitaxy (HVPE) III-N-based epitaxial layer coupled to the MOCVD epitaxial layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 9, 2020
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 10655243
    Abstract: An engineered substrate includes a support structure comprising a polycrystalline ceramic core, an adhesion layer coupled to the polycrystalline ceramic core, and a barrier layer coupled to the adhesion layer. The engineered substrate also includes an bonding layer coupled to the support structure, a substantially single crystal layer coupled to the bonding layer, and an epitaxial gallium nitride layer coupled to the substantially single crystal layer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 19, 2020
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 10612157
    Abstract: Provided is a method for manufacturing an SiC composite substrate 10 having a single-crystal SiC layer 12 on a polycrystalline SiC substrate 11, wherein: the single-crystal SiC layer 12 is provided on one surface of a holding substrate 21 comprising Si, and a single-crystal SiC-layer carrier 14 is prepared; polycrystalline SiC is then accumulated on the single-crystal SiC layer 12 by a physical or chemical means, and an SiC laminate 15 is prepared in which the single-crystal SiC layer 12 and the polycrystalline SiC substrate 11 are laminated on the holding substrate 21; and the holding substrate 21 is then physically and/or chemically removed. With the present invention, an SiC composite substrate having a single-crystal. SiC layer with good crystallinity is obtained with a simple manufacturing process.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: April 7, 2020
    Assignees: SHIN-ETSU CHEMICAL CO., LTD., CUSIC INC.
    Inventors: Yoshihiro Kubota, Shoji Akiyama, Hiroyuki Nagasawa
  • Patent number: 10460948
    Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10453739
    Abstract: A method of transferring blocks of semiconductor material to a substrate comprises the following steps: a. providing an intermediate substrate, the intermediate substrate comprising, on one of its faces, blocks, the blocks comprise a monocrystalline material, the blocks comprising an embrittlement area delimiting a block portion intended to be transferred onto a final substrate; b. executing an assembling step by putting a free surface of each of the blocks in contact with the final substrate; and c. executing, after the assembling step, detachment at the embrittlement area of each of the blocks. During the assembling step, the intermediate substrate deforms so that the free surfaces of the blocks become coplanar.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: October 22, 2019
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 10400352
    Abstract: Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 3, 2019
    Assignee: SORAA, INC.
    Inventors: Mark P. D'Evelyn, James S. Speck, Derrick S. Kamber, Douglas W. Pocius
  • Patent number: 10283355
    Abstract: The present disclosure provides a method for manufacturing a poly-silicon layer. The method for manufacturing the poly-silicon layer comprises steps of: depositing a porous metal film on a microcrystalline silicon layer of a base substrate; immersing the base substrate deposited with the porous metal film into an etching liquid comprising hydrogen fluoride and oxidants for etching the microcrystalline silicon layer; after the microcrystalline silicon layer has been etched successfully, removing the metal film with an acid solution and washing the microcrystalline silicon layer with a deionized water subsequently so as to obtain a processed microcrystalline silicon layer; and depositing an amorphous silicon layer on the processed microcrystalline silicon layer and subjecting the amorphous silicon layer to laser annealing treatment so as to obtain the poly-silicon layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 7, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qianqian Bu
  • Patent number: 9941168
    Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 10, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sanghyeon Kim, Hyung-jun Kim, Jae-Phil Shim, Seong Kwang Kim, Won Jun Choi
  • Patent number: 9922858
    Abstract: Provided is a semiconductor device manufacturing method that includes joining a support substrate to a back side of a semiconductor wafer across a ceramic adhesive layer and a mask, to form a joined body. The method further includes forming a functional structure on a front side of the semiconductor wafer. The method further includes detaching the support substrate from the semiconductor wafer by removing the ceramic adhesive layer and the mask. The method further includes a back side processing step of carrying out back side processing on the back side of the semiconductor wafer.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: March 20, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaaki Tachioka, Tsunehiro Nakajima
  • Patent number: 9783885
    Abstract: Methods and apparatus are disclosed for producing diamond masses and products thereof using diamond unit cell forming reactions in vapor phase and solid phase. The present invention enables the fabrication of diamond products having a purity and morphology previously unattainable.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 10, 2017
    Assignee: Unit Cell Diamond LLC
    Inventors: Arnold L. Newman, Daniel Hodes
  • Patent number: 9754810
    Abstract: The invention relates to a method for the production of layers of solid material, in particular for use as wafers, comprising the following steps: providing a workpiece for the separation of layers of solid material, the workpiece having at least one exposed surface, producing and/or providing a carrier unit for receiving at least one layer of solid material, the carrier unit being made in a number of layers, the carrier unit having a stabilisation layer and the stabilisation layer being overlapped at least partially by a receiving layer, the receiving layer being made to hold the layer of solid material, and the stabilisation layer being formed, at least partially, such that it has an E modulus that is greater than the E modulus of the receiving layer, connecting the receiving layer to the exposed surface of the workpiece, thus forming a composite structure, exposing the composite structure to an inner and/or outer stress field such that the layer of solid material is separated along a plane of the workpiece
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 5, 2017
    Assignee: Siltectra GmbH
    Inventor: Lukas Lichtensteiger
  • Patent number: 9716107
    Abstract: This composite substrate has a single-crystal semiconductor thin film (13) provided to at least the front surface of an inorganic insulating sintered-body substrate (11) having a thermal conductivity of at least 5 W/m·K and a volume resistivity of at least 1×108 ?·cm. The composite substrate also has, provided between the inorganic insulating sintered-body substrate (11) and the single-crystal semiconductor thin film (13), a silicon coating layer (12) comprising polycrystalline silicon or amorphous silicon. As a result of the present invention, metal impurity contamination from the sintered body can be inhibited, even in a composite substrate in which a single-crystal silicon thin film is provided upon an inexpensive ceramic sintered body which is opaque with respect to visible light, which exhibits an excellent thermal conductivity, and which further exhibits little loss at a high frequency range, and characteristics can be improved.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: July 25, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Makoto Kawai, Shigeru Konishi
  • Patent number: 9709740
    Abstract: Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 9627420
    Abstract: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: April 18, 2017
    Assignee: Carestream Health, Inc.
    Inventors: Roger Stanley Kerr, Timothy John Tredwell
  • Patent number: 9627235
    Abstract: A supporting member separation method for separating a laminate which is formed by laminating a substrate and a support plate through an adhesive layer and in which a release layer is provided on at least a part of the peripheral portion on the surface of the side of the substrate facing the support plate or the peripheral portion on the surface of the side of the support plate facing the substrate, the method including reducing the adhesive force of at least a part of the release layer which is provided on the peripheral portion of the substrate or the support, and fixing a part in the substrate and the support plate and separating the support plate from the substrate by applying a force to another part, after the preliminary treatment.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 18, 2017
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yasumasa Iwata, Yoshihiro Inao, Akihiko Nakamura, Shinji Takase, Takahiro Yoshioka
  • Patent number: 9614270
    Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, John M. Cotte
  • Patent number: 9520286
    Abstract: A semiconductor substrate having a silicon-based substrate, a buffer layer provided on the silicon-based substrate and made of a nitride semiconductor containing boron, and an operation layer formed on the buffer layer, wherein a concentration of boron in the buffer layer gradually decreasing toward a side of the operation layer from a side of the silicon-based substrate. Thereby, the semiconductor substrate in which the buffer layer contains boron sufficient to obtain a dislocation suppression effect and boron is not diffused to the operation layer is provided.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: December 13, 2016
    Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 9508894
    Abstract: A method of selectively transferring semiconductor devices comprises the steps of providing a substrate having a first surface and a second surface; providing a plurality of semiconductor epitaxial stacks on the first surface, wherein each of the plurality of semiconductor epitaxial stacks comprises a first semiconductor epitaxial stack and a second semiconductor epitaxial stack, and the first semiconductor epitaxial stack is apart from the second semiconductor epitaxial stack, and wherein a adhesion between the first semiconductor epitaxial stack and the substrate is different from a adhesion between the second semiconductor epitaxial stack and the substrate; and selectively separating the first semiconductor epitaxial stack or the second semiconductor epitaxial stack from the substrate.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 29, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Chiang Lu, Yi-Ming Chen, Chun-Yu Lin, Ching-Pei Lin, Chung-Hsun Chien, Chien-Fu Huang, Hao-Min Ku, Min-Hsun Hsieh, Tzu-Chieh Hsu
  • Patent number: 9472650
    Abstract: A method of manufacturing a flexible display device, the method including forming a sacrificial layer on a carrier substrate such that the sacrificial layer includes a hydrogen trap material and amorphous silicon; forming a support layer and a thin film transistor on the sacrificial layer; and separating the support layer from the carrier substrate by irradiating a laser to the sacrificial layer.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Woo Koo, Ki Hyun Kim, Sun Ho Kim, Jeong ho Kim
  • Patent number: 9011598
    Abstract: The present invention provides methods for fabricating a composite substrate including a supporting substrate and a layer of a binary or ternary material having a crystal form that is non-cubic and semi-polar or non-polar. The methods comprise transferring the layer of a binary or ternary material from a donor substrate to a receiving substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 21, 2015
    Assignee: Soitec
    Inventors: Alice Boussagol, Frédéric Dupont, Bruce Faure
  • Patent number: 8932403
    Abstract: A method for forming a surface-textured single-crystal film layer by growing the film atop a layer of microparticles on a substrate and subsequently selectively etching away the microparticles to release the surface-textured single-crystal film layer from the substrate. This method is applicable to a very wide variety of substrates and films. In some embodiments, the film is an epitaxial film that has been grown in crystallographic alignment with respect to a crystalline substrate.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sandia Corporation
    Inventors: Qiming Li, George T. Wang
  • Patent number: 8888914
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Patent number: 8882910
    Abstract: A substrate is formed of AlxGa1-xN, wherein 0<x?1. The substrate is a single crystal and is used producing a Group III nitride semiconductor device. A method for producing a substrate of AlxGa1-xN, wherein 0<x?1, includes the steps of forming a layer of AlxGa1-xN, wherein 0<x?1, on a base material and removing the base material. The method adopts the MOCVD method using a raw material molar ratio of a Group V element to Group III element that is 1000 or less, a temperature of 1200° C. or more for forming the layer of AlxGa1-xN, wherein 0<x?1. The base material is formed of one member selected from the group consisting of sapphire, SiC, Si, ZnO and Ga2O3. The substrate is used for fabricating a Group III nitride semiconductor device.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 11, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hiroshi Amano, Akira Bando
  • Patent number: 8877077
    Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 4, 2014
    Assignee: Siltectra GmbH
    Inventor: Lukas Lichtensteiger
  • Patent number: 8835282
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan Cheung
  • Patent number: 8723288
    Abstract: A single crystal having a technologically generated cleavage surface that extends along a natural crystallographic cleavage plane with an accuracy of less than |0.001°| when measured over a length relevant for the technology of the single crystal or over each of a plurality of surface areas extending in the direction of separation and having a length ?2 mm within the technologically relevant surface area.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 13, 2014
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ralf Hammer, Manfred Jurisch
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 8097080
    Abstract: A method of dividing single crystals, particularly of plates of parts thereof, is proposed, which can comprise: pre-adjusting the crystallographic cleavage plane (2?) relative to the cleavage device, setting a tensional intensity (K) by means of tensional fields (3?, 4?), determining an energy release rate G(?) in dependence from a possible deflection angle (?) from the cleavage plane (2?) upon crack propagation, controlling the tensional fields (3?, 4?) such that the crack further propagates in the single crystal, wherein G(0)?2?e(0) and simultaneously at least one of the following conditions is satisfied: ? ? G ? ? ? ? = 0 ? 2 ? ? e h ? ? if ? ? ? 2 ? G ? ? 2 ? 0 ? ? or ( 2.1 ) ? ? G ? ? ? ? 2 ? ? e h ? ? ? ? : ? ? 1 < ? < ? 2 . ( 2.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 17, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ralf Hammer, Manfred Jurisch
  • Patent number: 8092597
    Abstract: Method for producing a III-N (AlN, GaN, AlxGa(1-x)N) crystal by Vapor Phase Epitaxy (VPE), the method comprising: providing a reactor having: a growth zone for growing a III-N crystal; a substrate holder located in the growth zone that supports at least one substrate on which to grow the III-N crystal; a gas supply system that delivers growth material for growing the III-N crystal to the growth zone from an outlet of the gas supply system; and a heating element that controls temperature in the reactor; determining three growth sub-zones in the growth zone for which a crystal grown in the growth sub-zones has respectively a concave, flat or convex curvature; growing the III-N crystal on a substrate in a growth region for which the crystal has a by desired curvature.
    Type: Grant
    Filed: January 22, 2011
    Date of Patent: January 10, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Vladimir A. Dmitriev, Yuri V. Melnik
  • Patent number: 8012289
    Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 6, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Takeshi Akatsu
  • Patent number: 7998273
    Abstract: An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: August 16, 2011
    Assignees: Freiberger Compound Materials GmbH, Osram Opto Semiconductors GmbH
    Inventors: Ferdinand Scholz, Peter Brückner, Frank Habel, Matthias Peter, Klaus Köhler
  • Patent number: 7993453
    Abstract: A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, u
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: August 9, 2011
    Assignee: Showa Denko K.K.
    Inventors: Naoki Oyanagi, Tomohiro Syounai, Yasuyuki Sakaguchi
  • Patent number: 7976629
    Abstract: Processes and machines for producing large area sheets or films of crystalline, polycrystalline, or amorphous material are set forth; the production of such sheets being valuable for the manufacturing of solar photovoltaic cells, flat panel displays and the like. The surface of rotating cylindrical workpiece (10) is implanted with ion beam (30), whereby a layer of weakened material is formed below the surface. Sheet (20) is detached and peeled off, producing arbitrarily large, monolithic sheets. The sheet may be supported on a temporary or permanent handle (50) such as a glass sheet or a polymer film. Pinch roller (60) may assist in the lamination of handle (50) to sheet (20) before or after the point of separation of sheet (20) from workpiece (10). The implantation, annealing and separation processes are adapted to encourage the material to separate along the implanted layer rather than a particular crystal plane.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: July 12, 2011
    Inventor: Adam Alexander Brailove
  • Patent number: 7959731
    Abstract: A method for producing a semiconductor wafer, including epitaxially growing a Si1-XGeX layer (0<X?1) on a surface of a silicon single crystal wafer to be a bond wafer; implanting at least one kind of a hydrogen ion or a rare gas ion through the Si1-XGeX layer and forming an ion-implanted layer inside the bond wafer; contacting and bonding a surface of the Si1-XGeX layer and a surface of a base wafer through an insulator film; then performing delamination at the ion-implanted layer; performing a bonding heat treatment of binding the bonded surfaces; and then removing a Si layer of a delaminated layer transferred to a side of the base wafer by the delamination. Thereby, the method does not cause lattice relaxation in the SiGe layer. Therefore, the method is suitable for production of a semiconductor wafer for high-speed semiconductor devices.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: June 14, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Hiroji Aga, Kiyoshi Mitani
  • Patent number: 7901966
    Abstract: A method for manufacturing a nitride semiconductor device, comprises: epitaxially growing a semiconductor layer of a GaN-based material on the Ga surface of a GaN substrate while the GaN substrate is mounted on a substrate holder the substrate warping during the epitaxial growth so that a epitaxial deposit is deposited on the N surface of the substrate; and subjecting the N surface of the GaN substrate to vacuum suction after the epitaxial growth of the semiconductor layer; removing the epitaxial deposit from the N side of the GaN substrate after the semiconductor layer has been epitaxially grown, and before the N surface of the n-type GaN substrate is subjected to vacuum suction.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: March 8, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Abe, Kazushige Kawasaki
  • Patent number: 7842134
    Abstract: The invention relates to a method of manufacture of a substrate for fabrication of semiconductor layers or devices, comprising the steps of providing a wafer of silicon including at least one first surface suitable for use as a substrate for CVD diamond synthesis, growing a layer of CVD diamond of predetermined thickness and having a growth face onto the first surface of the silicon wafer, reducing the thickness of the silicon wafer to a predetermined level, and providing a second surface on the silicon wafer that is suitable for further synthesis of at least one semiconductor layer suitable for use in electronic devices or synthesis of electronic devices on the second surface itself and to a substrate suitable for GaN device growth consisting of a CVD diamond layer intimately attached to a silicon surface.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: November 30, 2010
    Inventors: Andrew John Whitehead, Christopher John Howard Wort, Geoffrey Alan Scarsbrook
  • Patent number: 7820523
    Abstract: The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 26, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Andrieu, Thomas Ernst, Simon Deleonibus
  • Patent number: 7794542
    Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: September 14, 2010
    Assignee: Cree, Inc.
    Inventors: Michael A. Tischler, Thomas F. Kuech, Robert P. Vaudo
  • Patent number: 7749325
    Abstract: A method of producing a separated GaN crystal body grown by vapor phase epitaxy on a substrate made of material different from GaN is provided. In this method, a nitride deposit is formed during the growth on a periphery of the substrate and GaN crystal body. The present method comprises the steps of: processing the periphery of the substrate to remove the nitride deposit; and, after the peripheral processing, separating the substrate from the GaN crystal body to make the substrate and the GaN crystal body independent of each other.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masahiro Nakayama
  • Patent number: 7544265
    Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: June 9, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Pierre Rayssac, legal representative, Gisele Rayssac, legal representative, Takeshi Akatsu, Olivier Rayssac
  • Patent number: 7501023
    Abstract: A method and apparatus for growing low defect, optically transparent, colorless, crack-free, substantially flat, single crystal Group III nitride epitaxial layers with a thickness of at least 10 microns is provided. These layers can be grown on large area substrates comprised of Si, SiC, sapphire, GaN, AlN, GaAs, AlGaN and others. In one aspect, the crack-free Group III nitride layers are grown using a modified HVPE technique. If desired, the shape and the stress of Group III nitride layers can be controlled, thus allowing concave, convex and flat layers to be controllably grown. After the growth of the Group III nitride layer is complete, the substrate can be removed and the freestanding Group III nitride layer used as a seed for the growth of a boule of Group III nitride material. The boule can be sliced into individual wafers for use in the fabrication of a variety of semiconductor structures (e.g., HEMTs, LEDs, etc.).
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: March 10, 2009
    Assignee: Technologies and Devices, International, Inc.
    Inventors: Vladimir A. Dmitriev, Yuri V. Melnik