Free Metal Or Intermetallic Compound Or Silicon-metal Compound Based, Except Arsenic (e.g., Alloys, Sige, Insb) {c30b 29/40, 29/52} Patents (Class 117/939)
  • Patent number: 8790462
    Abstract: A nanoengineered structure comprising an array of more than about 1000 nanowhiskers on a substrate in a predetermined spatial configuration, for use for example as a photonic band gap array, wherein each nanowhisker is sited within a distance from a predetermined site not greater than about 20% of its distance from its nearest neighbour. To produce the array, an array of masses of a catalytic material are positioned on the surface, heat is applied and materials in gaseous form are introduced such as to create a catalytic seed particle from each mass, and to grow, from the catalytic seed particle, epitaxially, a nanowhisker of a predetermined material, and wherein each mass upon melting, retains approximately the same interface with the substrate surface such that forces causing the mass to migrate across said surface are less than a holding force across a wetted interface on the substrate surface.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 29, 2014
    Assignee: Qunano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson, Thomas M. I. Martensson
  • Patent number: 8568681
    Abstract: A method is provided for synthesizing silicon-germanium hydride compounds of the formula (H3Ge)4-xSiHx, wherein x=0, 1, 2 or 3. The method includes combining a silane triflate with a compound having a GeH3 ligand under conditions whereby the silicon-germanium hydride is formed. The compound having the GeH3 ligand is selected from the group consisting of KGeH3, NaGeH3 and MR3GeH3, wherein M is a Group IV element and R is an organic ligand. The silane triflate can be HxSi(OSO2CF3)4-x or HxSi(OSO2C4F9)4-x. The method can be used to synthesize trisilane, (H3Si)2SiH2, and the iso-tetrasilane analog, (H3Si)3SiH, by combining a silane triflate with a compound comprising a SiH3 ligand under conditions whereby the silicon hydride is formed. The silane triflate can include HxSi(OSO2CF3)4-x or HxSi(OSO2C4F9)4-x wherein x=1 or 2. A method for synthesizing (H3Ge)2SiH2 includes combining H3GeSiH2(OSO2CF3) with KGeH3 under conditions whereby (H3Ge)2SiH2 is formed.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 29, 2013
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona acting for and on behalf of Arizona State University
    Inventors: John Kouvetakis, Cole J. Ritter, John Tolle
  • Patent number: 8187377
    Abstract: The present invention provides for treating a surface of a semiconductor material. The method comprises exposing the surface of the semiconductor material to a halogen etchant in a hydrogen environment at an elevated temperature. The method controls the surface roughness of the semiconductor material. The method also has the unexpected benefit of reducing dislocations in the semiconductor material.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: May 29, 2012
    Assignee: Silicon Genesis Corporation
    Inventors: Igor J. Malik, Sien G. Kang, Martin Fuerfanger, Harry Kirk, Ariel Flat, Michael Ira Current, Philip James Ong
  • Patent number: 8048222
    Abstract: The present invention provides an improved process for preparing modafinil, whereby it may be isolated in high purity by a single crystallization. The process produces modafinil free of sulphone products of over-oxidation and other byproducts. The invention further provides new crystalline Forms II-VI of modafinil and processes for preparing them. Each of the new forms is differentiated by a unique powder X-ray diffraction pattern. The invention further provides pharmaceutical compositions containing novel modafinil Forms II-IV and VI.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: November 1, 2011
    Assignee: Teva Pharmaceutical Industries, Ltd.
    Inventors: Arina Ceausu, Anita Lieberman, Judith Aronhime
  • Patent number: 8043980
    Abstract: The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, SixGeyHz—aXa; wherein X is halogen, and x, y, z, and a are defined herein, and methods for the deposition of high-Ge content Si films on silicon substrates using compounds of the invention.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 25, 2011
    Assignee: Arizona Board of Regents, A Body Corporate Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Jesse Tice, Yan-Yan Fang
  • Patent number: 7981392
    Abstract: A method is provided for synthesizing silicon-germanium hydride compounds of the formula (H3Ge)4-XSiHX, wherein x=0, 1, 2 or 3. The method includes combining a silane triflate with a compound having a GeH3 ligand under conditions whereby the silicon-germanium hydride is formed. The compound having the GeH3 ligand is selected from the group consisting of KGeH3, NaGeH3 and MR3GeH3, wherein M is a Group IV element and R is an organic ligand. The silane triflate can be HXSi(OSO2CF3)4-x or HxSi(OSO2C4F9)4-x. The method can be used to synthesize trisilane, (H3Si)2SiH2, and the iso-tetrasilane analog, (H3Si)3SiH, by combining a silane triflate with a compound comprising a SiH3 ligand under conditions whereby the silicon hydride is formed. The silane triflate can include HXSi(OSO2CF3)4-x or HXSi(OSO2C4F9)4-x wherein x=1 or 2. A method for synthesizing (H3Ge)2SiH2 includes combining H3GeSiH2(OSO2CF3) with KGeH3 under conditions whereby (H3Ge)2SiH2 is formed.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: July 19, 2011
    Assignee: The Arizona Board of Regents, a body corporate of the state of Arizona acting for and on behalf of Arizona State University
    Inventors: John Kouvetakis, Cole J. Ritter, III, John Tolle
  • Patent number: 7820523
    Abstract: The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 26, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Andrieu, Thomas Ernst, Simon Deleonibus
  • Patent number: 7759228
    Abstract: A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: July 20, 2010
    Assignees: Kabushiki Kaisha Toshiba, Oki Electric Industry Co., Ltd.
    Inventors: Naoharu Sugiyama, Norio Hirashita, Tsutomu Tezuka
  • Patent number: 7674335
    Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 7615116
    Abstract: In a vapor phase growth apparatus including a reaction chamber, a susceptor, a lift pin, an upper heating device, and a lower heating device, a heating ratio between the upper heating ratio and the lower heating ratio is adjusted.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 10, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koichi Kanaya, Tsuyoshi Nishizawa
  • Patent number: 7608147
    Abstract: A nanoengineered structure comprising an array of more than about 1000 nanowhiskers on a substrate in a predetermined spatial configuration, for use for example as a photonic band gap array, wherein each nanowhisker is sited within a distance from a predetermined site not greater than about 20% of its distance from its nearest neighbor. To produce the array, an array of masses of a catalytic material are positioned on the surface, heat is applied and materials in gaseous form are introduced such as to create a catalytic seed particle from each mass, and to grow, from the catalytic seed particle, epitaxially, a nanowhisker of a predetermined material, and wherein each mass upon melting, retains approximately the same interface with the substrate surface such that forces causing the mass to migrate across said surface are less than a holding force across a wetted interface on the substrate surface.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: October 27, 2009
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson, Thomas M. I. Martensson
  • Patent number: 7598513
    Abstract: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x?0.25, y?0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: October 6, 2009
    Inventors: John Kouvetakis, Matthew Bauer, John Tolle
  • Patent number: 7594967
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: September 29, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Patent number: 7557018
    Abstract: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shu Nakaharai, Tsutomu Tezuka, Shinichi Takagi
  • Patent number: 7540920
    Abstract: Embodiments of the invention generally provide a composition of silicon compounds and methods for using the silicon compounds to deposit a silicon-containing film. The processes employ introducing the silicon compound to a substrate surface and depositing a portion of the silicon compound, the silicon motif, as the silicon-containing film. The ligands are another portion of the silicon compound and are liberated as an in-situ etchant. The in-situ etchants supports the growth of selective silicon epitaxy. Silicon compounds include SiRX6, Si2RX6, Si2RX8, wherein X is independently hydrogen or halogen and R is carbon, silicon or germanium. Silicon compound also include compounds comprising three silicon atoms, fourth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen, as well as, comprising four silicon atoms, fifth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: June 2, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Paul B. Comita, Lance A. Scudder, David K. Carlson
  • Patent number: 7501331
    Abstract: The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited silicon-germanium film, temperature can be reduced substantially. In preferred embodiments, for example in a monolithic three dimensional array of stacked memory levels, reduced temperature allows the use of aluminum metallization. In some embodiments, use of metal-induced crystallization in a vertically oriented silicon-germanium diode having conductive contacts at the top and bottom end is be particularly advantageous, as increased solubility of the metal catalyst in the contact material will reduce the risk of metal contamination of the diode.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 10, 2009
    Assignee: Sandisk 3D LLC
    Inventor: S. Brad Herner
  • Patent number: 7488386
    Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7452792
    Abstract: The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: November 18, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Nicolas Daval, Zohra Chahra, Romain Larderet
  • Patent number: 7374617
    Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7357838
    Abstract: A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: April 15, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu, Fu-Liang Yang, Shih-Chang Chen, Mong-Song Liang, Liang-Gi Yao
  • Patent number: 7306670
    Abstract: In the case of the epitaxial growth according to the prior art, a number o strips often have to be produced in a plane in order to restore an area to be repaired. This leads to overlapping and misorientation of the crystalline structures. In the case of the method according to the invention, the strip is of such a width that no overlapping occurs, since the width is adapted to the contour of the area to be repaired.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Beck, Georg Bostanjoglo, Nigel-Philip Cox, Rolf Wilkenhöner
  • Patent number: 7147709
    Abstract: The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: December 12, 2006
    Assignee: Silicon Genesis Corporation
    Inventors: Philip Ong, Francois Henley, Igor Malik
  • Patent number: 7105052
    Abstract: An ordered array of magnetized nanorods includes a plurality of metallic nanorods generally cylindrical in shape and including a nickel portion coated with a positively charged polyelectrolyte and a gold portion coated with an alkanethiolate; and a layer of a hardened polymer wherein each individual nanorod of the plurality is held by having said gold portion embedded therein so that the nickel portion extends approximately perpendicularly away from the layer of hardened polymer, and wherein said plurality of metallic nanorods is ordered in the array by having substantially all individual nanorods of the plurality of nanorods oriented generally parallel to each other.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: September 12, 2006
    Assignee: The Florida State University Research Foundation, Inc.
    Inventor: Joseph B. Schlenoff
  • Patent number: 7041170
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: May 9, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 6890835
    Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly seletive etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts of the SiGe/Si heterojunction diodes.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, David R. DiMilia, Lijuan Huang
  • Patent number: 6887441
    Abstract: Bulk Aluminum Antimonide (AlSb)-based single crystal materials have been prepared for use as ambient (room) temperature X-ray and Gamma-ray radiation detection.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: May 3, 2005
    Assignee: The Regents of the University of California
    Inventors: John W. Sherohman, Arthur W. Coombs, III, Jick H. Yee
  • Patent number: 6881259
    Abstract: Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: April 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Jack Oon Chu, Basanth Jagannathan, Ryan W. Wuthrich
  • Patent number: 6849120
    Abstract: The present invention provides an improved process for preparing modafinil, whereby it may be isolated in high purity by a single crystallization. The process produces modafinil free of sulphone products of over-oxidation and other byproducts. The invention further provides new crystalline Forms II-VI of modafinil and processes for preparing them. Each of the new forms is differentiated by a unique powder X-ray diffraction pattern. The invention further provides pharmaceutical compositions containing novel modafinil Forms II-IV and VI.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 1, 2005
    Assignee: Teva Pharmaceutical Industries Ltd.
    Inventors: Claude Singer, Neomi Gershon, Arina Ceausu, Anita Lieberman, Judith Aronhime
  • Patent number: 6830617
    Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that promotes the crystallization of silicon, an influence of this metal element can be suppressed. A nickel element 104 is retained in contact with a surface of an amorphous silicon film 103 patterned to form a predetermined pattern in such a manner that the metal element is brought into contact with the amorphous silicon film 103 patterned to form a predetermined pattern. Next, the crystalline silicon film 105 is formed by a heat treatment. At this time, the nickel element is segregated in the edge region of the pattern. Further, a crystalline silicon film 100 having no region to which the metal element concentrated by patterning using a mask 107. By using this crystalline silicon film 100 as an active layer, the thin film transistor is fabricated.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto, Shunpei Yamazaki
  • Patent number: 6764546
    Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: July 20, 2004
    Assignee: ASM International N.V.
    Inventor: Ivo Raaijmakers
  • Patent number: 6719841
    Abstract: A method of fabricating a high-density magnetic data-storage medium, the method comprising the steps of: (a) forming a plurality of nanodots of non-magnetic material in a regular array on a surface of a substrate, said array being notionally dividable into a plurality of clusters that each comprise a plurality of nanodots, wherein each nanodot of a said cluster overlaps with neighbouring nanodots of that cluster to form a well between them; (b) depositing magnetic material onto said substrate to at least partly fill the wells of each cluster; and (c) removing material to reveal a regular array of wells filled with magnetic material, each of said wells being separated from neighbouring wells by non-magnetic material.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: April 13, 2004
    Assignee: Data Storage Institute
    Inventors: Yunjie Chen, Jian-Ping Wang
  • Patent number: 6689211
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: February 10, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein, Gianna Taraschi
  • Patent number: 6660393
    Abstract: A B-doped Si1−x−yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1−x−yGexCy layer 102 is annealed to form a B-doped Si1−x−yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: December 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tohru Saitoh, Yoshihiko Kanzawa, Katsuya Nozawa, Minoru Kubo
  • Patent number: 6656573
    Abstract: Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: December 2, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yong Chen, R. Stanley Williams, Douglas A. A. Ohlberg
  • Patent number: 6569240
    Abstract: After an underlying layer, made of a single crystal metal material, has been formed on a semiconductor layer, part or all of the underlying layer is changed into a metal oxide layer by supplying oxygen thereto from above the underlying layer. Then, a ferroelectric or high-dielectric-constant film is further formed on the metal oxide layer. Since the film made of a metal material is formed on the semiconductor layer, a silicon dioxide film or the like is not formed easily. Thus, a dielectric film, which includes an underlying layer with a high dielectric constant and has a large capacitance per unit area, can be obtained. Various defects such as interface states in the semiconductor layer can also be reduced advantageously if these process steps are performed after a thermal oxide film has been formed on the semiconductor layer.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: May 27, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nishikawa, Kenji Iijima
  • Patent number: 6524651
    Abstract: A stable oxidized structure and an improved method of making such a structure, including an improved method of making an interfacial template for growing a crystalline metal oxide structure, are disclosed. The improved method comprises the steps of providing a substrate with a clean surface and depositing a metal on the surface at a high temperature under a vacuum to form a metal-substrate compound layer on the surface with a thickness of less than one monolayer. The compound layer is then oxidized by exposing the compound layer to essentially oxygen at a low partial pressure and low temperature. The method may further comprise the step of annealing the surface while under a vacuum to further stabilize the oxidized film structure. A crystalline metal oxide structure may be subsequently epitaxially grown by using the oxidized film structure as an interfacial template and depositing on the interfacial template at least one layer of a crystalline metal oxide.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: February 25, 2003
    Assignee: Battelle Memorial Institute
    Inventors: Shupan Gan, Yong Liang
  • Patent number: 6521041
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: February 18, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein
  • Patent number: 6511539
    Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: January 28, 2003
    Assignee: ASM America, Inc.
    Inventor: Ivo Raaijmakers
  • Publication number: 20010003269
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.
    Type: Application
    Filed: April 9, 1999
    Publication date: June 14, 2001
    Inventors: KENNETH C. WU, EUGENE A. FITZGERALD, JEFFREY T. BORENSTEIN
  • Patent number: 6228166
    Abstract: In order to reduce boron concentration between a silicon substrate and an Si or Si1-xGex layer which is epitaxially grown in a CVD (chemical vapor deposition) apparatus, the silicon substrate is pretreated, before being loaded into the CVD apparatus, such as to prevent the substrate from being contaminated by boron in a clean room. Further, in accordance with one embodiment, a CVD growth chamber itself is cleaned, before the substrate is loaded into the growth chamber, using an F2 gas at a predetermined temperature of the substrate, thereby to remove boron residues in the growth chamber.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventors: Tatsuya Suzuki, Tohru Aoyama
  • Patent number: 6143659
    Abstract: A method for forming an Al layer using an atomic layer deposition method is disclosed. First, a semiconductor substrate is loaded into a deposition chamber. Then, an Al source gas is supplied into the deposition chamber and the Al source gas is chemisorbed into the semiconductor substrate to form the Al layer. Next, a purge gas is supplied onto the deposition chamber without supplying the Al source gas so that the unreacted Al source gas is removed, thereby completing the Al layer. To form an Al layer to a required thickness, the step of supplying the Al source gas and the step of supplying the purge gas are repeatedly performed, thereby forming an Al atomic multilayer. Therefore, the uniformity and step coverage of the Al layer can be greatly improved.
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: November 7, 2000
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Hyeun-seog Leem
  • Patent number: 6143070
    Abstract: The present invention describes the growth of single crystals of non-congruently melting alloys, in particular, silicon-germanium of constant composition in a quartz ampoule by the use of CaCl.sub.2 as an encapsulant for the liquid encapsulated zone melting (LEZM) technique. The zone melting process was modified with the addition of calcium chloride which acts as a liquid encapsulant at temperatures above 660.degree. C. so that the crystal can grow without sticking to the container. The calcium chloride encapsulant creates a non-wetting buffer layer between the quartz container and the SiGe charge material allowing single crystal growth of mixed alloys. The crystal growth system consists of a vertical tube RF furnace with a water cooled split-ring concentrator. The concentrator is 5 mm. Thick by 25 mm diameter and provides a high temperature melt zone with a "spike" profile.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 7, 2000
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: David F. Bliss, Brian G. Demczyk, John Bailey
  • Patent number: 6039803
    Abstract: A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi on the substrate. A semiconductor structure including a monocrystalline silicon substrate having a (001) crystallographic surface orientation, the substrate being off-cut to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and a relaxed graded layer of a crystalline GeSi which is epitaxially grown on the substrate.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: March 21, 2000
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Srikanth B. Samavedam
  • Patent number: 6037614
    Abstract: Sn.sub.x Ge.sub.1-x alloys that are substantially free of compositional inhomogeneities and Sn segregation, and have a measurable direct band gap. Methods for making the Sn.sub.x Ge.sub.1-x alloys are also disclosed.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: March 14, 2000
    Assignee: California Institute of Technology
    Inventors: Gang He, Harry A. Atwater
  • Patent number: 6022410
    Abstract: A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: February 8, 2000
    Assignee: Motorola, Inc.
    Inventors: Zhiyi Yu, Jun Wang, Ravindranath Droopad, Daniel S. Marshall, Jerald A. Hallmark, Jonathan K. Abrokwah
  • Patent number: 6007623
    Abstract: A method for producing a horizontal magnetic recording medium that has as its magnetic film a granular film with grains of a chemically-ordered FePt or FePtX (or CoPt or CoPtX) alloy in the tetragonal L1.sub.0 structure uses an etched seed layer beneath the granular film. The granular magnetic film reveals a very high magnetocrystalline anisotropy within the individual grains. The film is produced by sputtering from a single alloy target or cosputtering from several targets. The granular structure and the chemical ordering are controlled by means of sputter parameters, e.g., temperature and deposition rate, and by the use of the etched seed layer that provides a structure for the subsequently sputter-deposited granular magnetic film. The structure of the seed layer is obtained by sputter etching, plasma etching, ion irradiation, or laser irradiation. The magnetic properties, i.e., H.sub.c and areal moment density M.sub.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 28, 1999
    Assignee: International Business Machines Corporation
    Inventors: Jan-Ulrich Thiele, Dieter Klaus Weller
  • Patent number: 5882399
    Abstract: The aluminum <111> crystal orientation content of an aluminum interconnect layer or the copper <111> crystal orientation content of a copper interconnect can be maintained at a consistently high value during the processing of an entire series of semiconductor substrates in a given process chamber. To provide the stable and consistent aluminum <111> content, or the stable and consistent copper <111> content, it is necessary that the barrier layer structure underlying the aluminum or the copper have a consistent crystal orientation throughout the processing of the entire series of substrates, as well. We have determined that to ensure the consistent crystal orientation content of the barrier layer structure, it is necessary to form the first layer of the barrier layer structure to have a minimal thickness of at least about 150 .ANG., to compensate for irregularities in the crystal orientation which may by present during the initial deposition of this layer.
    Type: Grant
    Filed: August 23, 1997
    Date of Patent: March 16, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Kenny King-tai Ngan, Barry Hogan, Seshadri Ramaswami
  • Patent number: 5782997
    Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-X) Ge.sub.X is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 21, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Chen Cho, Hung-Yu Liu
  • Patent number: 5759898
    Abstract: A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Bruce A. Ek, Subramanian Srikanteswara Iyer, Philip Michael Pitner, Adrian R. Powell, Manu Jamndas Tejwani
  • Patent number: 5733370
    Abstract: A magnetic recording medium comprising a magnetic alloy layer having a bicrystal cluster microstructure and, hence, reduced medium noise, is formed by depositing a seed layer on a glass or a glass-ceramic material substrate, oxidizing the seed layer, depositing an underlayer, such as chromium, on the oxidized seed layer, whereby the underlayer exhibits a (200) crystallographic orientation. A magnetic alloy epitaxially grown on the underlayer having a (200) crystallographic orientation exhibits a bicrystal cluster microstructure.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: March 31, 1998
    Assignee: Seagate Technology, Inc.
    Inventors: Ga-Lane Chen, Qixu Chen