Abstract: A micromechanical structure in accordance with various embodiments may include: a substrate; and a functional structure arranged at the substrate; wherein the functional structure includes a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region; and wherein at least a section of the functional region has an elastic modulus in the range from about 5 GPa to about 70 GPa.

Abstract: A photoelectric conversion device has a silicon substrate which includes a first portion configured to perform photoelectric conversion, and a second portion which is arranged farther apart from a light receiving surface of the silicon substrate than the first portion and contains carbon. A first peak concentration as a carbon peak concentration in the second portion is not less than 1×1018 [atoms/cm3] and not more than 1×1020 [atoms/cm3], and a second peak concentration as an oxygen peak concentration in the second portion is not less than 1/1000 and not more than 1/10 of the first peak concentration.

Abstract: A method of processing a polycrystalline diamond element is disclosed. The method may include depositing a vaporized material over a selected portion of a polycrystalline diamond element to form a protective coating over the selected portion. The polycrystalline diamond element may include a polycrystalline diamond table. The method may also include exposing at least a portion of the polycrystalline diamond element to a leaching solution such that the leaching solution contacts an exposed surface region of the polycrystalline diamond table and at least a portion of the protective coating. The method may also include removing the polycrystalline diamond element from the leaching solution. The protective coating may be substantially impermeable to the leaching solution.

Abstract: A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Abstract: A wafer can be provided to include a single crystalline semiconductor material with a predetermined crystal orientation. The wafer can include a laser mark at a determined position on a front surface or on a back surface of the wafer, where the determined position is configured to indicate the predetermined crystal orientation of the single crystalline semiconductor material.

Abstract: The present invention consists of a method for imparting asymmetry to a truncated annular wafer by either rounding one corner of the orientation flat, or rounding one corner of a notch. This novel method of rounding corners impart a visual and/or tactile asymmetry which can be utilized by a person in order to differentiate between the two different sides of the wafer. This inventive wafer design and method for making an asymmetric wafer is especially useful in the field of semiconductor technology and may be used on sapphire crystal wafers or any other class of wafer.

Abstract: The present invention consists of a method for imparting asymmetry to a truncated annular wafer by either rounding one corner of the orientation flat, or rounding one corner of a notch. This novel method of rounding corners impart a visual and/or tactile asymmetry which can be utilized by a person in order to differentiate between the two different sides of the wafer. This inventive wafer design and method for making an asymmetric wafer is especially useful in the field of semiconductor technology and may be used on sapphire crystal wafers or any other class of wafer.

Abstract: The present invention consists of a method for imparting asymmetry to a truncated annular wafer by either rounding one corner of the orientation flat, or rounding one corner of a notch. This novel method of rounding corners impart a visual and/or tactile asymmetry which can be utilized by a person in order to differentiate between the two different sides of the wafer. This inventive wafer design and method for making an asymmetric wafer is especially useful in the field of semiconductor technology and may be used on sapphire crystal wafers or any other class of wafer.

Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body between the first and second surfaces. The voids can extend from the first surface to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate material, and then a first stratum of the microelectronic substrate above the separation region is separated from a second stratum of the microelectronic substrate below the separation region. The first stratum of the microelectronic substrate can be further separated into discrete microelectronic dies before the first stratum is separated from the second stratum. In one aspect of this embodiment, the substrate can support a film and microelectronic devices can be formed in the film and/or in the substrate.

Abstract: A micromechanical diaphragm is described which has a partially n-doped p-substrate on its surface and a top n-epitaxial layer, one or more n-epitaxial layers which are p-doped in the diaphragm area being arranged on the p-substrate.

Abstract: A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract: An identification indication is formed on a side surface of a semiconductor wafer, and thus even if various treatment processes are repeatedly conducted for forming a semiconductor circuit, or even by the wrapping treatment on the rear side of the wafer, the identification indication cannot disappear or become unclear so that the identification indication can be clearly recognized at least until the process for cutting the wafer into chips.

Abstract: A substrate beam 1b is formed so as to divide a membrane for enabling detection of an energy ray upon back illumination, there by suppressing distortion of the membrane and preventing defocus upon detection due to the distortion, or the like. The distance is set sufficiently short from each region of the membrane to a substrate frame or to the substrate beam, thereby decreasing substrate resistance and enabling high-speed reading operation.

Abstract: A silicon structure having little solar light beam reflection, which is suitable for a solar battery. On the entire surface of a quartz substrate, Mo is deposited at a thickness of approximately 51 &mgr;m to form a lower electrode. On the entire surface of the lower electrode, a p type silicon structure having a thickness of 30 to 40 &mgr;m comprising an aggregate of a plurality of columnar silicon members mainly comprising silicon and having random orientations is formed via a film mainly comprising silicon, using Si2Cl6 mixed with BCl3. On the surface of the p type silicon structure, P is diffused by a thermal diffusion method using POCl3 to form an n type region at the periphery of the columnar silicon members. On the entire surface of the p type silicon structure, a transparent electrode comprising indium-tin oxide having a thickness of 30 to 40 &mgr;m is formed, and an upper electrode comprising Al having a thickness of approximately 1 &mgr;m is formed on the transparent electrode.

Abstract: A system and method are disclosed for determining properties of a feature located at a surface of a substrate. A plurality of probe tips are operable to traverse a surface of the substrate and provide measurement data indicative of topographical features scanned thereby. The measurement data obtained from the plurality of probe tips is aggregated and processed to determine feature properties, such as may include line edge roughness and/or linewidth.

Abstract: A silicon wafer for epitaxial growth consisting of a highly boron-doped silicon single crystal wafer, an antimony-doped silicon single crystal wafer or a phosphorus-doped silicon single crystal wafer, which allows easy oxygen precipitation and exhibits high gettering ability in spite of its suppressed oxygen concentration, and an epitaxial silicon wafer in which an epitaxial layer grown by using the aforementioned wafer as a substrate wafer has an extremely low heavy metal impurity concentration are produced with high productivity and supplied. The present invention relates to a boron-doped silicon single crystal wafer having a resistivity of from 10 m&OHgr;·cm to 100 m&OHgr;·cm, an antimony-doped silicon single crystal wafer, or a phosphorus-doped silicon single crystal wafer, which are produced by slicing a silicon single crystal ingot grown by the Czochralski method with nitrogen doping.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.

Abstract: The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases.

Abstract: A method of forming a network of islands (124) of semiconductor material on an electrically insulating material (112), comprising: p1 a) the deposition of nucleation kernels (122) on the surface of the electrically insulating material, b) the formation of islands of semiconductor material (124) respectively on the nucleation kernels. In accordance with the invention, the deposition of the nucleation kernels is effected using at least one so-called distribution layer (116) made of a material having a substantially regular molecular structure, formed on the surface of the electrically insulating material (112), in order to distribute the nucleation kernels in a substantially regular fashion on the surface of the electrically insulating material.

Abstract: A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a thermal anneal to dissolve agglomerated vacancy defects present in a stratum extending from the front surface toward the center of the wafer. The annealed wafer is then heat-treated to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, conservation of resources and reduction of cost are realized by reuse of the wafer and the like. Carried out to achieve the above are a step of bonding a principal surface of a first substrate to a principal surface of a second substrate, the first substrate being Si substrate in which at least one layer of non-porous thin film is formed through a porous Si layer, a step of exposing the porous Si layer in a side surface of a bonding substrate comprised of the first substrate and the second substrate, a step of dividing the porous Si layer by oxidizing the bonding substrate, and a step of removing the porous Si and oxidized porous Si layer on the second substrate separated by the division of the porous Si layer.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A wafer marking is disclosed, which is represented by a large number of soft marks incorporated into a surface of a wafer. The soft marks each have a depth of at least 4 &mgr;m, an internal diameter of at least 50 &mgr;m and, in a particularly advantageous manner, a minimum gradient their surface of 0.2. These depressions can be proded, using appropriate technology, with depths of up to &mgr;m.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to establish a vacancy concentration profile within the wafer. The oxidized wafer is then cooled from the temperature of said oxidizing heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A surface layer portion of a silicon substrate is etched by using a mixed solution which contains ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a weight ratio of 1:(1.3 to 2.65):(275 to 433). The density of the etch pits which have occurred in a surface of the silicon substrate whose surface layer portion was etched by the etching step is measured. The crystal quality, etc. of the silicon substrate are evaluated before a process for manufacturing semiconductor devices using such silicon substrates, in order to avoid a lowering of the yields of the semiconductor devices.