Barrier Layer Stock Material, P-n Type Patents (Class 148/33)
  • Patent number: 10825837
    Abstract: Various embodiments provide a substrate processing apparatus for grinding a substrate, and a display device including a substrate in which a hole is formed in an edge of the substrate using the substrate processing apparatus. The substrate processing apparatus for processing a display substrate includes a body which, in operation, rotates, a cylindrical grinding part connected to the body, and a lateral groove formed in a surface of the cylindrical grinding part. The lateral groove is configured to accommodate the display substrate. Thus, it is possible to form a hole by grinding an edge of the display substrate so as to be matched with a designed value.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: November 3, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ik Hyun Kuon, Jeong Kweon Park, Ju Ik Hong, Jangcheol Kim, Jinwook Kwak
  • Patent number: 10770340
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 8, 2020
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang Wen, Shaohua Zhang, Yulei Jiang, Yanghui Sun, Guoqiang Yu
  • Patent number: 10707174
    Abstract: According to one embodiment, a semiconductor device includes a device region covered with a resin film and a dicing region extending along at least one side of the device region, the dicing region including at least a first lithography mark and a second lithography mark. The resin film includes a first dicing region portion which covers a portion of the dicing region between the first lithography mark and the second lithography mark.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki
  • Patent number: 10632438
    Abstract: Contamination of fluidized bed-produced polycrystalline granules by phosphorus is reduced by employing as seals and/or packings, graphite containing <500 ppmw of phosphorus.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 28, 2020
    Assignee: WACKER CHEMIE AG
    Inventors: Gerhard Forstpointner, Dirk Weckesser
  • Patent number: 10475637
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Ying-Ru Shih, Wen-Ching Hsu
  • Patent number: 10345252
    Abstract: The disclosed technology relates to a method of selecting a material composition and/or designing an alloy. In one aspect, a method of selecting a composition of a material having a target property comprises receiving an input comprising thermodynamic phase data for a plurality of materials. The method additionally includes extracting from the thermodynamic phase data a plurality of thermodynamic quantities corresponding to each of the materials by a computing device. The extracted thermodynamic quantities are predetermined to have correlations to microstructures associated with physical properties of the material. The method additionally includes storing the extracted thermodynamic quantities in a computer-readable medium. The method further includes electronically mining the stored thermodynamic quantities using the computing device to rank at least a subset of the materials based on a comparison of at least a subset of the thermodynamic quantities that are correlated to the target property.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: July 9, 2019
    Assignee: Scoperta, Inc.
    Inventors: Kenneth Vecchio, Justin Lee Cheney
  • Patent number: 10347473
    Abstract: A method for forming a high purity, copper indium gallium selenide (CIGS) bulk material is disclosed. The method includes sealing precursor materials for forming the bulk material in a reaction vessel. The precursor materials include copper, at least one chalcogen selected from selenium, sulfur, and tellurium, and at least one element from group IIIA of the periodic table, which may be selected from gallium, indium, and aluminum. The sealed reaction vessel is heated to a temperature at which the precursor materials react to form the bulk material. The bulk material is cooled in the vessel to a temperature below the solidification temperature of the bulk material and opened to release the formed bulk material. A sputtering target formed by the method can have an oxygen content of 10 ppm by weight, or less.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 9, 2019
    Assignees: The United States of America, as represented by the Secretary of the Navy, Sunlight Photonics Inc.
    Inventors: Vinh Q Nguyen, Jesse A. Frantz, Jasbinder S. Sanghera, Ishwar D. Aggarwal, Allan J. Bruce, Michael Cyrus, Sergey V. Frolov
  • Patent number: 10297520
    Abstract: A manufacturing method of a semiconductor device includes: forming a mark on a surface of a semiconductor wafer, at least a part of the mark being disposed in a planned-peripheral region, the planned-peripheral region being located around a respective planned-element region where a semiconductor element is to be formed; forming the semiconductor element in the planned-element region using the mark; forming a film that extends across a range including the planned-element region or the planned-peripheral region in the surface so as to cover at least a part of the mark with the film, after forming the semiconductor element; and after forming the film, cutting the semiconductor wafer along a dicing region, the dicing region located around the planned-peripheral region.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 21, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Katsutoshi Narita
  • Patent number: 10265832
    Abstract: An apparatus for edge grinding a glazing comprising a grinding wheel, rotatable about an axis, a groove in a circumference of the wheel and first and second orifices arranged on first and second sides of the plane of the groove, which form first and second jets of coolant directed substantially into the groove on first and second trajectories not in the plane of the groove. A corresponding process for edge grinding causes fewer sharp portions and fewer small fractures in the glazing edge than the prior art. A glazing manufactured by the apparatus or the process has higher edge strength than the prior art.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: April 23, 2019
    Assignee: PILKINGTON GROUP LIMITED
    Inventors: Lukasz Myl, Sebastian Hablasek
  • Patent number: 10094939
    Abstract: A semiconductor detector for detecting radiation comprises a first semiconductor part in which an electron and a hole are generated by incident radiation; a signal output electrode outputting a signal base on the electron or the hole; and a gettering part gettering impurities in the first semiconductor part. In addition, the semiconductor detector further comprises a second semiconductor part doped with a type of dopant impurities and having dopant impurity concentration higher than that of the first semiconductor part. The second semiconductor part is in contact with the first semiconductor part. The gettering part is in contact with the second semiconductor part and not in contact with the first semiconductor part.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 9, 2018
    Assignees: FONDAZIONE BRUNO KESSLER, HORIBA, LTD.
    Inventors: Antonino Picciotto, Pierluigi Bellutti, Maurizio Boscardin, Nicola Zorzi, Daisuke Matsunaga
  • Patent number: 10069065
    Abstract: Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arup Polley, Archana Venugopal, Robert Reid Doering, Luigi Colombo
  • Patent number: 10038070
    Abstract: A nitride semiconductor device according to the present invention includes a nitride semiconductor layer including an electron transit layer and an electron supply layer which is in contact with the electron transit layer and which has a composition different from that of the electron transit layer, a gate electrode on the nitride semiconductor layer and a gate insulating film between the gate electrode and the nitride semiconductor layer. A region whose depth is 250 nm from an interface between the gate insulating film and the gate electrode includes a region which has a deep acceptor concentration equal to or more than 1.0×1016 cm?3.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 31, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Taketoshi Tanaka, Minoru Akutsu, Norikazu Ito
  • Patent number: 9945048
    Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Hong Syue, Pu-Fang Chen, Shiang-Bau Wang
  • Patent number: 9929150
    Abstract: Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventor: Adrian Finney
  • Patent number: 9835570
    Abstract: An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: December 5, 2017
    Assignee: The United States of America as represented by the Administrator of NASA
    Inventors: Yeonjoon Park, Hyun Jung Kim, Jonathan R. Skuza, Kunik Lee, Glen C. King, Sang Hyouk Choi
  • Patent number: 9711353
    Abstract: An aspect of the present disclosure resides in a method for manufacturing a compound semiconductor epitaxial substrate including a substrate and a compound semiconductor epitaxial layer disposed on the substrate, the method including providing the substrate, heating a carrier gas, preparing a mixed gas by mixing the heated carrier gas with at least a portion of a source gas that is a source for the compound semiconductor epitaxial layer, the source gas having a lower temperature than the heated carrier gas, and forming the compound semiconductor epitaxial layer on the substrate by supplying the mixed gas onto the substrate.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 18, 2017
    Assignee: PANASONIC CORPORATION
    Inventor: Chiaki Kudou
  • Patent number: 9590172
    Abstract: A sensing device is provided. The sensing device includes a semiconductor layer, a first electrode and a second electrode, a first detection electrode and a second detection electrode, and at least one conductive pattern. The first electrode and the second electrode are disposed at opposite ends of the semiconductor layer. The first detection electrode and the second detection electrode are disposed at the other opposite ends of the semiconductor layer, wherein a virtual connection line is provided through the first detection electrode and the second detection electrode. The at least one conductive pattern is disposed on the semiconductor layer, wherein the conductive pattern does not overlap with the virtual connection line.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 7, 2017
    Assignee: Au Optronics Corporation
    Inventors: Chih-Che Kuo, Tokuro Ozawa, Koji Aoki, Chia-Wei Chang
  • Patent number: 9437522
    Abstract: A semiconductor device according to the present invention has a semiconductor module 2; a cooling unit 3, the semiconductor module 2 being joined to an upper surface of the cooling unit 3, and a pipe 14, 15 for circulating a refrigerant being fixed to a side surface 20, 22 of the cooling unit 3; and a resin mold layer 4 that covers outer peripheries of the semiconductor module 2 and the cooling unit 3. Further, a protruding portion 25, 26 that protrudes from the side surface 20, 22 of the cooling unit 3 and surrounds the pipe 14, 15 is provided on the side surface 20, 22 of the cooling unit 3.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 6, 2016
    Assignee: CALSONIC KANSEI CORPORATION
    Inventors: Toshikazu Yoshihara, Satoshi Tamagawa, Yasuyuki Oi, Hideki Kobayashi
  • Patent number: 9425347
    Abstract: A method of manufacturing a semiconductor substrate includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a first portion of a second semiconductor layer on the first semiconductor layer and the metallic material layer, removing the metallic material layer under the first portion of the second semiconductor layer by dipping the substrate in a solution, forming a second portion of the second semiconductor layer on the first portion of the second semiconductor layer, and forming a cavity in a portion of the first semiconductor layer located under where the metallic material layer was removed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: August 23, 2016
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 9362485
    Abstract: A vertical Hall Effect sensor assembly in one embodiment includes a first sensor with a first doped substrate, a first doped well, the first doped well having a doping opposite to the first doped substrate, a first endmost inner contact accessible at a first surface of the first sensor and located at a first end portion of the first doped well, a first intermediate inner contact accessible at the first surface and located between the first endmost inner contact and a second end portion of the first doped well, and a first electrode positioned on the first surface immediately adjacent to the first endmost inner contact and the first intermediate inner contact, the first electrode electrically isolated from the first doped well, and a first voltage source operably connected to the first electrode.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 7, 2016
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Rocznik
  • Patent number: 9349799
    Abstract: Disclosed are a method and a semiconductor device. The method includes implanting recombination center atoms via a first surface into a semiconductor body, and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 24, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef Georg Bauer, Mario Barusic, Oliver Humbel, Hans Millonig, Werner Schustereder
  • Patent number: 9337080
    Abstract: The present invention is a method for manufacturing an SOI wafer, including: implanting one or more gas ion selected from a hydrogen ion and a rare gas ion into a bond wafer composed of a semiconductor single crystal substrate from a surface of the bond wafer to form an ion-implanted layer; bonding the surface from which the ion is implanted into the bond wafer and a surface of a base wafer through an oxide film; and then delaminating the bond wafer at the ion-implanted layer by performing a delamination heat treatment with a heat treatment furnace to form the SOI wafer, wherein after the delamination heat treatment, a temperature of the heat treatment furnace is decreased to 250° C. or less at temperature-decreasing rate of less than 3.0° C/min, and then the SOI wafer and the bond wafer after delamination are taken out from the heat treatment furnace.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 10, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Isao Yokokawa, Toru Ishizuka
  • Patent number: 9212049
    Abstract: In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer (1) and an active layer wafer (6) which are bonded together with an oxide film (3) therebetween, each of the support wafer (1) and the active layer wafer (6) being a silicon wafer; a cavity (1b) formed in a bonding surface of at least one of the silicon wafers; and a gettering material (2) formed on a surface on a side opposite to the bonding surface.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 15, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiji Yoshikawa, Jyunichi Ichikawa, Yukihisa Yoshida
  • Patent number: 9190445
    Abstract: Provided is a semiconductor device having good properties. Particularly, the semiconductor device is provided which can improve imaging properties. The semiconductor device (CMOS image sensor) includes a plurality of pixels, each having a photodiode PD for generating a charge by receiving light, and a transfer transistor TX for transferring the charge generated by the photodiode PD. The semiconductor device further includes an active region AcTP with the photodiode, and an active region AcG located on an upper side of the region AcTP in the planar direction and having a contact Pg to which a ground potential is applied. A gettering region GET is disposed in the active region AcG.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 17, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tadashi Yamaguchi
  • Patent number: 9142616
    Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 22, 2015
    Assignee: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov
  • Patent number: 9087700
    Abstract: To provide an oxide semiconductor film which has high stability and does not easily cause variation in electric characteristics of a transistor, a transistor including the oxide semiconductor film in its channel formation region, and a highly reliable semiconductor device including the transistor. The oxide semiconductor film including indium includes a crystal part whose c-axis is substantially perpendicular to a surface of the oxide semiconductor film. In the crystal part, the length of a crystal arrangement part containing indium and oxygen on a plane perpendicular to the c-axis is more than 1.5 nm. Further, the semiconductor device includes the transistor including the oxide semiconductor film in its channel formation region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi
  • Patent number: 9076798
    Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8524012
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: September 3, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
  • Patent number: 8366967
    Abstract: Metal chalcogenide precursor solutions are described that comprise an aqueous solvent, dissolved metal formate salts and a chalcogenide source composition. The chalcogenide source compositions can be organic compounds lacking a carbon-carbon bond. The precursors are designed to form a desired metal chalcogenide upon thermal processing into films with very low levels of contamination. Potentially contaminating elements in the precursors form gaseous or vapor by-products that escape from the vicinity of the product metal chalcogenide films.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 5, 2013
    Assignee: Inpria Corporation
    Inventors: Douglas A. Keszler, Bejamin L. Clark
  • Patent number: 8278666
    Abstract: The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, Sean R. McLaughlin, Thomas J. Knight, Robert M. Young, Brian P. Wagner, David A. Kahler, Andre E. Berghmans, David J. Knuteson, Ty R. McNutt, Jerry W. Hedrick, Jr., George M. Bates, Kenneth Petrosky
  • Patent number: 8128756
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13 } gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: March 6, 2012
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
  • Patent number: 7879455
    Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %?Sb/(Sn+Sb)?48 wt %, 5 wt %?Ag<20 wt %, 3 wt %?Cu<10 wt %, and Ag+Cu?25 wt %.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Kazutoshi Itou
  • Patent number: 7727341
    Abstract: A gasket system is described and depicting having a gasket located between and sealing a cylinder head and a cylinder block. The gasket has a first metal layer and a second metal layer adjacent said first metal layer. The second metal layer has a bead region and a stopper region. At least a portion of the bead region has a predetermined tensile strength and a predetermined range of yield strength.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: June 1, 2010
    Assignee: Dana Automotive Systems Group, LLC
    Inventor: Frank W. Popielas
  • Patent number: 7704331
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: April 27, 2010
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 7662239
    Abstract: Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f), backward (b) or inward (u) with thermoplastic wax having a thickness of 10 ?m or less, grinding the as-grown wafers, lapping the ground wafers, polishing the lapped wafers into mirror wafers with a bevel of a horizontal width of 200 ?m or less and a vertical depth of 100 ?m or less.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: February 16, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Masato Irikura, Seiji Nakahata
  • Patent number: 7482068
    Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: January 27, 2009
    Assignees: Norstel AB, SiCED Electronics Development GmbH & Co. KG
    Inventors: Alexandre Ellison, Björn Magnusson, Asko Vehanen, Dietrich Stephani, Heinz Mitlehner, Peter Friedrichs
  • Patent number: 7344604
    Abstract: Disclosed herein is a LED and a lighting apparatus, which employs a LED as a light source of low power and high efficiency for an optical projection system. The lighting apparatus comprises a reflection part together with the LED, and enhances light emitting directionality of the LED, thereby generating parallel light or focused light suitable for the light source of the optical projection system. The LED comprises a negative electrode and a positive electrode formed on an identical plane with different stack constructions, thereby reducing the number of wires between the electrodes occupying a predetermined volume. In addition, the substrate and the electrodes are made of a transparent material to transmit light therethrough, so that the light source using the LED radiates light in all direction as in the light source using the arc discharge, without shielding the light at a rear side by the electrodes.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: March 18, 2008
    Assignee: LG Electronics Inc.
    Inventor: Chan Young Park
  • Patent number: 7220324
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: May 22, 2007
    Assignee: The Regents of the University of California
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 7186302
    Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: March 6, 2007
    Assignees: The Regents of the University of California, The Agency of Industrial Science and Technology
    Inventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James Stephen Speck, Steven P. Denbaars, Shuji Nakamura, Umesh Kumar Mishra
  • Patent number: 7118934
    Abstract: A porous substrate for epitaxial growth includes an underlying layer made of III-nitride semiconductor which is grown on a sapphire substrate, a void-formation preventive layer which is grown on the underlying layer, a porous III-nitride semiconductor layer and a porous metallic layer on the porous III-nitride semiconductor layer.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: October 10, 2006
    Assignee: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Masatomo Shibata
  • Patent number: 7101444
    Abstract: A semiconductor device includes at least one defect-free epitaxial layer. At least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on top of a surface of a first solid state material having a first thermal evaporation rate and a plurality of defects, where the surface comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects, the method including the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: September 5, 2006
    Assignee: NL Nanosemiconductor GmbH
    Inventors: Vitaly Shchukin, Nikolai Ledentsov
  • Patent number: 7011717
    Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1–60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 14, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
  • Patent number: 6997776
    Abstract: The invention relates to a process for producing a semiconductor wafer by simultaneous polishing of a front surface and a back surface of the semiconductor wafer with a polishing fluid between rotating polishing plates during a polishing run which lasts for a polishing time, the semiconductor wafer being located in a cutout in a carrier having a defined carrier thickness and being held on a defined geometric path, the semiconductor wafer having a starting thickness prior to polishing and a final thickness after polishing. The polishing time for the polishing run is calculated from data which include the starting thickness of the semiconductor wafer and the carrier thickness as well as the starting thickness and final thickness and the flatness of a semiconductor wafer which was polished during a polishing run preceding the present polishing run.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: February 14, 2006
    Assignee: Siltronic AG
    Inventors: Gunther Kann, Manfred Thurner, Karl-Heinz Wajand, Armin Deser, Markus Schnappauf
  • Patent number: 6924240
    Abstract: A low dielectric constant material having excellent water resistance comprising a borazine skeleton structure represented by any one of the formulas (2) to (4): wherein R1 to R4 are independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkyiphosphino group, or a group of the formula: Si(OR7)(OR8)(OR9), provided that at least one of R1 to R4 is not a hydrogen atom.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 2, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideharu Nobutoki, Teruhiko Kumada, Toshiyuki Toyoshima, Naoki Yasuda, Suguru Nagae
  • Patent number: 6884303
    Abstract: A wafer having a rounded edge is thinned to 100 microns or less, producing a tapered razor like edge. The edge is ground to blunt it and reduce danger to personnel and equipment during handling of the wafer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 26, 2005
    Assignee: International Rectifier Corporation
    Inventor: Richard Francis
  • Patent number: 6855996
    Abstract: An electronic device substrate structure including a substrate 2, a metal thin film 4 as a (111)-oriented film of a face-centered cubic structure or as a (0001)-oriented film of a hexagonal closest packed structure formed on the substrate 2, and a wurtzite type thin film 5 as a (0001)-oriented film of a wurtzite crystal structure formed on the metal thin film 4, wherein: each of the two thin films is a polycrystalline film containing at least two kinds of crystal grains different in direction of crystal orientation in the plane; when the metal thin film 4 is a (111)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <1-10> axes in the plane of the metal thin film 4; and when the metal thin film 4 is a (0001)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <11-20> axes in the plane of the metal thin film 4.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 15, 2005
    Assignee: TDK Corporation
    Inventors: Takao Noguchi, Hisatoshi Saitou, Hidenori Abe, Yoshinari Yamashita
  • Publication number: 20040149353
    Abstract: The invention provides a doped semiconductor powder comprising nanocrystals of a group IV semiconductor and a rare earth element, the rare earth element being dispersed on the surface of the group IV semiconductor nanocrystals. The invention also provides processes for the preparation of the above doped semiconductor powder, and a composite material comprising a matrix in which is dispersed a doped semiconductor powder.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Inventor: Steven E. Hill
  • Publication number: 20030176003
    Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm−3 at Al mole fractions up to 65% are obtained.
    Type: Application
    Filed: May 15, 2002
    Publication date: September 18, 2003
    Inventors: William J. Schaff, Jeonghyun Hwang
  • Patent number: 6525402
    Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: February 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Matsumoto, Hisato Oyamatsu, Takeo Nakayama, Yasuhiro Fukaura, Kunihiro Kasai, Masahiro Inohara
  • Patent number: RE46799
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita