Abstract: A method is disclosed for depositing a high-quality thin films of ultrawide bandgap oxide semiconductors at growth rates that are higher than possible using prior-art methods. Embodiments of the present invention employ LPCVD deposition using vapor formed by evaporating material as a precursor, where the material has a low vapor pressure at the growth temperature for the thin film. The vapor is carried to a reaction chamber by an inert gas, such as argon, where it mixes with a second precursor. The reaction chamber is held at a pressure that nucleation of the precursor materials occurs preferentially on the substrate surface rather than in vapor phase. The low vapor pressure of the material gives rise to growth rates on the substrate surface that a significantly faster than achievable using prior-art growth methods.

Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

Abstract: The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates.

Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

Abstract: A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract: A dielectric composition containing a crystalline phase represented by a general formula of Bi12SiO20 and a crystalline phase represented by a general formula of Bi2SiO5 as the main components. The dielectric composition contains preferably 5 mass % to 99 mass % of the Bi2SiO5 crystalline phase, and more preferably 30 mass % to 99 mass %.

Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate.

Abstract: An electronic device comprising a cover plate is disclosed. The cover plate comprises one or more sapphire layers, wherein at least one of the layers has a low level of inclusions.

Abstract: An electronic device comprising a cover plate is disclosed. The cover plate comprises at least one layer of modified sapphire having a dielectric constant that is higher than the dielectric constant of sapphire.

Abstract: An electronic device comprising a cover plate is disclosed. The cover plate comprises one or more sapphire layers having a thickness of less than 50 microns. Also disclosed are methods for preparing these ultrathin sapphire layers using an ion implantation/exfoliation method.

Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.

Abstract: Technologies pertaining to designing microsystems-enabled photovoltaic (MEPV) cells are described herein. A first restriction for a first parameter of an MEPV cell is received. Subsequently, a selection of a second parameter of the MEPV cell is received. Values for a plurality of parameters of the MEPV cell are computed such that the MEPV cell is optimized with respect to the second parameter, wherein the values for the plurality of parameters are computed based at least in part upon the restriction for the first parameter.

Abstract: A method of producing a silicon-on-insulator article, the method including: forming a first aluminum nitride layer thermally coupled to a first silicon substrate; forming a second aluminum nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminum nitride layers of the first and second substrates together so that the first and second aluminum nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminum nitride layers.

Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.

Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.

Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.

Abstract: A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the first side having a topology extending a first distance above the first side. A support member is attached to a second portion of the first side and extending a second distance above the first side, wherein the first distance is about the same as the second distance. In some exemplary embodiments, the support member is formed by applying adhesive to the second portion. The wafer is then spun to adjust the second distance.

Abstract: Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Abstract: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 1016 ?-cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300-1000° C.). The bond strength between the semiconductor layer (15) and the support substrate (20) is preferably at least 8 joules/meter2. The semiconductor layer (15) can include a hybrid region (16) in which the semiconductor material has reacted with oxygen ions originating from the glass or glass-ceramic.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.

Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

Abstract: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including functional groups; an epoxy resin (B); a phenolic epoxy resin curing agent (C); a photoreactive monomer (D), wherein the Tg of the cured material obtained by ultraviolet light irradiation is 250° C. or more; and a photoinitiator (E) which generates a base and a radical by irradiation with ultraviolet light of wavelength 200-450 nm.

Abstract: A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained.

Abstract: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 1016 ?-cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300-1000° C.). The bond strength between the semiconductor layer (15) and the support substrate (20) is preferably at least 8 joules/meter2. The semiconductor layer (15) can include a hybrid region (16) in which the semiconductor material has reacted with oxygen ions originating from the glass or glass-ceramic.

Abstract: A semiconductor comprises a compound (A) adsorbed on a surface of the semiconductor, the compound (A) having at least one lone electron pair and substantially not undergoing in oxidation-reduction reactions, wherein the presence of the compound (A) negatively changes a flat band potential of the semiconductor with reference to that when the compound is absent.

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second silicon substrates. A first thin layer of silicon dioxide is formed on one substrate and a second thicker layer of silicon dioxide is formed on the other substrate. A layer of rare earth is deposited, generally by evaporation, on the thicker layer of silicon dioxide. The rare earth layer is placed on the thin silicon dioxide layer and the structure is bonded by annealing to form a layer of rare earth silicon dioxide. A portion of the one substrate is removed to form a thin crystalline active layer on preferably the rare earth silicon dioxide layer, but potentially on the thicker silicon dioxide layer.

Abstract: A composite sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The composite sacrificial material includes a polymeric or oligomeric matrix with filler material mixed therein. The filler material may be particulate matter that may be used to modify one or more properties of the composite sacrificial material during semiconductor processing.

Abstract: A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5-10 ?. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

Abstract: A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 ?m and 10 ?m, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.

Abstract: A structure having a first part and at least one second part. The second part is electrically insulated from the first part and the parts are formed in the same wafer of a material. The first and second parts have the same thickness, extend in the same plane and have at least one mutually adjacent edge. The adjacent edges are separated by a spacing. In addition there is at least one joint of insulating material arranged in the spacing to make the first and second parts integral. The structure may be used for sensors and isolated circuits.

Abstract: According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region.

Abstract: A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not protected by the mask, leaving a wall thin enough to be imaged by TEM.

Abstract: The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.

Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract: A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a thermal anneal to dissolve agglomerated vacancy defects present in a stratum extending from the front surface toward the center of the wafer. The annealed wafer is then heat-treated to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon.

Abstract: A process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity of charge carriers within a silicon wafer includes forming a plurality of semiconductor zones in the surface; reducing surface recombination velocity of charge carriers within the silicon wafer by maintaining temperature below 100° C. while sequentially performing the steps of cleaning the surface to remove oxide; drying the surface by blowing a non-oxidizing gas thereon; directly applying a layer of lacquer onto the surface at a temperature below 100° C.; and drying the layer of lacquer at a temperature below 100° C. to generate an electrically non-conducting layer and reduce the surface recombination velocity of charge carriers within the silicon wafer in which the layer of lacquer contains halogen in a concentration of more than 0.1 volume %; and forming at least one conducting structure on the surface of the layer of lacquer.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer which is atop a semiconductor substrate. The buffer film layer comprises a material which is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure which covers the shallow trench corners is created.

Abstract: A bismuth silicate film (insulating film) 3 of Bi2SiO5 oriented predominantly in the direction of (100) is formed on a Si substrate 2 and a ferroelectric thin film 4 is formed on the bismuth silicate film 3 to create an MFIS structure having a c-axis-oriented ferroelectric thin film 4 formed with good reproducibility. A highly reliable thin film device is produced by applying the MFIS structure to a FET.

Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, conservation of resources and reduction of cost are realized by reuse of the wafer and the like. Carried out to achieve the above are a step of bonding a principal surface of a first substrate to a principal surface of a second substrate, the first substrate being Si substrate in which at least one layer of non-porous thin film is formed through a porous Si layer, a step of exposing the porous Si layer in a side surface of a bonding substrate comprised of the first substrate and the second substrate, a step of dividing the porous Si layer by oxidizing the bonding substrate, and a step of removing the porous Si and oxidized porous Si layer on the second substrate separated by the division of the porous Si layer.

Abstract: A method of making a wafer is provided. A first semiconductor film is formed onto a semiconductor substrate. An epitaxial film is formed onto an epitaxial wafer. The epitaxial wafer is placed with the epitaxial film on the first semiconductor film. The epitaxial film is debonded from the EPI wafer. The epitaxial film is bonded to the first semiconductor film.

Abstract: A method of processing a substrate, such as a semiconductor wafer, in a vacuum processing chamber includes the steps of depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases by flowing SiH4 into the chamber. Preferably, WSix is deposited on a semiconductor wafer using a mixture comprising WF6, dichlorosilane and a noble gas, and the chamber is subsequently purged of residual WF6 and dichlorosilane by flowing SiH4 into the chamber. A further method of processing a substrate in a vacuum processing chamber includes the step of conditioning the chamber by flowing SiH4 into the chamber prior to depositing a material on the surface of the substrate. Semiconductor wafers processed according to the inventive method are characterized by more uniform sheet resistance values and reduced film stress.