Abstract: Compositions useful for the selective removal by etching of silicon-germanium-containing materials relative to silicon-containing materials, from a microelectronic device having features containing these materials at a surface, the compositions containing hydrofluoric acid, acetic acid, hydrogen peroxide, and at least one additional acid that will improve performance as measured by one or more of an etching rate or selectivity and are tunable to achieve the required Si:Ge removal selectivity and etch rates.

Abstract: A method for preparation of orientation-patterned (OP) templates comprising the steps of: depositing a first layer of a first material on a common substrate by a far-from-equilibrium process; and depositing a first layer of a second material on the first layer of the first material by a close-to-equilibrium process, wherein a first assembly is formed. The first material and the second material may be the same material or different materials. The substrate material may be Al2O3 (sapphire), silicon (Si), germanium (Ge), GaAs, GaP, GaSb, InAs, InP, CdTe, CdS, CdSe, or GaSe. The first material deposited on the common substrate may be one or more electronic or optical binary materials from the group consisting of AlN, GaN, GaP, InP, GaAs, InAs, AlAs, ZnSe, GaSe, ZnTe, CdTe, HgTe, GaSb, SiC, CdS, CdSe, or their ternaries or quaternaries. The far-from-equilibrium process is one of MOCVD and MBE, and the close-to-equilibrium process is HVPE.

Abstract: A semiconductor device includes: a p type first semiconductor layer that contains acceptors as impurities; an n type second semiconductor layer that is provided on the first semiconductor layer and contains donors as impurities; and a p type first diffusion portion that includes a contact portion in contact with the first semiconductor layer, the contact portion containing acceptors whose concentration is higher than that in the first semiconductor layer.

Abstract: A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

Abstract: The present disclosure provides a light-emitting device. The light-emitting device comprises a substrate; a light-emitting stack which emits infrared (IR) light on the substrate; and a semiconductor window layer comprising AlGaInP series material disposed between the substrate and the light-emitting stack.

Abstract: Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process.

Abstract: Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process.

Abstract: In order to provide a light-emitting device having improved color rendering properties, a light-emitting device which uses a SiC fluorescent material comprises a first SiC fluorescent portion in which a donor impurity and an acceptor impurity are added and which is formed of a SiC crystal; a second SiC fluorescent portion which is formed of a SiC crystal in which the same donor impurity as the first SiC fluorescent portion and the same acceptor impurity as the first SiC fluorescent portion are added, and in which a concentration of the acceptor impurity is higher than the concentration of the acceptor impurity in the first SiC fluorescent portion and an emission wavelength is longer than that of the first SiC fluorescent portion; and a light-emitting portion that emits excitation light that excites the first SiC fluorescent portion and the second SiC fluorescent portion.

Abstract: A method for fabricating light emitting diode (LEDs) comprises providing a plurality of LEDs on a substrate wafer, each of which has an n-type and p-type layer of Group-III nitride material formed on a SiC substrate with the n-type layer sandwiched between the substrate and p-type layer. A conductive carrier is provided having a lateral surface to hold the LEDs. The LEDs are flip-chip mounted on the lateral surface of the conductive carrier. The SiC substrate is removed from the LEDs such that the n-type layer is the top-most layer. A respective contact is deposited on the n-type layer of each of the LEDs and the carrier is separated into portions such that each of the LEDs is separated from the others, with each of the LEDs mounted to a respective portion of said carrier.

Abstract: Some embodiments provide methods of processing wafers comprising: positioning a stacked wafer into a position to be ground, wherein the stacked wafer comprises a first wafer secured with a carrier-wafer, wherein the first wafer is secured with the carrier-wafer such that a surface of the first wafer is exposed to be ground; initiating a grinding of the first wafer while supported by the carrier-wafer; activating one or more sensors relative to the first wafer while grinding the first wafer; determining, while grinding the first wafer, a thickness of the first wafer separate from a thickness of the carrier-wafer as a function of data from the one or more sensors; determining whether the determined thickness of the first wafer has a predefined relationship with a first thickness threshold; and halting the wafer grinding when the thickness of the first wafer has the predefined relationship with the first thickness threshold.

Abstract: A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).

Abstract: A method of chemical mechanical polishing (CMP) a diamond containing surface includes providing a slurry including a plurality of particles, at least one oxidizer, and at least one acid, wherein the slurry has a pH?3 or pH greater than 11. At least an outer surface of the plurality of particles is softer than the diamond surface or the particles are diamond particles averaging less than (<)2 ?m in size. The diamond surface is pressed with respect to a polishing pad providing a Shore D Hardness less than 99 having the slurry in between while rotating the polishing pad relative to the diamond surface to form a smooth diamond surface having a root mean square (rms) surface roughness less than 15 nm.

Abstract: An image-sensor device includes a first semiconductor substrate. The image-sensor device further includes a second semiconductor substrate under the first semiconductor substrate. The first semiconductor substrate has a first dopant concentration less than a second dopant concentration of the second semiconductor substrate. A ratio of a first resistance of the first semiconductor substrate to a second resistance of the second semiconductor substrate is larger than or equal to about 100. The image-sensor device also includes a diffusion layer positioned between the first semiconductor substrate and the second semiconductor substrate. A ratio of a first thickness of the diffusion layer to a second thickness of the first semiconductor substrate ranges from about 0.1 to about 1.

Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.

Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.

Abstract: A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer, such as aluminum nitride (AlN), on the annealed substrate, and growing the non-polar m-plane III-nitride film on the nucleation layer using MOCVD.

Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.

Abstract: Disclosed herein is a LED and a lighting apparatus, which employs a LED as a light source of low power and high efficiency for an optical projection system. The lighting apparatus comprises a reflection part together with the LED, and enhances light emitting directionality of the LED, thereby generating parallel light or focused light suitable for the light source of the optical projection system. The LED comprises a negative electrode and a positive electrode formed on an identical plane with different stack constructions, thereby reducing the number of wires between the electrodes occupying a predetermined volume. In addition, the substrate and the electrodes are made of a transparent material to transmit light therethrough, so that the light source using the LED radiates light in all direction as in the light source using the arc discharge, without shielding the light at a rear side by the electrodes.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: An electronic device substrate structure including a substrate 2, a metal thin film 4 as a (111)-oriented film of a face-centered cubic structure or as a (0001)-oriented film of a hexagonal closest packed structure formed on the substrate 2, and a wurtzite type thin film 5 as a (0001)-oriented film of a wurtzite crystal structure formed on the metal thin film 4, wherein: each of the two thin films is a polycrystalline film containing at least two kinds of crystal grains different in direction of crystal orientation in the plane; when the metal thin film 4 is a (111)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <1-10> axes in the plane of the metal thin film 4; and when the metal thin film 4 is a (0001)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <11-20> axes in the plane of the metal thin film 4.

Abstract: A semiconductor device having a silicon single crystal substrate and a boron phosphide semiconductor layer containing boron and phosphorus as constituent elements on a surface of the silicon single crystal substrate is disclosed. The surface of the silicon single crystal substrate is a {111} crystal plane inclined at an angle of 5.0° to 9.0° toward a <110> crystal azimuth.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: The surface of a silicon substrate is covered with a natural oxide film having a thickness of several tens of angstroms. In an initial process, the natural oxide film is removed with hydrogen fluoride (HF) diluted with pure water to 10% (process(1)). The surface of the silicon substrate from which the oxide film has been removed is covered with hydrogen atoms. A large amount of plasma energy is applied to the silicon substrate in a process (2) for depositing a ZnO thin film thereon by sputtering. Hydrogen is dissociated by this energy at low temperature as well as a thin film buffer layer, in which an amorphous material and fine crystals are mixed, is formed by easing the difference of lattice intervals between silicon and zinc oxide. Next, in a process (3), a ZnO thin film of high quality is formed on the buffer layer by MO-CVD using it as a seed crystal. With this arrangement, a zinc oxide semiconductor member suitable for a light receiving element can be formed on a silicon substrate.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer.

Abstract: A dramatic reduction of the dislocation density in GaN was obtained by insertion of a single thin interlayer grown at an intermediate temperature (IT-IL) after the growth of an initial grown at high temperature. A description of the growth process is presented with characterization results aimed at understanding the mechanisms of reduction in dislocation density. A large percentage of the threading dislocations present in the first GaN epilayer are found to bend near the interlayer and do not propagate into the top layer which grows at higher temperature in a lateral growth mode. TEM studies show that the mechanisms of dislocation reduction are similar to those described for the epitaxial lateral overgrowth process, however a notable difference is the absence of coalescence boundaries.

Abstract: The process consists in depositing, by chemical vapour deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450° C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.

Abstract: A method of manufacturing and testing a laser device that facilitates in-wafer testing of the laser device includes forming the laser device on a wafer and forming a light detecting device on the wafer adjacent to the laser device. The laser device should include a grating. The method further includes causing the laser device to lase while in the wafer and detecting light generated from the laser device with the light detecting device. Finally, the method includes obtaining an electro-optic parameter of the laser device from the detected light.

Abstract: An economical hybrid wafer utilizing a lower-quality, lower cost transfer substrate to support a higher-quality thin film. A high-quality thin film (2101) is separated from a donor wafer (2100) and bonded to a transfer, or target, substrate (46). The donor wafer is preferably single-crystal silicon optimized for device fabrication, while the transfer substrate provides mechanical support. The thin film is not grown on the transfer substrate, and thus defects in the transfer substrate are not grown into the thin film. A low-temperature bonding process can provide an abrupt junction between the target wafer and the thin film.

Abstract: A practical photolithographic process for use in manufacturing isolation structures in semiconductor substrates at the 0.18 &mgr;m scale uses an inorganic anti-reflective coating (ARC) layer, particularly silicon oxynitride, under a silicon nitride mask layer to minimize substrate reflectivity. The same ARC layer increases latitude in process conditions in photolithographic patterning of both a first mask layer and a second planarization mask level. The silicon oxynitride layer additionally reduces edge/corner stress in isolation structures, improving gate oxide integrity in the device of which the isolation structure forms a part. Furthermore, because silicon oxynitride and silicon nitride respond to the same process conditions, a silicon oxynitride ARC layer can be introduced without increasing process complexity.

Abstract: A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.