Amorphous Semiconductor Patents (Class 148/DIG1)
  • Patent number: 6124186
    Abstract: A method or producing hydrogenated amorphous silicon on a substrate, comprising the steps of: positioning the substrate in a deposition chamber at a distance of about 0.5 to 3.0 cm from a heatable filament in the deposition chamber; maintaining a pressure in said deposition chamber in the range of about 10 to 100 millitorr and pressure times substrate-filament spacing in the range of about 10 to 100 millitorr-cm, heating the filament to a temperature in the range of about 1,500 to 2,000.degree. C., and heating the substrate to a surface temperature in the range of about 280 to 475.degree. C.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: September 26, 2000
    Assignee: Midwest Research Institute
    Inventors: Edith C. Molenbroek, Archie Harvin Mahan, Alan C. Gallagher
  • Patent number: 5981326
    Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: November 9, 1999
    Inventor: Frank M. Wanlass
  • Patent number: 5946601
    Abstract: The present invention is a liner and/or barrier layer that will encapsulate the low k materials and act as a diffusion barrier between the low k material and the surrounding metal layers. As the temperatures of the processing sequence increase the liner and/or barrier layer will decrease the diffusion of fluorine from the low k material into the surrounding metal layers. Thus, the present invention will reduce potential corrosion problems of the metal layers.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: August 31, 1999
    Assignee: Intel Corporation
    Inventors: Lawrence D. Wong, Indrajit Banerjee, Steven Towie
  • Patent number: 5902650
    Abstract: A method of depositing an amorphous silicon based film that has controlled resistivity in between that of an intrinsic amorphous silicon and an n.sup.+ doped amorphous silicon on a substrate for an electronic device by a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: May 11, 1999
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: Jeff Feng, Robert Robertson, Kam Law
  • Patent number: 5894037
    Abstract: A silicon semiconductor substrate including a silicon semiconductor layer at one of upper and lower surfaces thereof, the silicon semiconductor layer being composed of polysilicon or noncrystal silicon and containing oxygen in the range of 2 atomic % to 20 atomic % both inclusive, nitrogen in the range of 4 atomic % to 20 atomic % both inclusive, or both nitrogen at 2 atomic % or greater and oxygen at 1 atomic % or greater. The polysilicon or noncrystal silicon semiconductor layer acts as a core for extrinsic gettering. In the silicon semiconductor substrate, the gettering performance is not deteriorated, even if the silicon semiconductor substrate experiences thermal treatment. Thus, it is possible to get rid of contamination caused by heavy metals in the silicon semiconductor substrate.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: April 13, 1999
    Assignee: NEC Corporation
    Inventors: Hiroaki Kikuchi, Seiichi Shishiguchi
  • Patent number: 5874129
    Abstract: A method of producing amorphous silicon layers on a substrate by chemical vapor deposition at elevated pressures of at least about 25 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain an amorphous silicon deposit of predetermined microcrystalline density, and the silicon precursor gases fed to the chamber to a preselected high pressure. Doped amorphous silicon films also can be deposited at high deposition rates.The above amorphous silicon films have a low density of nucleation sites; thus when the films are annealed, polycrystalline films having large crystal grains are produced.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: February 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mali Venkatesan
  • Patent number: 5863598
    Abstract: A method of forming a doped silicon film on a substrate. According to the present invention, a substrate is placed in a reaction chamber and heated. Next, a silicon containing gas is fed into the reaction chamber to produce a silicon containing gas partial pressure of between 4 and 20 torr.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: January 26, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Mahalingam Venkatesan, Shulin Wang, Vedapuram S. Achutharaman
  • Patent number: 5811323
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: September 22, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: 5789030
    Abstract: A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: August 4, 1998
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 5776819
    Abstract: A method of producing hydrogenated amorphous silicon on a substrate by flowing a stream of safe (diluted to less than 1%) silane gas past a heated filament.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: July 7, 1998
    Assignee: Midwest Research Institute
    Inventors: Archie Harvin Mahan, Edith C. Molenbroek, Brent P. Nelson
  • Patent number: 5700520
    Abstract: A method of producing doped and undoped silicon layers on a substrate by chemical vapor deposition at elevated pressures of from about 10 to about 350 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain a silicon deposit of predetermined crystallinity, and the silicon precursor gases fed to the chamber to a preselected high pressure. Both undoped and doped silicon can be deposited at high rates up to about 3000 angstroms per minute.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: December 23, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, David K. Carlson
  • Patent number: 5686320
    Abstract: The present invention relates to a method for manufacturing a thin film transistor which can improve the yield, characteristics and reliability of the thin film transistor by selectively forming a semiconductor layer on a desired portion of a substrate using a temperature difference on the surface of the substrate achieved by heating the substrate with a lamp. The method comprises the steps of forming a black matrix layer of metal on a portion of the whole surface of an insulating glass substrate, forming an insulating layer for protecting the substrate on the whole substrate including the black matrix layer, forming source/drain electrodes on the insulating layer over the black matrix, selectively forming a semiconductor layer on the insulating layer including the source/drain electrodes, forming a gate insulating layer and forming a gate electrode.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: November 11, 1997
    Assignee: Goldstar Co., Ltd.
    Inventor: Jeong Hyun Kim
  • Patent number: 5674777
    Abstract: The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: October 7, 1997
    Assignee: National Science Council
    Inventors: Tung-Po Chen, Tan-Fu Lei, Chun-Yen Chang
  • Patent number: 5648293
    Abstract: The invention provides a novel method of depositing an amorphous silicon film wherein a high frequency discontinuous discharge is carried out to decompose a silane system gas for a chemical vapor deposition for depositing an amorphous silicon film under conditions of a cyclic frequency of 500 Hz or more and a duty ratio of 30% or less.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: July 15, 1997
    Assignee: NEC Corporation
    Inventors: Hiroshi Hayama, Hiroyuki Uchida, Kazushige Takechi
  • Patent number: 5648287
    Abstract: A process for forming a MOS transistor having a salicide structure with a second gate spacers 36 and a source/drain/gate contact pads 32 33. A gate electrode 18 having first sidewall spacers 24 is formed on a substrate. Source and drain regions 28 are formed in the substrate. An amorphous silicon layer is formed over the substrate and patterned leaving the amorphous silicon layer over first sidewall spacers 24 and forming source/drain contact pads 33 over the source/drain regions and gate contact pads 32 over the gate electrode. Nitrogen ions are implanted vertically into the amorphous silicon layer 32 forming a nitrogen rich layer 34. The nitrogen rich layer 34 acts as an oxidation barrier source/drain an gate contact pads. The amorphous silicon layer 28 over the first sidewall spacer is oxidized using the nitrogen rich layer 34 as an oxidation barrier forming second gate spacers 36. A Ti layer is formed over the resultant surface.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: July 15, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chieh Tsai, Shie-Sen Peng
  • Patent number: 5614257
    Abstract: A method of producing amorphous silicon layers on a substrate by chemical vapor deposition at elevated pressures of at least about 25 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain an amorphous silicon deposit of predetermined microcrystalline density, and the silicon precursor gases fed to the chamber to a preselected high pressure. Doped amorphous silicon films also can be deposited at high deposition rates. The above amorphous silicon films have a low density of nucleation sites; thus when the films are annealed, polycrystalline films having large crystal grains are produced.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: March 25, 1997
    Assignee: Applied Materials, Inc
    Inventors: Israel Beinglass, Mali Venkatesan
  • Patent number: 5597741
    Abstract: A process for preparing a semiconductor device, in which a polycrystalline silicon film is formed on a monocrystalline semiconductor substrate and arsenic or phosphorus is injected as an impurity into the polycrystalline silicon film by an ion-injection method to make the polycrystalline silicon film an amorphous layer. The amorphous layer is heat-treated at a temperature of 600.degree. C. to 650.degree. C. to recrystallize the amorphous layer, thus forming a recrystallized layer having a grain size greater than that of the polycrystalline silicon film by solid phase growth. The recrystallized layer is heat-treated at a temperature of 800.degree. C. to 900.degree. C. to diffuse the impurity into the monocrystalline semiconductor substrate.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: January 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaru Sakamoto, Masakazu Morishita, Shigeru Nishimura
  • Patent number: 5585295
    Abstract: A method for forming an inverse-T gate lightly-doped drain (ITLDD) structure for deep sub-micron metal oxide semiconductor (MOS) transistors is disclosed. The present invention includes forming a gate oxide layer on a substrate, and forming stacked-amorphous-silicon layers on the gate oxide layer, where the stacked-amorphous-silicon layers comprise at least two layers. Next, a first dielectric layer is patterned on top of the stacked-amorphous-silicon layer by a photoresist mask, and then a lightly-doped source/drain regions is formed. Thereafter, all of the stacked-amorphous-silicon layers are removed except for the bottom amorphous polysilicon layer. A second dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and heavily-doped source/drain regions are formed. The bottom layer of the stacked-amorphous-silicon layers is and the gate oxide layer is removed using the spacer as an etch mask.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: December 17, 1996
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Shye-Lin Wu
  • Patent number: 5576060
    Abstract: A CVD process of forming a hydrogenated amorphous silicon film comprising not more than 40 atomic percent of hydrogen atoms is disclosed, which comprises introducing a silicon-containing gas and a gas containing impurity for controlling conductivity of said film into a film-forming space, wherein the concentration of the gas containing the impurity is controlled during film formation to vary the content of the impurity in the thickness direction of the amorphous silicon film.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 19, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yutaka Hirai, Toshiyuki Komatsu, Katsumi Nakagawa
  • Patent number: 5552027
    Abstract: A working electrode or an electrochemical-enzymatic sensor system has a metallic base body which is provided with a thin layer of amorphous hydrogenated carbon (a-C:H).
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: September 3, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Siegfried Birkle, Johann Kammermaier, deceased, Rolf Schulte
  • Patent number: 5531182
    Abstract: Polycrystalline silicon thin-films having a large grain size are formed by preparing a substrate of amorphous surface comprising first regions containing tin atoms at a higher content and second regions containing tin atoms at a lower content or not substantially containing them, and then heat-treating the substrate to grow crystal grains from crystal nuclei formed only in the first regions.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: July 2, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 5529937
    Abstract: After a pattern is transferred on silicon film crystallized by annealing, the silicon film is annealed by radiation of intense rays for a short time. Especially, in the crystallizing process by annealing, an element which promotes crystallization such as nickel is doped therein. The area not crystallized by annealing is also crystallized by radiation of intense rays and a condensed silicon film is formed. After a metal element which promotes crystallization is doped, annealing by light for a short time is performed by radiating intense rays onto the silicon film crystallized by annealing in an atmosphere containing halide. After the surface of the silicon film is oxidized by heating or by radiating intense rays in a halogenated atmosphere and an oxide film is formed on the silicon film, the oxide film is then etched. As a result, nickel in the silicon film is removed.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: June 25, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma, Yasuhiko Takemura
  • Patent number: 5518937
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: May 21, 1996
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5514618
    Abstract: A direct laser ablation process is disclosed for forming thin film transistors on liquid crystal matrix for enabling typically color presentation from a flat panel display. The thin film transistor is of the type having an active matrix addressing scheme wherein a capacitor when charged turns on and maintains in the "on" state a field effect transistor to permit passage of light through a liquid crystal display. All patterning of the display is done either by utilizing deposition, direct ablation of an etch block followed by etching, or more preferably deposition followed by direct laser ablation. In the preferred embodiment, aluminum channels are made by deposition followed by a direct laser ablation. Anodizing follows with deposition of a silicon-nitrogen layer. With respect to the capacitor, indium tin oxide is deposited to complete a matrix capable of selectively strobing and charging the capacitor for each matrix element.
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: May 7, 1996
    Assignee: Litel Instruments
    Inventors: Robert O. Hunter, Jr., Chester A. Farris
  • Patent number: 5491107
    Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: February 13, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Turner, Monte Manning
  • Patent number: 5488000
    Abstract: Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline silicon film having excellent crystailinity is obtained. TFTs are built, using this crystalline silicon film.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: January 30, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Satoshi Teramoto
  • Patent number: 5441914
    Abstract: In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: August 15, 1995
    Assignee: Motorola Inc.
    Inventors: Robert C. Taft, Craig D. Gunderson, Arkalgud R. Sitaram
  • Patent number: 5424230
    Abstract: An amorphous silicon hydride thin film is deposited on an insulating body by a plasma CVD method, and is then heated for dehydrogenating the amorphous silicon thin film so that a dehydrogenated amorphous silicon thin film containing hydrogen of 3 atomic % or less is formed. The insulating body may be an insulating substrate (such as a glass substrate) alone, or a combination of an insulating substrate with an intermediate insulating base layer thereon. Impurity ions are injected into the dehydrogenated amorphous silicon hydride thin film to form source and drain regions. Excimer laser beams are applied to the dehydrogenated amorphous silicon thin film, thereby polycrystallizing the amorphous silicon thin film into a polysilicon thin film and activating the injected impurity ions.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: June 13, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventor: Haruo Wakai
  • Patent number: 5391518
    Abstract: To fabricate a programmable read only memory cell an implant region is formed within a substrate. A first conductive layer is formed over the substrate. For example, the first conductive layer is polysilicon. The first conductive layer is etched to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for a transistor. Atoms of a first conductivity type are implanted into the substrate into a first source/drain region on a first side of the gate region and into a second source/drain region on a second side of the gate region. The second source/drain region is electrically coupled to the implant region. An insulating layer is formed over the first electrode. The insulating layer has a link contact which extends to the first electrode region. The insulating layer also has a contact hole extending to the first source drain region. An amorphous silicon layer is formed within the link contact and in contact with the first electrode.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: February 21, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Bharat Bhushan
  • Patent number: 5366928
    Abstract: A method of manufacturing a semiconductor device is set forth comprising a semiconductor body (1) having a surface (2) adjoined by a semiconductor region (3) and a field oxide region (4) surrounding this region, on which surface (2) is provided a metal layer (13), in which a conductor track (17, 18) is formed, after which an isolating layer of silicon oxide (19) is deposited over the conductor track (17, 18) on the surface (2). According to the invention, before the layer of silicon oxide (19) is provided over the conductor track (17, 18), this track is provided with a top layer (16) of an oxidation-preventing material. By providing this top layer (16), it is avoided that the conductor track (17, 18) covered by silicon oxide (19) has a high electrical resistance or even an electrical interruption.
    Type: Grant
    Filed: June 4, 1993
    Date of Patent: November 22, 1994
    Assignee: U.S. Philips Corporation
    Inventors: Robertus A. M. Wolters, Alexander G. M. Jonkers
  • Patent number: 5366921
    Abstract: An electronic circuit apparatus which is constructed by laminating a plurality of thin films onto an insulative substrate. On the substrate, an electronic circuit element having two conductive layer which are laminated through an insulative layer is formed. The insulative layer is formed so as to cover the whole surface of the insulative substrate.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: November 22, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuaki Tashiro
  • Patent number: 5346833
    Abstract: An inverted staggered (bottom gate) thin film transistor (TFT) for active matrix liquid crystal display is processed with three masks. The first mask is used to pattern a metal film on a glass substrate as the gate of the TFT, the scan line of the TFT array, and a portion of the data line of the TFT array. The second mask is used to form a TFT mesa with a gate dielectric layer, an a-Si layer as channel, and a heavily-doped n+s-Si layer for contacting the source and the drain of the TFT. A third mask is used to pattern the transparent conductive indium-tin oxide film as the pixel electrode, the source/drain electrodes of the TFT, and the interconnections of the data line.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: September 13, 1994
    Assignee: Industrial Technology Research Institute
    Inventor: Biing-Seng Wu
  • Patent number: 5326712
    Abstract: A method for manufacturing a semiconductor device which utilizes anodic oxidation. A first semiconductor layer of a first conductive type is formed on an insulating substrate, a highly doped second semiconductor layer of the first conductive type is formed on the first semiconductor layer, and then an anti-oxidizing pattern is formed on the second semiconductor layer to expose a predetermined portion of the second semiconductor layer. After forming the anti-oxidizing pattern, anodic oxidation is performed to oxidize the exposed portion of the second semiconductor layer. Instead of employing a conventional plasma etching process for removing the portion of the ohmic contact layer which is not in contact with the source and drain electrodes, the portion of the ohmic contact layer to be removed is subjected to anodic oxidation, to thereby form an anodic oxidation layer, thus facilitating removal of the unnecessary portions of the ohmic contact layer without the use of a plasma etching step.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: July 5, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-seong Bae
  • Patent number: 5318920
    Abstract: A silicon layer having semispherical protrusions of about 100 nm is formed as a lower electrode of a capacitor by low pressure vapor deposition method. A silicon oxide film is formed by oxidizing the surface of this silicon layer. The intervals between the rough portions of the silicon layer are increased by removing this silicon oxide film. Thereafter, a dielectric layer and an upper electrode are formed. In other methods, after the formation of the silicon layer having the roughness, thermal treatment is continuously carried out in oxygen-free atmosphere to increase radius of curvature of the roughness of the silicon layer. Thereafter, the dielectric layer and the upper electrode are formed.
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: June 7, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Hayashide
  • Patent number: 5310698
    Abstract: In a multistage process for producing a smooth polycrystalline silicon layer, in particular a layer with low arsenic doping, for very large scale integrated circuits, by thermal decomposition of gaseous compounds containing the elements, a doped layer and an undoped silicon layer above the doped layer are deposited directly one after the other in a two-stage process. Initially, a surface-covering arsenic layer being at most a few atoms thick, is deposited as a preliminary lining. Then an undoped amorphous silicon layer is deposited on the arsenic layer at a temperature of less than 580.degree. C. Subsequently, the silicon layer is uniformly doped with the arsenic layer serving as a diffusion source, by temperature treatment. Simultaneously, the amorphous silicon is made into a polycrystalline silicon layer.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: May 10, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Barbara Wild
  • Patent number: 5302549
    Abstract: A metal semiconductor ohmic contact farming process consists of enrichment of the surface of the semiconductor on which contact is to be formed, by ion implantation of a dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature lower than 500.degree. C. and for a period shorter than 60 minutes.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: April 12, 1994
    Assignee: SGS-Thompson Microelectronics S.r.L.
    Inventors: Antonello Santangelo, Carmelo Magro, Guiseppe Ferla, Paolo Lanza
  • Patent number: 5296405
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: March 22, 1994
    Assignee: Semiconductor Energy Laboratory Co.., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5290734
    Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: March 1, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani
  • Patent number: 5290729
    Abstract: A lower electrode of a stacked capacitor in accordance with the present invention is formed of a silicon layer formed by low pressure CVD method. The silicon layer is formed by thermal decomposition of monosilane gas at a prescribed temperature. By setting partial pressure of the monosilane gas and formation temperature at prescribed values, the silicon layer is formed to be in a transitional state between poly crystal and amorphous. Such silicon layer has large concaves and convexes on the surface thereof. Consequently, opposing areas of the electrodes of the capacitor can be increased, and therefore electrostatic capacitance of the capacitor is also increased.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: March 1, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshio Hayashide, Wataru Wakamiya
  • Patent number: 5283207
    Abstract: A photoconductive material comprises a photocarrier generating zone using a wide-band gap material and a photocarrier moving zone using an amorphous silicon material. A photocarrier generating zone including a silicon atom as a principal atom comprises an amorphous silicon which contains at least one kind of atom selected from a group including oxygen, nitrogen and carbon and also contains an atom which terminates a dangling bond of a silicon. This photoconductive material can be used for various devices because of its wide-band gap and high photosensitivity.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: February 1, 1994
    Assignees: Ricoh Company, Ltd., Ricoh Research Institute of General Electronics Co., Ltd.
    Inventors: Koichi Haga, Masafumi Kumano
  • Patent number: 5281546
    Abstract: A method of fabricating a thin film transistor (TFT) including the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer over the gate conductor; depositing a layer of amorphous silicon over the gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+ doped silicon over the treated amorphous silicon surface such that an interface is formed between the amorphous silicon and the n+ doped layer that has relatively low contact resistance; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The TFT material layers are preferably deposited by plasma enhanced chemical vapor deposition.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: January 25, 1994
    Assignee: General Electric Company
    Inventors: George E. Possin, Robert F. Kwasnick, Brian W. Giambattista
  • Patent number: 5278093
    Abstract: A method for forming a semiconductor thin film comprises crystallizing an amorphous silicon thin film by a first thermal treatment at 700.degree. C. or lower for ten hours or longer and carrying out a second thermal treatment at 1200.degree. C. or higher in which a lamp light is radiated to the crystallized thin film.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: January 11, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 5278087
    Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: January 11, 1994
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Ching-Shi Jenq
  • Patent number: 5278096
    Abstract: A method of forming p.sup.+ transistor gates is disclosed. A polysilicon layer is covered with an amorphous silicide layer which prevents penetration of p-type dopants through the gate oxide. The silicide may be covered by a dielectric which is formed at a temperature low enough to prevent crystallization of the silicide, a p-type dopant species is directed at the silicide layer. Subsequently an anneal is performed at a temperature high enough to cause a substantial amount of the p-type dopant to move to the polysilicon layer.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: January 11, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Kuo-Hua Lee, Chen-Hua D. Yu
  • Patent number: 5273920
    Abstract: A method of fabricating a thin film transistor (TFT) includes the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer of silicon nitride over the gate conductor; treating the exposed silicon nitride on the surface of the gate dielectric layer with a hydrogen plasma at a power level of at least 44 mW/cm.sup.2 for at least 5 minutes; depositing a layer of amorphous silicon semiconductor material over the gate dielectric layer; depositing a layer of n+ doped silicon over the treated amorphous silicon surface; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The deposition of the TFT material layers and the hydrogen plasma treatment is preferably by plasma enhanced chemical vapor deposition.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: December 28, 1993
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin
  • Patent number: 5273919
    Abstract: A method of producing a thin film field effect transistor. An insulating thin film layer is formed on a gate electrode subsequent to the gate electrode being formed on a substrate. A multilayer structure is formed on the insulating thin film layer subsequent to the insulating thin film layer being formed on the gate electrode by alternately laminating a number of non-monocrystalline semiconductor material layers and a number of non-monocrystalline material layers.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: December 28, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Sano, Katsuji Takasu, Hisanori Tsuda, Yutaka Hirai
  • Patent number: 5270227
    Abstract: An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as "voids 21" which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: December 14, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuichi Kameyama, Genshu Fuse
  • Patent number: 5266504
    Abstract: A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: November 30, 1993
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey L. Blouse, Jack O. Chu, Brian Cunningham, Jeffrey P. Gambino, Louis L. Hsu, David E. Kotecki, Seshadri Subbanna, Zu-Jean Tien
  • Patent number: 5262350
    Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semiconductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: November 16, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yujiro Nagata
  • Patent number: 5250451
    Abstract: Process for the local passivation of a substrate by a hydrogenated amorphous carbon layer and process for producing thin film transistors on said passivated substrate. The local passivation process consists of producing photosensitive resin patterns (3) on the substrate (1), subjecting the structure obtained to a radio-frequency plasma essentially constituted by a hydrocarbon for thus depositing a hydrogenated amorphous carbon layer (6) on the structure and dissolving the resin patterns (3) in order to eliminate the amorphous carbon deposited on the resin, the amorphous carbon deposited on the substrate constituting the said passivation.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: October 5, 1993
    Assignee: France Telecom Etablissement Autonome de Droit Public
    Inventor: Yannick Chouan