Amorphous Semiconductor Patents (Class 148/DIG1)
  • Patent number: 5250451
    Abstract: Process for the local passivation of a substrate by a hydrogenated amorphous carbon layer and process for producing thin film transistors on said passivated substrate. The local passivation process consists of producing photosensitive resin patterns (3) on the substrate (1), subjecting the structure obtained to a radio-frequency plasma essentially constituted by a hydrocarbon for thus depositing a hydrogenated amorphous carbon layer (6) on the structure and dissolving the resin patterns (3) in order to eliminate the amorphous carbon deposited on the resin, the amorphous carbon deposited on the substrate constituting the said passivation.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: October 5, 1993
    Assignee: France Telecom Etablissement Autonome de Droit Public
    Inventor: Yannick Chouan
  • Patent number: 5248630
    Abstract: A thin film silicon semiconductor device provided on a substrate according to the present invention comprises a thin polycrystalline silicon film having a lattice constant smaller than that of a silicon single crystal and a small crystal grain size. This thin polycrystalline silicon film can be obtained by depositing a thin amorphous silicon film in an inert gas having a pressure of 3.5 Pa or lower by a sputtering deposition method and annealing the thin amorphous silicon film for a short time of 10 seconds or less to effect polycrystallization thereof. A thin film silicon semiconductor device comprising such a thin polycrystalline silicon film having a small lattice constant has excellent characteristics including a carrier mobility of 100 cm.sup.2 /V.multidot.s or higher.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: September 28, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tadashi Serikawa, Seiichi Shirai, Akio Okamoto, Shirou Suyama
  • Patent number: 5238866
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) process for producing an amorphous semiconductive surface coating consisting essentially of hydrogenated silicon carbide (a-SiC:H) having an improved blood compatibility, the process including positioning a substrate to be coated in a reactor chamber; heating the substrate to a substrate temperature ranging from 0.degree. C. to 350.degree. C.; providing a flow of a reactive gas mixture including from about 50 to about 100% of methane (CH.sub.4), from about 0 to about 50%, of silane (SiH.sub.4), and from about 0 to about 2% of phosphine (PH.sub.3), the flow having a flow rate based on a flow rate of silane (SiH.sub.4) which ranges from 10 to 50 sccm, the methane (CH.sub.4) and the phosphine (PH.sub.3) having respective flow rates which are based on the flow rate of the silane (SiH.sub.4); introducing the flow of the reactive gas mixture into the reactor chamber to provide a process pressure ranging from 0.
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: August 24, 1993
    Assignee: GmbH & Co. Ingenieurburo Berlin Biotronik Mess- und Therapiegerate
    Inventors: Armin Bolz, Max Schaldach
  • Patent number: 5236850
    Abstract: A method of manufacturing a semiconductor film and a semiconductor device is disclosed. The method comprises the steps of:forming a non-single crystal semiconductor film on a surface by sputtering in an atmosphere comprising hydrogen; andcrystallizing the non-single crystal semiconductor film at a temperature of 450.degree. C. to 750.degree. C.
    Type: Grant
    Filed: September 18, 1991
    Date of Patent: August 17, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 5236872
    Abstract: A method of manufacturing a semiconductor device in which a thin buried silicide layer is formed by implantation includes the step of first forming an amorphous layer by implantation, which layer is then converted into the buried silicide layer by a heat treatment. A sufficiently thin buried silicide layer, of about 10 nm thickness, can be obtained in this manner, and the resulting structure is suitable, for example, for the manufacture of a metal-base transistor.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: August 17, 1993
    Assignee: U.S. Philips Corp.
    Inventors: Alfred H. van Ommen, Jozef J. M. Ottenheim, Erik H. A. Dekempeneer, Gerrit C. van Hoften
  • Patent number: 5231040
    Abstract: A semiconductor device constituting a high electron mobility transistor or metal semiconductor field effect transistor includes an n.sup.+ type InGaAs layer at an upper surface of the device, a source and a drain electrode on the n.sup.+ type InGaAs layer, as non-alloying ohmic contacts, a gate electrode produced of the same metal as the source and drain electrodes, and the gate electrode and the source and drain electrodes are self-aligningly positioned and separated from each other by L-shaped insulating films.
    Type: Grant
    Filed: January 23, 1992
    Date of Patent: July 27, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Teruyuki Shimura
  • Patent number: 5219767
    Abstract: Disclosed is a process for preparing a semiconductor device which comprises a step of growing, in a molecular beam epitaxial growth apparatus, a P-type silicon epitaxial layer which becomes the base, on an N-type silicon epitaxial layer which becomes the collector; a step of growing, in a molecular beam epitaxial growth apparatus, an antimony doped N-type silicon amorphous layer which becomes the emitter, on said P-type silicon epitaxial layer; and a step of converting the above N-type silicon amorphous layer to an N-type silicon epitaxial layer by the solid phase epitaxy method according to the annealing heat treatment.
    Type: Grant
    Filed: August 22, 1991
    Date of Patent: June 15, 1993
    Assignee: NEC Corporation
    Inventor: Hiroshi Kohno
  • Patent number: 5210050
    Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 .ANG. to 4 .mu.m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7.times.10.sup.19 atoms.multidot.cm.sup.-3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7.times.10.sup.19 atoms.multidot.cm.sup.-3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5.times.10.sup.18 atoms.multidot.cm.sup.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: May 11, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang
  • Patent number: 5180690
    Abstract: A method for the low temperature fabrication of doped polycrystalline semiconductor alloy material. The method includes the steps of exposing a body of semiconductor alloy material to a reaction gas containing at least a source of the dopant element, and establishing an electrical potential sufficient to sputter etch the surface of said layer, while decomposing the reaction gas. This allows for the deposition of a layer of doped amorphous semiconductor alloy material upon the body of semiconductor alloy material. Thereafter, the doped layer of amorphous semiconductor alloy material is exposed to an annealing environment sufficient to at least partially crystallize said amorphous material, and activate the dopant element.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: January 19, 1993
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Wolodymyr Czubatyj, Stanford R. Ovshinsky, Guy C. Wicker, David Beglau, Ronald Himmler, David Jablonski, Subhendu Guha
  • Patent number: 5171710
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: December 15, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5158903
    Abstract: A method for producing field-effect type semiconductor devices is disclosed which includes the steps of: forming a gate insulator film on a semiconductor substrate; forming a conductor film on the gate insulator film; and implanting impurity ions in the semiconductor substrate through the gate insulator film and the conductor film for the purpose of controlling a threshold voltage of the device, wherein the conductor film is employed as a gate electrode of the device. The method of this invention has the excellent advantages of readily controlling a threshold voltage of field-effect type semiconductor devices and of preventing the scatter of the threshold voltage values. An alternative embodiment employs formation of a second conductor film and implantation from an inclined direction.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: October 27, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Hori, Shuichi Kameyama, Hiroshi Shimomura, Mizuki Segawa
  • Patent number: 5151255
    Abstract: A method for forming a dihydride rich amorphous silicon semiconductor film suitable for use as a window material of solar cells only from a silicon material, which comprises decomposing a gaseous mixture composed of disilane, a dopant capable of imparting p-type electrical conductivity and a diluent gas by applying a glow discharge energy, and thereby forming a semiconductor film having an optical band gap of at least 1.8 eV, preferably more than 1.9 eV, on a substrate.
    Type: Grant
    Filed: October 3, 1990
    Date of Patent: September 29, 1992
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Nobuhiro Fukuda, Sadao Kobayashi, Kenji Miyachi, Hidemi Takenouchi, Yoji Kawahara, Takayuki Teramoto
  • Patent number: 5135886
    Abstract: A process for the formation of material layers such as amorphous silicon is disclosed. When a precursor gas such as silane is utilized to form amorphous silicon, silicon crystals are often formed on top of the amorphous silicon layer. The crystals are created by the presence of low pressure silane in the reactor at the end of the deposition cycle. Formation of crystals is inhibited by lowering the temperature before silane flow is terminated.
    Type: Grant
    Filed: December 6, 1990
    Date of Patent: August 4, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Ajit S. Manocha, Arun K. Nanda, Virendra V. S. Rana
  • Patent number: 5108936
    Abstract: A bipolar hetero-junction transistor has an emitter formed which consists of doped and hydrogenated semiconductor material which is at least partly in amorphous form. A high current gain (.beta.) is obtained due to the wide bandgap in the emitter material. Preferably, the layer forming the emitter consists of microcrystalline silicon which is doped and hydrogenated. This yields a small base resistance which is preferable for high frequency purposes. The amorphous bipolar hetero-junction transistor can be produced by a CVD-technique, by using a plasma or by photodissociation. The transistor having a microcrystalline emitter layer can be produced by one of the above methods or by heating an amorphous emitter layer.
    Type: Grant
    Filed: May 21, 1991
    Date of Patent: April 28, 1992
    Assignee: Interuniveritair Micro Elektronica Centrum
    Inventors: Moustafa Y. Ghannam, Robert Mertens, Johan Nijs
  • Patent number: 5102813
    Abstract: A thin film transistor is produced by applying onto a non-silicon foundation, a thin film of silicon semiconductor material under such conditions that polycrystalline or microcrystalline material is formed. Source and/or drain regions of doped semiconductor material are then formed onto the film; following by applying insulating material onto the film, and a gate region onto the insulating material. The source and/or drain regions are applied so that such regions have a crystalline structure that depends upon the crystalline structure of the underlying thin film. The resulting source and drain regions have high lateral conductivity so that source and drain contacts can be made with reduced cross-sectional areas. The method may employ a self-alignment process to simplify device production.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: April 7, 1992
    Assignee: Interuniversitair Micro Elektronica
    Inventors: Kazuhiro Kobayashi, Kris A. E. F. Baert, Johan F. A. Nijs
  • Patent number: 5075237
    Abstract: Disclosed is a process for making a thin film transistor photodetector which has the combined merits of the photodiode and the photoconductor without their problems. The resulting device of this process has an accumulation gate on the bottom of the active semiconductor layer and a transparent depletion gate on the top of the active semiconductor layer. The gate length of the depletion gate is smaller than that of the accumulation gate.
    Type: Grant
    Filed: July 26, 1990
    Date of Patent: December 24, 1991
    Assignee: Industrial Technology Research Institute
    Inventor: Biing-Seng Wu
  • Patent number: 5070030
    Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: December 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuyuki Sugahara, Shigeru Kusunoki, Kyusaku Nishioka
  • Patent number: 5055421
    Abstract: The invention provides a method for making a new semiconductor base material comprising thin layers of amorphous, hydrogenous carbon (a-c:H) with a specific electrical resistance of between 10.sup.1 and 10.sup.8 .OMEGA..cm and a charge carrier concentration (n+p) of between 10.sup.10 and 10.sup.18 cm.sup.-3, respectively at room temperature. The new semiconductor base material can be manufactured in thin layer technology with the application of band processes and exhibits a charge carrier mobility of at least 1 cm.sup.2.v.sup.-1.s.sup.-1.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: October 8, 1991
    Assignee: Siemens Aktiengesellschaft
    Inventors: Siegfried Birkle, Johann Kammermaier, Rolf Schulte, Albrecht Winnacker, Gerhard Rittmayer
  • Patent number: 5049523
    Abstract: In a gaseous glow-discharge process for coating a substrate with semiconductor material, a variable electric field in the region of the substrate and the pressure of the gaseous material are controlled to produce a uniform coating having useful semiconducting properties. Electrodes having concave and cylindrical configurations are used to produce a spacially varying electric field. Twin electrodes are used to enable the use of an AC power supply and collect a substantial part of the coating on the substrate. Solid semiconductor material is evaporated and sputtered into the glow discharge to control the discharge and improve the coating. Schottky barrier and solar cell structures are fabricated from the semiconductor coating. Activated nitrogen species is used to increase the barrier height of Schottky barriers.
    Type: Grant
    Filed: August 16, 1989
    Date of Patent: September 17, 1991
    Assignee: Plasma Physics Corp.
    Inventor: John H. Coleman
  • Patent number: 5021103
    Abstract: A microcrystalline silicon-containing silicon carbide semiconductor film has an optical energy gap of not less than 2.0 eV, and a dark electric conductivity of less than 10.sup.-6 Scm.sup.-1. The Raman scattering light of the microcrystalline silicon-containing silicon carbide semiconductor film, which shows the presence of silicon crystal phase, has a peak in the vicinity of 530 cm.sup.-1. This microcrystalline silicon-containing silicon carbide semiconductor film is formed on a substrate by preparing a mixture gas having a hydrogen dilution rate .gamma., which is the ratio of the partial pressure of hydrogen gas to the sum of the partial pressure of a silicon-containing gas and the partial pressure of a carbon-containing gas, of 30, transmitting microwave of a frequency of not less than 100 MHz into the mixture gas near a substrate with an electric power density of not less than 4.4.times.10.sup.-2, and generating plasma at a temperature of the substrate of not less than 200.degree. C.
    Type: Grant
    Filed: May 2, 1990
    Date of Patent: June 4, 1991
    Assignees: Nippon Soken, Inc., Nippondenso Co., Ltd., Yoshihiro Hamakawa
    Inventors: Yoshihiro Hamakawa, Hiroaki Okamoto, Yutaka Hattori
  • Patent number: 4988642
    Abstract: An improved semiconductor device manufacturing system and method is shown. In the system, undesirable sputtering effect can be averted by virtue of a combination of an ECR system and a CVD system. Prior to the deposition according to the above combination, a sub-layer can be pre-formed of a substrate in a reaction chamber and transported to another chamber in which deposition is made according to the combination without making contact with air, so that a junction thus formed has good characteristics.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: January 29, 1991
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4977098
    Abstract: A process for manufacturing a polysilicon-based bipolar semiconductor device, in particular an improved emitter contact configuration, eliminates native oxide anomalies at semiconductor interface regions, thus improving the characteristics of the emitter and its associated contact. Unwanted oxide is sputtered off the surface of a silicon substrate, so as to provide an effectively clean substrate surface. Next, a first amorphous silicon layer is formed on the surface of the substrate. Dopants are then implanted into the first amorphous silicon layer, to provide a source of diffusion impurities for forming an underlying (emitter) region. The resulting structure is then subjected to a rapid anneal which causes the impurities within the first amorphous silicon layer to diffuse into the substrate, forming the emitter region. Unwanted oxide that has been formed on the surface of the first amorphous silicon layer during the diffusion step is removed by sputtering.
    Type: Grant
    Filed: June 23, 1989
    Date of Patent: December 11, 1990
    Assignee: Korea Electronics & Communications Research Inst.
    Inventors: Hyunkyu Yu, Sangwon Kang, Jinhyo Lee
  • Patent number: 4963503
    Abstract: A liquid crystal display device comprises, a plurality of display electrodes which are selectively energized through on-off control of thin film transistors. In order to reduce the channel length of the thin film transistors to increase operation speed and obtain uniform characteristics each display electrode and an associated transistor source electrode is formed on one of a pair of transparent substrates of the liquid crystal display device, a semiconductor layer is formed between the display electrode and source electrode, a gate insulating film is formed on the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film between the display electrode and source electrode. Then, ions are implanted into the semiconductor layer with the gate electrode used as a mask, thus rendering portions of the semiconductor layer contiguous to the display electrode and source electrode into ohmic layers.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: October 16, 1990
    Assignee: Hosiden Electronics Co., Ltd.
    Inventors: Shigeo Aoki, Yasuhiro Ugai, Katsumi Miyake, Kotaro Okamoto
  • Patent number: 4950615
    Abstract: A technique is disclosed forming thin films (13) of group IIB metal-telluride, such as Cd.sub.x Zn.sub.1-x Te (0.ltoreq.x.ltoreq.1), on a substrate (10) which comprises depositing Te (18) and at least one of the elements (19) of Cd, Zn, and Hg onto a substrate and then heating the elements to form the telluride. A technique is also provided for doping this material by chemically forming a thin layer of a dopant on the surface of the unreacted elements and then heating the elements along with the layer of dopant.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: August 21, 1990
    Assignee: International Solar Electric Technology, Inc.
    Inventors: Bulent M. Basol, Vijay K. Kapur
  • Patent number: 4935383
    Abstract: A method for preparation of a dilute magnetic semiconductor (DMS) film is provided, wherein a Group II metal source, a Group VI metal source and a transition metal magnetic ion source are pyrolyzed in the reactor of a metalorganic chemical vapor deposition (MOCVD) system by contact with a heated substrate. As an example, the preparation of films of Cd.sub.1-x Mn.sub.x Te, wherein 0.ltoreq..times..ltoreq.0.7, on suitable substrates (e.g., GaAs) is described. As a source of manganese, tricarbonyl (methylcyclopentadienyl) maganese (TCPMn) is employed. To prevent TCPMn condensation during the introduction thereof int the reactor, the gas lines, valves and reactor tubes are heated. A thin-film solar cell of n-i-p structure, wherein the i-type layer comprises a DMS, is also described; the i-type layer is suitably prepared by MOCVD.
    Type: Grant
    Filed: September 23, 1988
    Date of Patent: June 19, 1990
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Akbar Nouhi, Richard J. Stirn
  • Patent number: 4908330
    Abstract: A process for the formation of a functional deposited film as a thin semiconductor film constituted with the group IV element or a thin semiconductor film constituted with group IV element alloy, by introducing, into a film forming space, a compound as the film-forming raw material and, if required, a compound containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of the compounds is activated, while forming hydrogen atoms in an excited state causing chemical reaction with at least one of the compounds in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film forming space, thereby forming a deposited film on a substrate, wherein the hydrogen atoms in the excited state are formed from a hydrogen gas or a gas mixture composed of a hydrogen gas and a rare gas by means of a microwave plasma generated in a plasma ge
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: March 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayoshi Arai, Masahiro Kanai, Soichiro Kawakami, Tsutomu Murakami
  • Patent number: 4888305
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, just formed semiconductor layer undergoes photo annealing and latent dangling bonds are let appear on the surface and gaps, then neutralizer is introduced to the ambience of the semiconductor. The semiconductor thus formed demonstrates SEL effect in place of Staebler-Wronski effect.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: December 19, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 4885258
    Abstract: There is provided an improved thin-film transistor of which a principal semiconducting layer comprises a layer composed of an amorphous material prepared by (a) introducing (i) a gaseous substance containing atoms capable of becoming constituents for said layer into a film forming chamber having a substrate for thin-film transistor through a transporting conduit for the gaseous substance and (ii) a gaseous halogen series substance having a property to oxidize the gaseous substance into the film forming chamber through a transporting conduit for the gaseous halogen series oxidizing agent, (b) chemically reacting the gaseous substance and the gaseous halogen series agent in the film forming chamber in the absence of a plasma to generate plural kinds of precursors containing exited precursors and (c) forming said layer on the substrate with utilizing at least one kind of those precursors as a supplier.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: December 5, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Ishihara, Hirokazu Ootoshi, Masaaki Hirooka, Junichi Hanna, Isamu Shimizu
  • Patent number: 4882295
    Abstract: Double injection field effect transistors, which may be horizontally or vertically arranged, each include a body of semiconductor material extending between two current-carrying electrodes and forming a current path therebetween. The semiconductor body of each may be substantially intrinsic or lightly doped. One or more control electrodes or gates located adjacent to each current path project a variable electric field over the ambipolar path, which modulates current by controlling the amount of charge carriers of both polarities injected into the semiconductor body. In most of the single gate embodiments, the electrodes extend across a portion, preferably a major portion such as 75% or 90%, or the length of the current path, but not the entire length of the current path. The embodiments having a plurality of gates typically have two insulated gates, one extending from the anode electrode and the other extending from the cathode electrode. The gates in a single device may overlap.
    Type: Grant
    Filed: March 27, 1989
    Date of Patent: November 21, 1989
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Wolodymyr Czubatyj, Michael G. Hack, Michael Shur
  • Patent number: 4873204
    Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.
    Type: Grant
    Filed: November 8, 1988
    Date of Patent: October 10, 1989
    Assignee: Hewlett-Packard Company
    Inventors: Siu-Weng S. Wong, Devereaux C. Chen, Kuang-Yi Chiu
  • Patent number: 4851302
    Abstract: There is provided a functional ZnSe:H deposited film composed of zinc atoms, selenium atoms, and at least hydrogen atoms, with the content of hydrogen atoms being 1 to 4 atomic % and the ratio of crystal grains per unit volume being 65 to 85 vol %. It is capable of efficient doping and is stable to irradiation. It can be made into a high conductivity p-type of n-type ZnSe:H:M film by doping. It can be efficiently deposited on a non-single crystal substrate such as metal, glass, and synthetic resin which was incapable of efficient depositing. Thus the invention makes it possible to form a high-functional device such as a photovoltaic element of ZnSe film on a non-single crystal substrate.
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: July 25, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Nakagawa, Shunichi Ishihara, Kozo Arao, Yasushi Fujioka, Akira Sakai, Masahiro Kanai
  • Patent number: 4847215
    Abstract: A method for forming a SiC film having a wide optical energy gap and a high conductivity, which is capable of being stacked on a substrate of a large area uniformly. The SiC film is formed by supplying a material gas composed of monosilane gas, methane gas, diboran gas and hydrogen gas and having a hydrogen dilution ratio of about 144 and carbon mixing ratio of about 0.35, to the substrate, and supplying rf power of 60 to 270W(rf power density=80 to 350mW/cm.sup.2) under a gas pressure of 0.2 torr at a substrate temperature of 220.degree. C. The obtained film exhibits high dark-conductivity of 10.sup.-6 Scm.sup.-1 or more, and a Raman spectrum light thereof peaks at around 520 cm.sup.-1.
    Type: Grant
    Filed: October 31, 1988
    Date of Patent: July 11, 1989
    Assignee: Nippon Soken, Inc.
    Inventors: Kenichi Hanaki, Hitomi Kitagawa, Takayuki Tominaga, Tadashi Hattori
  • Patent number: 4814292
    Abstract: In a process of fabricating a semiconductor device, an amorphous semiconductor layer is formed on a substrate, densified by heat-treatment, and is subjected to further heat-treatment to be changed into a polycrystalline semiconductor layer. A MOS transistor can be formed using the polycrystalline semiconductor layer.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: March 21, 1989
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masayoshi Sasaki, Teruo Katoh
  • Patent number: 4810637
    Abstract: A method of fabrication of non-linear control elements as applicable to electrooptical displays and in particular to large-area liquid-crystal displays of the flat-panel type, in which the following layers are stacked successively on a substrate: a first layer of metallic material, a first layer of undoped amorphous semiconductor material, a layer of doped amorphous semiconductor material, a second layer of undoped amorphous semiconductor material, and a second layer of metallic material.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: March 7, 1989
    Assignee: Thomson-Csf
    Inventors: Nicolas Szydlo, Jean N. Perbet, Rolande Kasprzak
  • Patent number: 4800174
    Abstract: A method of producing an amorphous silicon semiconductor device makes use of a capacitance-coupled high-frequency glow-discharge semiconductor production apparatus which is equipped with a plurality of glow-discharge chambers each having a high-frequency electrode and a substrate holder opposing each other and means for supplying material gases to the glow-discharge chambers. A reaction of a material gas is effected in a first glow-discharge chamber, so as to form a semiconductor layer having a first conductivity type on a substrate introduced into the first glow-discharge chamber, and, after moving the substrate into a second glow-discharge chamber, a reaction of a material gas different from the material gas used in the first glow-discharge chamber is effected, thereby forming a semiconductor layer having a second conductivity type on the semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: May 18, 1987
    Date of Patent: January 24, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Ishihara, Masatoshi Kitagawa, Takashi Hirao
  • Patent number: 4797108
    Abstract: An a-Si FET comprising electrically conductive source and drain regions supported by an insulating substrate; a layer of amorphous silicon which is separately deposited in a space between said source and drain regions so as to engage the source and drain regions; source and drain electrodes electrically connected with said source and drain regions respectively; a gate electrode disposed adjacent said layer of amorphous silicon; and an insulating layer separating the gate electrode from the amorphous silicon layer; the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer of amorphous silicon which is disposed in said space. A low cost, low-temperature substrate such as soda glass may be used and the a-Si FET may be of the thin film type. Such an a-Si FET can be used in an LCD device which is addressed using one or more of the FET's.
    Type: Grant
    Filed: December 10, 1986
    Date of Patent: January 10, 1989
    Assignee: Lucas Industries Public Limited Company
    Inventor: Simon N. Crowther
  • Patent number: 4789883
    Abstract: An improved electrically erasable programmable read only memory (EEPROM) integrated circuit structure and method for its fabrication is disclosed, having an enhanced interface between the floating gate electrode and the underlying tunnel oxide. The structure is capable of a relatively higher floating gate breakdown voltage and is less subject to charge migration from the floating gate and resultant charge trapping in the tunnel oxide. The improvements comprise forming the floating gate electrode from amorphous silicon and doping the silicon floating gate by implantation with a dopant, such as arsenic or phosphorus, under conditions wherein the doping agent will not easily migrate into the underlying tunnel oxide layer.
    Type: Grant
    Filed: December 17, 1985
    Date of Patent: December 6, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William P. Cox, Mong-Song Liang
  • Patent number: 4788157
    Abstract: A method for fabricating a thin-film transistor having a stagger structure, in which the inner portion of the amorphous silicon layer doped as an ohmic contact layer to source and drain areas is defined by an insulating layer interposed therebetween, a step for forming source and drain electrodes on said amorphous silicon layer, which comprises a film forming process for forming a metal layer; a thermal treatment process for heating so as to generate a surface reaction between said metal layer and said amorphous silicon layer in order to selectively form a reaction layer only on said amorphous silicon layer; and a patterning process for selectively removing said metal layer so as to form source and drain electrodes.
    Type: Grant
    Filed: April 28, 1987
    Date of Patent: November 29, 1988
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Takeshi Nakamura
  • Patent number: 4777150
    Abstract: There is described a process for the formation on a substrate of a refractory metal silicide layer, usable particularly for producing the interconnection layers of integrated circuits. This process consists of successively depositing on the substrate a first amorphous hydrogenated silicon layer, a second amorphous hydrogenated refractory metal layer, e.g. of tungsten, titanium, molybdenum or tantalum, and a third amorphous hydrogenated silicon layer. The thus coated substrate is then subjected to an annealing treatment at a temperature equal to or higher than 350.degree. C. in a hydrogen atmosphere. Preferably, following the deposition of the three layers, the coated substrate undergoes ionic implantation, e.g. using tungsten ions, for producing defects in the layers, which makes it possible to speed up the formation of the refractory metal silicide layer during the annealing stage.
    Type: Grant
    Filed: February 26, 1986
    Date of Patent: October 11, 1988
    Assignee: Centre de La Recherch Scientifique
    Inventors: Alain Deneuville, Pierre Mandeville
  • Patent number: 4769338
    Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.
    Type: Grant
    Filed: March 9, 1987
    Date of Patent: September 6, 1988
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, Stephen J. Hudgens
  • Patent number: 4762807
    Abstract: An insulated-gate field effect transistor (IGFET) having the structure of the source and drain disposed in the longitudinal direction, i.e., the laminating direction, so that the channel region extends in the lateral direction when a high voltage is applied. This structure prevents a high current density at the interface of the channel region and the gate insulation film, allowing the fabrication of a large-current power transistor or the integration of such transistors.
    Type: Grant
    Filed: August 13, 1986
    Date of Patent: August 9, 1988
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4746628
    Abstract: A thin film transistor (TFT) of a self-aligned structure, wherein a pair of a source electrode and a drain electrode are formed in alignment with a gate electrode and in contact with low resistance areas formed at both side portions of a semiconductor layer deposited on an insulating substrate. The low resistance areas are formed by the diffusion of metal atoms through heat-treatment.
    Type: Grant
    Filed: August 29, 1986
    Date of Patent: May 24, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Kohhei Kishi, Kohzo Yano
  • Patent number: 4737474
    Abstract: A process for forming a bonding layer comprising amorphous silicon, titanium, chromium, or tungsten, between the silicide and the N+ polysilicon layer is disclosed. The bonding layer is preferably less than 50 nm. thick. After the bonding layer is deposited, a silicide layer is deposited and the wafer is then sintered at 900.degree.-1000.degree. C. for ten minutes or less.
    Type: Grant
    Filed: November 17, 1986
    Date of Patent: April 12, 1988
    Assignee: Spectrum CVD, Inc.
    Inventors: J. B. Price, Yu C. Chow, John Mendonca, Schyi-Yi Wu
  • Patent number: 4704783
    Abstract: An organic or inorganic base solution is employed as a means for passivating the back channel region of an amorphous silicon FET device following plasma etching of the back channel region. The passivation provided significantly reduces back channel leakage currents resulting in FET devices which are compatible with conventional processing methods and which exhibit desirable properties for use in liquid crystal display systems.
    Type: Grant
    Filed: May 5, 1986
    Date of Patent: November 10, 1987
    Assignee: General Electric Company
    Inventors: George E. Possin, Harold G. Parks, William W. Piper
  • Patent number: 4689093
    Abstract: Process for preparing a photoelectromotive force member by forming a photoelectric conversion layer on a substrate by: (a) generating an active species by the action of microwave energy on a substance in a space leading to a film forming space containing a substrate; (b) generating a precursor by the action of microwave energy on a substance in a space situated within the space for generating the active species; and (c) introducing the resulting active species and precursor into the film forming space to chemically react them and to form the photoelectric conversion layer.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: August 25, 1987
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Ishihara, Keishi Saito, Shunri Oda, Isamu Shimizu
  • Patent number: 4677742
    Abstract: A method of making an electronic matrix array atop a non-conductive surface is disclosed. The method includes forming a first set of address lines on the non-conductive surface, depositing continuous layers of semiconductor materials atop the non-conductive surface and the first set of address lines to form a continuous selection means structure, and forming a second set of address lines over the selection means structure. In accordance with one preferred embodiment, the first set of address lines are formed by depositing a continuous layer of material which is convertible from an initially deposited non-conductive state to a conductive state responsive to the impingement of actinic radiation thereon and exposing selected portions of said convertible to actinic radiation.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: July 7, 1987
    Assignee: Energy Conversion Devices, Inc.
    Inventor: Robert R. Johnson
  • Patent number: 4597160
    Abstract: A method for making a TFT comprises forming an amorphous silicon layer having a smooth upper surface. An insulating layer is then formed on the smooth surface at or below the critical temperature for the instantaneous crystallization of amorphous. This slowly converts the amorphous silicon to polycrystalline silicon while retaining the smooth surface. TFTs incorporating the invention have a relatively high field effect (surface) mobility.
    Type: Grant
    Filed: August 9, 1985
    Date of Patent: July 1, 1986
    Assignee: RCA Corporation
    Inventor: Alfred C. Ipri
  • Patent number: 4589006
    Abstract: Passivation of predominantly crystalline semiconductor devices (12) is provided for by a surface coating (21) of sputtered hydrogenated amorphous semiconductor material. Passivation of a radiation detector germanium diode, for example, is realized by sputtering a coating (21) of amorphous germanium onto the etched and quenched diode surface (11) in a low pressure atmosphere of hydrogen and argon. Unlike prior germanium diode semiconductor devices (12), which must be maintained in vacuum at cryogenic temperatures to avoid deterioration, a diode processed in the described manner may be stored in air at room temperature or otherwise exposed to a variety of environmental conditions. The coating (21) compensates for pre-existing undesirable surface states as well as protecting the semiconductor device (12) against future impregnation with impurities.
    Type: Grant
    Filed: November 1, 1984
    Date of Patent: May 13, 1986
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: William L. Hansen, Eugene E. Haller
  • Patent number: 4565584
    Abstract: An amorphous or polycrystalline film which continuously covers the exposed surface of a single crystal substrate and an insulating film, is deposited in ultra-high vacuum and then heat-treated. The film is subjected to solid phase epitaxial growth at a temperature far lower than in prior-art methods, whereby a single crystal film is formed.
    Type: Grant
    Filed: January 25, 1983
    Date of Patent: January 21, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Masao Tamura, Makoto Ohkura, Masanobu Miyao, Nobuyoshi Natsuaki, Naotsugu Yoshihiro, Takashi Tokuyama, Hiroshi Ishihara