Oxidation, Selective Patents (Class 148/DIG117)
  • Patent number: 6162305
    Abstract: A method is provided for providing extra insulation between lead layers and first and second shield layers of a read head so as to prevent electrical shorting therebetween. A sensor layer is partially formed with a capping layer of a first oxidizable metallic layer. A lead layer is formed with a second oxidizable metallic capping layer thereon. A rear edge of the partially completed sensor is then formed followed by formation of an insulation layer which seals the rear edge. The wafer, upon which the components are constructed, is then subjected to an oxygen-based plasma which oxidizes the oxidizable layers with the second oxidizable metallic layers oxidizing at a faster rate than the first oxidizable metallic layer. The second oxidized layer then provides the desired extra insulation between the lead layers and the second shield layer. The read head produced by the method includes a sensor layer and first and second lead layers.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: December 19, 2000
    Assignee: International Business Machines Corporation
    Inventors: Richard Hsiao, Daniele Mauri, Neil Leslie Robertson
  • Patent number: 6096613
    Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: August 1, 2000
    Assignee: Acer Semiconductor Manufacturing Inc.
    Inventor: Shye-Lin Wu
  • Patent number: 5981326
    Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: November 9, 1999
    Inventor: Frank M. Wanlass
  • Patent number: 5861347
    Abstract: A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830.degree. C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: January 19, 1999
    Assignee: Motorola Inc.
    Inventors: Bikas Maiti, Wayne Paulson, James Heddleson
  • Patent number: 5696023
    Abstract: A method of forming a native oxide from an aluminum-bearing Group III-V semiconductor material is provided. The method entails exposing the aluminum-bearing Group III-V semiconductor material to a water-containing environment and a temperature of at least about 375 C to convert at least a portion of said aluminum-bearing material to a native oxide characterized in that the thickness of said native oxide is substantially the same as or less than the thickness of that portion of said aluminum-bearing Group III-V semiconductor material thus converted. The native oxide thus formed has particular utility in electrical and optoelectrical devices, such as lasers.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: The Board Of Trustees Of The University Of Illinois
    Inventors: Nick Holonyak, Jr., John M. Dallesasse
  • Patent number: 5646074
    Abstract: Disclosed is a process for manufacturing a gate oxide of a MOSFET. Since the performance of the gate oxide is deteriorated in photo resist removing, DI healing and high temperature annealing are introduced to recover the gate oxide. A process for manufacturing the gate oxide of the MOSFET on a wafer, includes the steps of: pre-cleaning the wafer, forming gate oxide layer, coating a photo resist, exposing the photo resist, developing the photo resist, implanting ions over the developed photo resist, removing the photo resist, post-cleaning the gate oxide for the purpose of good attachment of a gate polysilicon layer, DI healing the gate oxide, and annealing the gate oxide at a high temperature. As a result, the pass rates for Ebd and Qbd tests of the gate oxide increase.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 8, 1997
    Assignee: Mosel Vitelic, Inc.
    Inventors: Rickey Chen, Rex Chen
  • Patent number: 5643813
    Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: July 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: Joyce Elizabeth Acocella, Carol Galli, Louis Lu-Chen Hsu, Seiki Ogura, Nivo Rovedo, Joseph Francis Shepard
  • Patent number: 5587327
    Abstract: A process for preparing a bipolar transistor for very high frequencies is described, which is especially advantageous for the preparation of heterobipolar transistors and leads to components with low parasitic capacities and low base lead resistance. The process includes forming a structured first layer with collector zone and insulation areas surrounding the collector zone on a monocrystalline lead layer. A series of monocrystalline transistor layers are grown on the first layer over the collector zone by differential epitaxy and a series of polycrystalline layers is grown at the same time over the insulation areas. A series of polycrystalline layers is designed as a base lead.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 24, 1996
    Assignees: Daimler Benz AG, Temictelefunken Microelectronic GmbH
    Inventors: Ulf Konig, Andreas Gruhle, Andreas Schuppen, Horst Kibbel, Harry Dietrich, Heinz-Achim Hefner
  • Patent number: 5576226
    Abstract: A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: November 19, 1996
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyun S. Hwang
  • Patent number: 5554545
    Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: September 10, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Chung-Cheng Wu, Ming-Tzong Yang
  • Patent number: 5521107
    Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: May 28, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi, Hideki Nemoto
  • Patent number: 5496762
    Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: March 5, 1996
    Assignee: Micron Semiconductor, Inc.
    Inventors: Gurtej S. Sandhu, Trung T. Doan, David A. Cathey
  • Patent number: 5427971
    Abstract: This invention relates to a method for fabrication of MOS transistors having LDD(Lightly Doped Drain) structure which comprises the steps of forming a gate insulation film on a semiconductor substrate of a first conduction type, forming a conduction layer for forming a gate pole on the gate insulation film, forming an oxidation prevention layer on the conduction layer, carrying out selective etchings of the oxidation prevention layer and the conduction layer to a certain thicknesses of areas except the gate pole area, forming an oxide film by an oxidation of the exposed portion of the conduction layer, carrying out a selective etching of the oxide film by using the oxidation prevention layer as a mask, forming a high density impurity area of a second conduction type in a predetermined area of the semiconductor substrate by a high density ion injection of the second conduction type impurity, removing the oxidation prevention layer and the oxide film, forming a low density impurity area of the second conduction
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: June 27, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventors: Chang J. Lee, Gong H. Park
  • Patent number: 5422293
    Abstract: A TFT panel is manufactured by a process of forming an oxide voltage-apply lines, gate lines, and capacitor lines on an insulating substrate, and a process of forming thin-film transistors, pixel electrodes, data lines, and ground lines. In a state that one end of the gate line and both ends of the capacitor line are connected to the oxide voltage-apply line, oxide films are formed on the surfaces of the gate line and the capacitor line by anodization. After forming the oxide film, the gate line and the capacitor line are electrically separated from the oxide voltage-apply line.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: June 6, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventor: Naohiro Konya
  • Patent number: 5362670
    Abstract: Element isolation regions are first formed on a silicon substrate. Active regions other than the isolation regions are formed with an oxide film. Then, a first oxidization prevention layer, a semiconductor layer and a second oxidization prevention layer are formed on the substrate in that order. A resist pattern having a hole in a P-channel MOS transistor formation region is formed. The second oxidization prevention layer in the P-channel MOS transistor formation region is removed and an impurity is ion-implanted using the resist pattern as a mask. After removing the resist pattern, the substrate is thermally treated in the presence of an oxidizer substance to transform an exposed portion of the semiconductor layer into an oxidized semiconductor layer and at the same time to diffuse the implanted impurity in the substrate to thereby form an N-well.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: November 8, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuji Iguchi, Shigeki Hayashida, Akio Kawamura, Shinichi Sato, Tomohiko Tateyama
  • Patent number: 5358893
    Abstract: An improved isolation method in a semiconductor device of selective polysilicon oxidation (SEPOX) which can create a field oxide layer having a size below the optical resolution and good isolation characteristics. A buffer layer comprised of polysilicon or amorphous silicon is formed on a semiconductor substrate, and then an anti-oxidative pattern with an opening which defines an isolation region exposing a portion of the buffer layer is formed. Then a portion of the exposed buffer layer is isotropically etched in order to form an undercut portion in the lower portion around the opening. Then an anti-oxidative spacer filling the undercut portion is formed on the sidewall of the opening. Thereafter, a field oxide layer is formed by partially oxidizing the portion of the buffer layer exposed by the opening and the semiconductor substrate exposed in the opening. The size of bird's beak is decreased, thereby forming a field oxide layer with good isolation characteristics and small size.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: October 25, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-suk Yang, Min-uk Hwang, Chang-gyu Hwang
  • Patent number: 5352626
    Abstract: Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation Layer is formed on regions that include the steps or side walls of the grooves.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: October 4, 1994
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5352618
    Abstract: A method for making submicron dielectric windows for electron tunneling between a floating gate and substrate in a semiconductor EEPROM device. A mask edge overlying an oxide layer on a substrate is undercut a small distance, the area surrounding that small distance is built up with oxide, then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: October 4, 1994
    Assignee: Atmel Corporation
    Inventors: Bradley J. Larsen, Donald A. Erickson
  • Patent number: 5342798
    Abstract: Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: August 30, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Tiao-Yuan Huang
  • Patent number: 5336638
    Abstract: Herein disclosed is a process for manufacturing a semiconductor device, which comprises: a step of forming a first electrode composed of tantalum and tungsten over a semiconductor substrate; a step of depositing a dielectric film of tantalum oxide on the first electrode; a step of oxidizing the first electrode and the dielectric film of tantalum oxide; and a step of forming a second electrode over the dielectric film.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: August 9, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Suzuki, Ryo Haruta, Hiroshi Shinriki, Masayuki Nakata
  • Patent number: 5326712
    Abstract: A method for manufacturing a semiconductor device which utilizes anodic oxidation. A first semiconductor layer of a first conductive type is formed on an insulating substrate, a highly doped second semiconductor layer of the first conductive type is formed on the first semiconductor layer, and then an anti-oxidizing pattern is formed on the second semiconductor layer to expose a predetermined portion of the second semiconductor layer. After forming the anti-oxidizing pattern, anodic oxidation is performed to oxidize the exposed portion of the second semiconductor layer. Instead of employing a conventional plasma etching process for removing the portion of the ohmic contact layer which is not in contact with the source and drain electrodes, the portion of the ohmic contact layer to be removed is subjected to anodic oxidation, to thereby form an anodic oxidation layer, thus facilitating removal of the unnecessary portions of the ohmic contact layer without the use of a plasma etching step.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: July 5, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-seong Bae
  • Patent number: 5304510
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a first insulating layer having a hole on a substrate, selectively forming a conductive layer in the hole, selectively forming a second insulating layer on the first insulating layer, patterning the second insulating layer, and forming an interconnection layer in an opening portion of the second insulating layer formed by patterning so as to be electrically connected to the conductive layer.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: April 19, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Haruo Okano
  • Patent number: 5298443
    Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the width of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of an oxide layer and a polysilicon or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: March 29, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Seong J. Jang
  • Patent number: 5266523
    Abstract: Self-aligned contacts are formed between a first layer of material which can be oxidized, such as polycrystalline silicon (poly 1), and a second layer of material such as metal or polycrystalline silicon (poly 2). A patterned layer of material, such as nitride, that prevents the first layer from oxidizing is deposited over the poly 1 layer. The exposed poly 1 material is oxidized, while the poly 1 material covered by the nitride is protected from oxidization. The nitride is removed and another layer of conductive material is formed, and thus contacts the poly 1 layer which was protected from oxidation, while the oxide insulates the other poly 1 areas.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: November 30, 1993
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5254494
    Abstract: A method of manufacturing a semiconductor device includes forming field oxide regions (17) in a surface (1) of a silicon body (2) through oxidation, which body is provided with an oxidation mask (15) formed in a layered structure provided on the surface with a lower layer (4) of silicon oxide, an intermediate layer (5) of polycrystalline silicon and an upper layer (6) of a material including silicon nitride in which windows (8) are etched into the upper layer. The intermediate layer is etched away inside the windows and below an edge (10) of the windows, a cavity (11) is formed below the edge, and a material including silicon nitride is provided in the cavity. The material including silicon nitride is provided in the cavity while the surface of the silicon body situated inside the windows is still covered by a layer of silicon oxide, preferably with the lower layer of the layered structure.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: October 19, 1993
    Assignee: U.S. Philips Corp.
    Inventors: Paulus A. Van Der Plas, Nicole A. H. F. Wils, Andreas H. Montree
  • Patent number: 5254489
    Abstract: According to this invention, there is provided a method of manufacturing a semiconductor device. An element region and an element isolation region are formed on a semiconductor substrate of a first conductivity type. A first oxide film prospectively serving as a gate insulating film is formed in the element region. Thermal oxidization is performed after annealing is performed in nitrogen or ammonia atmosphere to nitrify an entire surface of the first oxide film. A predetermined region of a nitrified first oxide film is removed, and a second oxide film prospectively serving as a gate insulating film is formed in the predetermined region using the nitrified first oxide film as a mask. A gate electrode constituted by a polysilicon film is formed on each of the nitrified first oxide film and the second oxide film.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: October 19, 1993
    Assignee: NEC Corporation
    Inventor: Hidetoshi Nakata
  • Patent number: 5240875
    Abstract: The present invention is directed to a technique for selectively oxidizing trench side walls in a silicon substrate. Each of the side walls can be oxidized individually and to different thicknesses according to the requirements of the trench IC.
    Type: Grant
    Filed: August 12, 1992
    Date of Patent: August 31, 1993
    Assignee: North American Philips Corporation
    Inventor: Len-Yuan Tsou
  • Patent number: 5236862
    Abstract: Defect-free field oxide isolation (34) is formed by oxidizing through a silicon nitride layer (30) which overlies the isolation regions (22) of the silicon substrate (12). Additionally, the silicon nitride layer (30) acts as a diffusion barrier during field growth, and thus inhibits the lateral diffusion of oxygen underneath the oxidation mask (18). Therefore, field oxide encroachment into the adjacent active regions is effectively reduced. Moreover, field oxide encroachment is also reproducibly controlled, and therefore integrated circuits with high device packing densities can be fabricated.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: August 17, 1993
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, Prashant Kenkare
  • Patent number: 5229317
    Abstract: According to this invention, an isolation trench is formed in a semiconductor substrate. A first insulating film is formed on a surface of the semiconductor substrate and an inner surface of the trench. A silicon oxide film containing phosphorus and boron is buried in the trench in which the first insulating film is formed. A second insulating film pattern having a width larger than that of the trench is formed on the trench and a peripheral portion of the trench. The second insulating film pattern prevents out-diffusion phosphorus and boron in the silicon oxide film. The first insulating film which is not covered with the second insulating film pattern is removed to form a first insulating film pattern. The surface of the semiconductor substrate which is not covered with the first and second insulating film patterns is thermally oxidized.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: July 20, 1993
    Assignee: NEC Corporation
    Inventor: Nobuya Nishio
  • Patent number: 5217920
    Abstract: A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: June 8, 1993
    Assignee: Motorola, Inc.
    Inventors: Robert J. Mattox, Paul R. Proctor, Syd R. Wilson
  • Patent number: 5215934
    Abstract: A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: June 1, 1993
    Inventor: Jyh-Cherng J. Tzeng
  • Patent number: 5210549
    Abstract: An ink jet recording head comprises a discharging opening for liquid discharge and an electricity-heat convertor. The electricity-heat convertor has a region formed by oxidation of at least part of an electroconductive material, and the region is adapted to generate heat.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: May 11, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroto Takahashi
  • Patent number: 5196367
    Abstract: A method for fabricating semiconductor devices having field oxide isolation with channel stop is described which overcomes the encroachment problems of the prior art. A semiconductor substrate is provided. A multilayer oxidation masking structure of a silicon oxide layer, a polycrystalline silicon layer and a silicon nitride layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and a portion of the polycrystalline silicon layer in the areas designated to have field oxide isolation grown therein. A sidewall insulator structure is formed on the exposed sidewalls of the patterned oxidation mask. Impurities are implanted into the area designated to have field oxide isolation to form the channel stop. The sidewall insulator structure is removed. The field oxide insulator structure is grown by subjecting the structure to oxidation whereby the channel stop is confined under the field oxide isolation and not encroaching the planned device regions.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: March 23, 1993
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Yuan Lu, Hsiao-Chin Tuan
  • Patent number: 5192707
    Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over the integrated circuit. A nitrogen doped polysilicon layer is formed over the pad oxide layer. A thick nitride layer is then formed over the nitrogen doped polysilicon layer. An opening is formed in the nitride layer and the nitrogen doped polysilicon layer exposing a portion of the pad oxide layer. The nitrogen doped polysilicon layer is annealed encapsulating the polysilicon layer in silicon nitride. A field oxide region is then formed in the opening.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: March 9, 1993
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Robert Hodges, Frank Bryant
  • Patent number: 5175123
    Abstract: A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: December 29, 1992
    Assignee: Motorola, Inc.
    Inventors: Barbara Vasquez, Michael P. Masquelier
  • Patent number: 5132241
    Abstract: An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: July 21, 1992
    Assignee: Industrial Technology Research Institute
    Inventor: Wen-Doe Su
  • Patent number: 5106767
    Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.
    Type: Grant
    Filed: April 10, 1991
    Date of Patent: April 21, 1992
    Assignee: International Business Machines Corporation
    Inventors: Janes H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang
  • Patent number: 5082793
    Abstract: A method of making a dielectric isolation integrated circuit structure in which dielectric material grooves formed by ion implantation extend down into the structure and intersect a PN junction or other active region at intersection lines such that each intersection line is within microns both laterally from the center of the groove and vertically from the bottom of the groove and the grooves continuously curve at least at the intersection lines at a radius of curvature less than 1 cm.
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: January 21, 1992
    Inventor: Chou H. Li
  • Patent number: 5057451
    Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.
    Type: Grant
    Filed: April 12, 1990
    Date of Patent: October 15, 1991
    Assignee: Actel Corporation
    Inventor: John L. McCollum
  • Patent number: 5049520
    Abstract: A method of partially eliminating the field oxide bird's beak over a storage cell and slightly enlarging the storage cell active area without adding any process steps is described. A photomask is used during a buried contact etch to reduce the field oxide bird's beak both vertically and horizonally. The storage cell active area is further enlarged during a first polysilicon etch step without adding process steps. At that point, the wafer is completed by existing techniques.
    Type: Grant
    Filed: June 6, 1990
    Date of Patent: September 17, 1991
    Assignee: Micron Technology, Inc.
    Inventor: David A. Cathey
  • Patent number: 5039625
    Abstract: A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without "bird's beak" formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: August 13, 1991
    Assignee: MCNC
    Inventors: Arnold Reisman, Mark Kellam, Charles K. Williams, Nandini Tandon
  • Patent number: 5019526
    Abstract: A method of manufacturing a semiconductor apparatus having a plurality of elements formed on a substrate comprises forming a pad oxidized film on the surface of the semiconductor substrate, forming a pattern of silicon nitride film to coat device areas on the pad oxidized film, and injecting boron ions into that surface of the pad oxidized film where no silicon nitride film is present, thereby to form a channel stopper region. Using the pattern of the silicon nitride film as a mask, a heat oxidized film is then formed on an elements separating region by heat oxidization, and ions of Si, N, C, or the like are injected into the surface of the heat oxidized film with such an acceleration energy that the ions are not injected into the silicon nitride film thereby to change the quality of the heat oxidized film.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: May 28, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroyuki Yamane, Yasushi Higuchi, Tetsuo Fujii
  • Patent number: 4999155
    Abstract: The present invention is directed to a method for forming porous oxide dispersion strengthened molten carbonate fuel cell anodes having improved anode creep resistance. The method comprises the steps of forming an alloy powder comprised of a base metal and an alloy metal, forming the alloy into a porous anode structure by sintering, and then placing the porous anode structure under conditions in which the base metal is reduced and the alloy metal is oxidized, thereby internally oxidizing the alloy metal to form oxide particles therein.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: March 12, 1991
    Assignee: Electric Power Research Institute, Inc.
    Inventors: Estela T. Ong, Diane S. Erickson, Leonard G. Marianowski
  • Patent number: 4968640
    Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing density VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: November 6, 1990
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4946800
    Abstract: The method for making an improved, surface-passivated and electrically isolated silicon device (including integrated circuit) comprises providing in a silicon wafer with a pn junction or other electronic rectifying barrier; and thermally oxidizing or ion-implanting oxygen or nitrogen into selected silicon surface regions to form electrically isolating grooves. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the pn junction or rectifying barrier. Through these unique oxide/nitride forming conditions and curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.
    Type: Grant
    Filed: August 6, 1973
    Date of Patent: August 7, 1990
    Inventor: Chou H. Li
  • Patent number: 4923827
    Abstract: On a semiconductor substrate (38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated with the remaining portions of the contact structure being masked by selective oxidation.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: May 8, 1990
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, David Ward
  • Patent number: 4906595
    Abstract: A method of manufacturing a semiconductor device, in which a surface (1) of a silicon wafer (2) is locally provided with an oxidation mask (3), whereupon the wafer is subjected to an oxidation treatment by heating it in an oxidizing gas mixture. According to the invention, the wafer is heated during the treatment in the oxidizing gas mixture to a temperature of 950.degree. to 1050.degree. C. Water is then added to the oxidizing gas mixture. The quantity of added water is initially less than 30% by volume and later larger. Thus, in a comparatively short time a comparatively thick layer of oxide can be formed without defects being formed in silicon lying under the oxide.
    Type: Grant
    Filed: July 21, 1989
    Date of Patent: March 6, 1990
    Assignee: U.S. Philips Corporation
    Inventors: Paulus A. van der Plas, Wilhelmina C. E. Snels
  • Patent number: 4897365
    Abstract: A method for reducing birdbeaks formed during a planox process is disclosed. On a silicon substrate (1), oxide (2) and nitride (3) are formed. The oxide and nitride are then selectively etched using a single plasma having high selectivity with respect to silicon and a photoresist mask (4). The high selectivity toward silicon is achieved by use of a CHF.sub.3 +CO.sub.2 plasma under conditions of 30:1 oxide/silicon selectivity. Field oxide regions (5) with reduced birdbeaks can then be formed.
    Type: Grant
    Filed: November 23, 1987
    Date of Patent: January 30, 1990
    Assignee: SGS Microelecttronica S.P.A.
    Inventors: Livio Baldi, Daniela Beardo, Marco Icardi, Adriana Rebora
  • Patent number: 4845048
    Abstract: A method of fabricating a semiconductor device which includes:(1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks,(2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method,(3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and(4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks.Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.
    Type: Grant
    Filed: November 7, 1988
    Date of Patent: July 4, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tokuhiko Tamaki, Masafumi Kubota
  • Patent number: 4840920
    Abstract: In a method of manufacturing a semiconductor device according to the present invention, regions of first conductivity type buried layers formed on a first conductivity type substrate are retracted with respect to regions of second conductivity type buried layers. Thus, in formation of second conductivity type epitaxial layer, first conductivity type impurity contained in the first conductivity type buried layers is prevented from floating diffusion up to element regions of the second conductivity type epitaxial layers. At the same time, the semiconductor device can be implemented with high density of integration.
    Type: Grant
    Filed: September 25, 1987
    Date of Patent: June 20, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kakutaro Suda