Abstract: A method for manufacturing a fully self-adjustsed bipolar transistor in which the emitter zone, the base zone, and the collector zone are aligned vertically in a silicon substrate; the collector is connected by means of a deeply extending terminal in the substrate, the inactive base zone is embedded in an insulating trench to separate the inactive base zone from the collector; the emitter terminal zone is composed of doped polycrystalline silicon and is separated from the inactive base zone by a silicon oxide layer. A fully self-adjusted bipolar transistor is produced wherein the emitter is self-adjusted relative to the base and the base is self-adjusted relative to the insulation. The number of method steps involving critical mask usage is low, and parasitic regions are minimized so that the switching speed of the component is increased. The transistor is used for integrated bipolar transistor circuits having high switching speeds.

Abstract: A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.

Abstract: Submicron resolution in the fabrication of transistors is obtained by using sidewall techniques. The techniques described remove the sidewalls after oxidizing the materials between the sidewalls and the openings so formed by the removal are used as a mask for subsequent substrate modification by either diffusion or ion implantation.

Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing desnity VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.

Abstract: A method for the manufacture of neighboring wells 9, implanted with dopant ions of differing conductivity type in silicon substrates provided with an epitaxial layer. A lateral under-etching having high selectivity to specified layers is designationally introduced into a silicon nitride layer provided for masking the n-well regions in the implantation of the p-wells. Thus, the edge of a silicon oxide layer serving as a masking in the following oxidation shifts in the direction of the n-wells. As a result of this type of self-adjusted well production, the influence of the counter-doping in the region of the well boundaries is noticeably reduced. In addition, a polysilicon layer can also be employed under the silicon nitride layer as a masking layer, this layer eing co-oxidized after the under-etching of the silicon nitride layer. Thus a box-shaped course is produced in the masking oxide instead of the prior art bird's bill course, whereby a steeper diffusion front is achieved in the n-well.

Abstract: An improved method is described for constructing one or more integrated circuit components including bipolar and MOS devices on a silicon substrate without damaging areas of the substrate wherein active elements of the integrated circuit components will be formed. The method comprises forming multilayer pedestals of masking materials over the active regions of the substrate and subsequently removing these masking materials using wet etching to avoid damage to the substrate by dry etching.

Abstract: In a method according to the present invention for forming isolation oxide films (14) on a silicon substrate (11) having trenches and islands bounded by the trenches, the isolation oxide films are simultaneously formed in the island regions and in the side wall regions of the trenches by oxidizing the substrate (11) with a single patterned oxidation mask (12).

Abstract: A method of manufacturing a semiconductor substrate, and, in particular, a technique of electrically isolating a semiconductor element formed on a semiconductor substrate. The method comprises the steps of depositing a silicon oxide layer on the surface of a silicon substrate, for its protection; forming a silicon nitride layer on the silicon oxide layer; selectively eliminating the silicon nitride layer; oxidizing the silicon substrate, with the retained silicon nitride layer being used as a mask, thereby providing an oxide layer; depositing a polycrystalline silicon layer on the oxide layer and the retained acid-resisting layer; oxidizing the polycrystalline silicon layer to provide an insulation layer; eliminating the insulation layer until the silicon nitride layer is exposed; and removing all the silicon nitride layer.

Abstract: A plurality of first cavities is formed in the planar surface of a silicon substrate. A first oxide region of predetermined thickness is formed in each of the first cavities such that each of the first oxide regions has a surface which is coplanar with the substrate surface. A layer of monocrystalline silicon is then epitaxially deposited over the planar first oxide region/substrate surface. Second cavities are then formed through the monocrystalline silicon layer and into the substrate adjacent the first oxide regions, extending to a depth equal to approximately one-half that of the first oxide regions. The second cavities are then thermally oxidized so as to form second oxide regions therein, these second oxide regions being coplanar with the first oxide regions. Silicon is next epitaxially deposited on those portions of the monocrystalline silicon layer remaining on the first oxide regions so as to yield a continuous monocrystalline silicon sheet over the first and second oxide regions.

Abstract: A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Abstract: A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer.

Abstract: Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Abstract: The present invention accomplishes the thermal oxidation of the silicon side of the interface present in epitaxial silicon films grown on yttria-stabilized cubic zirconia, <Si>/<YSZ>, to form a dual-layer structure of <Si>/amorphous SiO.sub.2 /<YSZ>. The SiO.sub.2 films are formed in either dry oxygen (at 1100.degree. C.) or in pyrogenic steam (at 925.degree. C.) by the rapid diffusion of oxidizing species through a 425 .mu.m thick cubic zirconia substrate. For instance, a 0.17 .mu.m thick SiO.sub.2 layer is obtained after 100 min in pyrogenic steam at 925.degree. C. This relatively easy transport of oxidants is unique to YSZ and other insulators which are also superionic oxygen conductors, and cannot be achieved in other existing Si/insulator systems, such as silicon-on-sapphire.

Abstract: The invention comprises an improved integrated circuit structure wherein an active device is formed in a silicon substrate for forming an intrinsic base region over a buried collector and an emitter is formed on the intrinsic base region to comprise three electrodes of the active device and at least one extrinsic base segment is formed in the substrate adjacent to the intrinsic base region to provide a contact for the intrinsic base; the improvement which comprises: separating the extrinsic base segment from the emitter formed on the intrinsic base to prevent the formation of a parasitic P-N junction between the extrinsic base and the emitter.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: A method of forming electric conductive patterns comprising the steps of forming first conductive patterns on a semiconductor substrate directly or through an insulating layer with first insulating film being formed thereon, selectively forming second conductive patterns, forming insulation layers on side surfaces of said second conductive patterns, thereby electrically insulating said second conductive patterns from said first conductive patterns through said insulation layers in a self-aligned manner. An semiconductor device having electric conductive patterns formed by above-mentioned method.

Abstract: The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.

Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.

Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.

Abstract: A process for growing field oxide regions in an MOS circuit. An initial thermally grown layer of silicon nitride seals the substrate surface and reduces lateral oxidation, or bird's beak formation along the substrate-nitride interface. Field oxidation takes place in two steps, with the first step being a dry oxidation in HCL and the second taking place in steam.

Abstract: A method of manufacturing a semiconductor substrate having dielectric regions is disclosed. The method comprises steps of forming an amorphous silicon layer on the surface of a monocrystalline silicon substrate, annealing a selected surface of said amorphous silicon layer to form a crystallized region intended as an active region, subjecting the obtained structure to a thermal oxidation process to form said dielectric isolation regions, and removing an oxide coating formed on the surface of said crystallized region.

Abstract: In a semiconductor device comprising at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, an impurity-introduced region having the same conductivity type as that of the semiconductor substrate is formed so as to surround the V-groove. A buried layer of the bipolar transistor comes into contact with the VIP isolating layer to divide the impurity-introduced region into two parts, one of which is combined with a base region and the other one of which serves as a channel stopper.

Abstract: A method of making semiconductor integrated circuit devices with narrow and deep isolation regions of polycrystalline silicon and wide and thick isolation regions of thermally grown silicon oxide. A multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, a second silicon nitride layer and a silicon oxide layer are formed on a semiconductor body. A photoresist layer is applied on the surface of the silicon oxide layer. An opening is formed in the photoresist layer and the multi-layer. The silicon oxide layer under the photoresist layer is side-etched through the opening. The exposed polycrystalline layer is converted into another silicon oxide layer. Another opening surrounding the silicon oxide layer is formed to expose surfaces of the semiconductor body. Deep grooves are formed in the semiconductor body.

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a semiconductor substrate comprising forming over the semiconductor substrate surface an electrically insulating layer of dielectric material having a plurality of openings therethrough and etching to form recesses in the semiconductor substrate exposed in the openings. Then, aluminum is deposited over the substrate so that an aluminum layer is formed on said layer of dielectric material as well as in said recesses. Next, the aluminum in the recesses is selectively anodized to form aluminum oxide, and the remaining aluminum on said layer of dielectric material is removed either by selectively etching away the aluminum layer or by a "lift-off" technique wherein the insulating layer of dielectric material under the aluminum is etched away thereby "lifting-off" and removing the aluminum.

Abstract: The invention provides a process comprising a step for depositing at least one intrinsic or doped monocrystalline silicon layer on a substrate, also monocrystalline, followed by a step for forming a thin silica layer at the level of the original substrate-silicon interface. The silica layer is obtained by oxidation through the substrate, followed by a heat treatment step during which the monocrystalline silicon is oxidized by the implanted oxygen ions. The first approach may take place according to two variants: thermal or plasma oxidation of the silicon-substrate interface. Oxidation takes place during the return to ambient temperature of the stack of layers after the deposit has been made.

Abstract: A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.

Abstract: One or more monolayers of cerium arrayed on the surface of a niobium metal acts as a catalyst to oxidation of the niobium at ambient temperature and results in a very thin, very high quality insulating layer which may be configured by patterning of the catalyst. Significant amounts of Nb.sub.2 O.sub.5 are formed at pressures as low as 6.6.times.10.sup.-6 Pa, promoted by the presence of the cerium. This catalytic activity is related to the trivalent to tetravalent valence change of the cerium during oxidation. The kinetics of Nb.sub.2 O.sub.5 formation beneath the oxidized cerium shows two stages:the first stage is fast growth limited by ion diffusion;the second stage is slow growth limited by electron tunneling.Other catalytic rare earths usable instead of cerium are terbium and praseodymium; other substrate materials usable instead of niobium are aluminum, hafnium, silicon and tantalum, or oxidizable alloys thereof.