Oxide Films Patents (Class 148/DIG118)
  • Patent number: 6165287
    Abstract: A ferromagnetic tunnel-junction magnetic sensor includes a first ferromagnetic layer, an insulation barrier layer formed on the first ferromagnetic layer and including therein a tunnel oxide film, and a second ferromagnetic layer formed on the insulation barrier layer, wherein the insulation barrier layer includes a metal layer carrying the tunnel oxide film thereon such that the tunnel oxide film is formed of an oxide of a metal element constituting the metal layer, and wherein the insulation barrier layer has a thickness of about 1.7 nm or less but larger than 1 molecular layer in terms of the oxide forming the tunnel oxide film.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: December 26, 2000
    Assignee: Fujitsu Limited
    Inventors: Masashige Sato, Kazuo Kobayashi, Hideyuki Kikuchi
  • Patent number: 5696023
    Abstract: A method of forming a native oxide from an aluminum-bearing Group III-V semiconductor material is provided. The method entails exposing the aluminum-bearing Group III-V semiconductor material to a water-containing environment and a temperature of at least about 375 C to convert at least a portion of said aluminum-bearing material to a native oxide characterized in that the thickness of said native oxide is substantially the same as or less than the thickness of that portion of said aluminum-bearing Group III-V semiconductor material thus converted. The native oxide thus formed has particular utility in electrical and optoelectrical devices, such as lasers.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: The Board Of Trustees Of The University Of Illinois
    Inventors: Nick Holonyak, Jr., John M. Dallesasse
  • Patent number: 5674788
    Abstract: A silicon oxynitride (oxynitride) dielectric layer is presented using a process in which nitrogen is incorporated into the dielectric as it is grown upon a silicon substrate. The oxynitride layer is grown at elevated temperature and pressure in an ambient containing N.sub.2 O and/or NO. A MOS gate dielectric is advantageously formed from the oxynitride dielectric layer with a sufficient nitrogen concentration near the interface between a boron-doped polysilicon gate electrode and the gate dielectric as to prevent boron atoms from penetrating into the gate dielectric. Further, the oxynitride layer contains a sufficient nitrogen concentration near the interface between the gate dielectric and a silicon substrate as to reduce the number of high-energy electrons injected into the gate dielectric which become trapped in the gate dielectric.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 7, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dirk J. Wristers, H. Jim Fulford, Dim Lee Kwong
  • Patent number: 5645943
    Abstract: An electrified object contact material characterized in that an oxide film formed in a high purity oxidizing atmosphere with a thickness from several tens to 100 .ANG. is formed at least in a section directly contacting an electrified object. By using the contact component according to the present invention, the electric potential of a wafer can always be suppressed to 50 V or less, and moreover, contamination of a wafer (especially by a metallic material) can completely be eliminated.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: July 8, 1997
    Assignee: Takasago Netsugaku Kogyo Kabushiki Kaisha
    Inventors: Tadahiro Ohmi, Hitoshi Inaba
  • Patent number: 5646074
    Abstract: Disclosed is a process for manufacturing a gate oxide of a MOSFET. Since the performance of the gate oxide is deteriorated in photo resist removing, DI healing and high temperature annealing are introduced to recover the gate oxide. A process for manufacturing the gate oxide of the MOSFET on a wafer, includes the steps of: pre-cleaning the wafer, forming gate oxide layer, coating a photo resist, exposing the photo resist, developing the photo resist, implanting ions over the developed photo resist, removing the photo resist, post-cleaning the gate oxide for the purpose of good attachment of a gate polysilicon layer, DI healing the gate oxide, and annealing the gate oxide at a high temperature. As a result, the pass rates for Ebd and Qbd tests of the gate oxide increase.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 8, 1997
    Assignee: Mosel Vitelic, Inc.
    Inventors: Rickey Chen, Rex Chen
  • Patent number: 5643817
    Abstract: A liquid crystal display having a gate insulating film of whose dielectric constant is a high and exhibits excellent leakage characteristics, includes a plurality of gate wirings formed on the transparent substrate, a plurality of signal lines arrayed to intersect the plurality of gate wirings, a plurality of switching devices located at the point of intersection between the respective gate wirings and signal lines. The switching device comprises a gate electrode constituted by aluminum or an aluminum alloy and a gate insulating film inserted between the channels of switching devices and the gate electrode. The gate insulating film has a first anodic oxide film constituted by aluminum or an aluminum alloy and a second anodic oxide film constituted by tantalum or a tantalum alloy. In the manufacturing method thereof, metals, aluminum or tantalum, are simultaneously anodically oxidized so as to suppress a hillock.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: July 1, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-seob Kim, Chi-woo Kim, Young-chan Kweon, Won-kie Chang
  • Patent number: 5597768
    Abstract: A method of forming a dielectric layer on a supporting structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer including the step of depositing a layer of Ga.sub.2 O.sub.3, having a sublimation temperature, on the surface of the supporting structure by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide with a melting point greater than 700.degree. C. above the sublimation temperature of the Ga.sub.2 O.sub.3. The evaporation can be performed by any one of thermal evaporation, electron beam evaporation, and laser ablation.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: January 28, 1997
    Assignee: Motorola, Inc.
    Inventors: Matthias Passlack, Jonathan K. Abrokwah
  • Patent number: 5593921
    Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: January 14, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Fusen E. Chen, Fu-Tai Liou, Girish A. Dixit
  • Patent number: 5523240
    Abstract: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: June 4, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Shunpei Yamazaki
  • Patent number: 5521126
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a wiring layer on the surface of a semiconductor substrate, depositing a silicone film on the whole surface of the semiconductor substrate including the wiring layer by a CVD method and exposing the silicone film to oxidative plasma with enhanced frequencies including components of 1 MHz or less to change to a silicon oxide film, the depositing step and exposing step being alternately repeated in the same apparatus till the silicon oxide film having any desired thickness is obtained. The resulting silicon oxide film has the smooth surface and the high density.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: May 28, 1996
    Assignee: NEC Corporation
    Inventors: Kenji Okamura, Masanobu Zenke, Yasuhide Den
  • Patent number: 5488015
    Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: January 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Shin-Puu Jeng, Bruce E. Gnade, Chih-Chen Cho
  • Patent number: 5459108
    Abstract: There is provided a semiconductor device manufacturing process which enables film deposition at low temperatures and can produce an interlayer insulating film of good quality which exhibits good surface smoothing effect. In the TEOS-O.sub.3 system normal pressure CVD process, film growth is carried out by adding to TEOS source a source containing nitrogen in its composition. For the source is used heptamethyl disilazane (chemical formula (CH.sub.3).sub.3 SiN(CH.sub.3)Si(CH.sub.3).sub.3), N, O-bis-trimethylsilyl acetamide (chemical formula (CH.sub.3)C(OSi(CH.sub.3).sub.3)(NSi(CH.sub.3).sub.3)) or tridimethylamino silane (chemical formula (CH.sub.3).sub.2 N).sub.3 SiN). Also, there is provided a semiconductor device manufacturing method which enables film deposition at a uniform growth rate irrespective of the substrate material and can produce a silicon oxide film of good quality which exhibits good surface smoothing effect. An organic source having an Si--N bond in its composition and O.sub.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsukasa Doi, Yukiko Mori
  • Patent number: 5422306
    Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: June 6, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
  • Patent number: 5413967
    Abstract: An organic silane compound gas and an oxidizing gas are introduced into a reaction vessel from each gas source. Further a gas containing at least one kind of halogen, for example carbon tetrafluoride, is decomposed into halogen radicals, etc., by microwave discharge, and introduced into the reaction vessel. Reaction occurs between the gases, resulting in silicon oxide films being formed on substrates in the reaction vessel.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: May 9, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Haruo Okano
  • Patent number: 5397719
    Abstract: The present invention relates to an improved method of manufacturing pads of a display panel. Al or Al alloy is deposited and patterned on a glass substrate for forming a plurality of gate electrodes and lines. Then a plurality of pads are formed with Ta or Ti, which is capable of forming an anodic oxide thereof; each pad extending over an edge of each of the respective gate lines to provide an electrical coupling therebetween. Thereafter, the entire surface of the pads, gate electrodes and lines is subjected to an anodic oxidation under a high anodization voltage. Anodic oxide layers on the pads are then etched away together with a silicon nitride layer during a subsequent pad opening processing step. Consequently, in accordance with the invention, a photoresist masking process for the selective anodic oxidation of Al gate lines and electrodes is eliminated.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: March 14, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Soo Kim, In-Sik Jang, Dong-Kyu Kim, Yong-Kuk Bae
  • Patent number: 5393352
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: February 28, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5382550
    Abstract: A deposition method of reducing fixed charge in a layer of silicon dioxide includes: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; b) providing an oxidizing gas to the reactor for reaction with the organosilicon compound; c) feeding a gaseous hydrogen containing source to the reactor; and d) reacting the organosilicon compound, oxidizing gas and gaseous hydrogen containing source to deposit a layer of silicon dioxide on the wafer, the hydrogen containing source gas effectively reacting with the organosilicon compound to produce reduced fixed charge in the deposited silicon dioxide layer over that which would be present if no hydrogen containing source gas were fed to the reactor under otherwise identical reacting conditions.
    Type: Grant
    Filed: August 5, 1993
    Date of Patent: January 17, 1995
    Assignee: Micron Semiconductor, Inc.
    Inventor: Ravi Iyer
  • Patent number: 5376591
    Abstract: A, method for forming semiconductor device, includes forming an insulating film on a body by chemical vapor deposition, at low temperature raising the temperature of, the body, and exposing the body to plasma gas.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: December 27, 1994
    Assignee: Semiconductor Process Laboratory Co., Ltd.
    Inventors: Kazuo Maeda, Noboru Tokumasu, Yuko Nishimoto
  • Patent number: 5334552
    Abstract: A method of fabricating a multi-layered interconnection structure which comprises the steps of: forming a first wiring layer on a silicon oxide film having a compressive stress; forming a thick (2 to 3.5 .mu.m) fluorine-containing silicon oxide film at a temperature not higher than 200 .degree. C.; etching back the fluorine-containing silicon oxide film to flatten the surface of the film; forming a silicon oxide film having a compressive stress; forming a through-hole in position; and forming a second wiring layer. Since the fluorine-containing silicon oxide film is used as part of an insulating film, a resistance to cracking, flatness and reliability are significantly improved.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: August 2, 1994
    Assignee: NEC Corporation
    Inventor: Tetsuya Homma
  • Patent number: 5334544
    Abstract: A method of making thin film transistors such that the first conductive layer of a thin film transistor is formed with an aluminum system metal having a low electric resistance, and another metal capable of anodic oxidation is deposited to prevent the aluminum system metal from producing hillocks. The metal capable of anodic oxidation and part of the aluminum system metal are changed into an insulator by an anodic oxidation treatment. In all, the gate insulator of the thin film transistor comprises three layers of aluminum oxide, an oxide of the metal capable of anodic oxidation, and silicon nitride. The method makes it possible to form the lower-layer wiring and gate electrode having a low electric resistance and a flawless gate insulator having excellent insulative quality.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: August 2, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomizo Matsuoka, Mamoru Takeda, Ikunori Kobayashi
  • Patent number: 5330920
    Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: July 19, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Hamid R. Soleimani, Brian S. Doyle, Ara Philipossian
  • Patent number: 5330935
    Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG..
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: July 19, 1994
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, David L. Harmon, Srinandan R Kasi, Donald M. Kenney, Son Van Nguyen, Tue Nguyen, Pai-Hung Pan
  • Patent number: 5328867
    Abstract: A method of removing impurities from the surface of an integrated circuit and forming a uniform thin native oxide layer on the same surface of an integrated circuit is described. A hydrofluoric acid solution, followed by a rinse and spin dry, is often used to remove gate oxide from within an opening etched in a polysilicon layer. The rinsing leaves water spots. Spin drying leaves impurities where water tracks were. An H.sub.2 O.sub.2 cleaning is performed to remove the water spots. After the cleaning, a uniform thin layer of native oxide is formed on the surface of the silicon substrate. A second layer of polysilicon is deposited over this first thin native oxide layer and doped with an implant dosage chosen so that it will go through the uniform native oxide layer. The substrate is annealed to drive in the buried contact. Processing continues to form polysilicon or silicide gate electrodes. Source and drain regions are formed within the openings to the silicon substrate between the gate electrodes.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: July 12, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Sun-Chieh Chien, Yu-Ju Liu
  • Patent number: 5314846
    Abstract: An apparatus and method for growing semiconductor quality oxide thermal layers on semiconductor wafers fast enough to be economically feasible as a single wafer process system. Process speed is insured by high pressure and high temperature. For example, if the pressure is about 100 atmospheres (1,500 psi) and at a temperature of 900.degree. C., approximately 2.66 minutes are required to grow a 5,000.ANG. oxide layer in a steam environment. The system can reach these operating conditions from ambient in approximately 30 seconds and depressurization and cool down require approximately 60 to 90 seconds. The apparatus includes a processing chamber to be pressurized with an oxidant, such as high pressure steam. The process chamber is contained in a pressure vessel adapted to be pressurized with an inert gas, such as nitrogen, to a high pressure. A pressure equalizing scheme is used to keep the fluid pressure of the process chamber and the pressure of the fluid pressure vessel substantially the same.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: May 24, 1994
    Assignee: Atomel Products Corporation
    Inventor: Charles Boitnott
  • Patent number: 5306672
    Abstract: A method for forming a gate oxide film of a high reliability and a superior performance applicable to a very-large-scale integrated circuit and a manufacturing equipment for the same are disclosed. The method includes steps for treating a substrate with a HF solution, then treating with a HF gas, and subsequently treating with H.sub.2 gas of a high purity, and oxidizing the substrate. The step of the H.sub.2 gas treatment is carried out at a temperature equal to or above 200.degree. C. and at a pressure equal to or below 10 Torr. The manufacturing equipment comprises loading-lock chambers between a HF gas treatment chamber and a H.sub.2 gas treatment chamber and between the H.sub.2 gas treatment chamber and a thermal oxidation chamber for avoiding exposure of the substrate to the air during transferring the substrate between the chambers.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: April 26, 1994
    Assignee: NEC Corporation
    Inventor: Youichirou Numasawa
  • Patent number: 5290736
    Abstract: A silicon oxide film to be used as an interlayer-insulating film in a semiconductor device is formed by a high pressure organic silane-O.sub.3 CVD. A semiconductor wafer is placed in a reaction vessel and is heated at a temperature of 350.degree. C. A mixture of an organic silane gas such as TEOS, HMDS and OMCTS and an ozone gas is introduced into the reaction vessel and the reaction is carried out at a pressure higher than the atmospheric pressure, preferably at a pressure of about 2 atm to form a silicon oxide film having excellent properties. A life time of the ozone gas which serves as an oxiding agent and/or catalyst can be prolonged under the high pressure, and therefore a deposition rate of the silicon oxide film ca be increased and the flatness of the silicon oxide film can be improved. Therefore, the silicon oxide film forming process can be performed efficiently and a flatening process after the formation of the silicon oxide film can be made simpler.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: March 1, 1994
    Assignee: Kawasaki Steel Corporation
    Inventors: Nobuyoshi Sato, Kyoji Tokunaga, Tomoharu Katagiri, Tsuyoshi Hashimoto, Tomohiro Ohta
  • Patent number: 5282903
    Abstract: A method for providing an oxide film of a material on the surface of a substrate using a reactive deposition of the material onto the substrate surface in the presence of a solid or liquid layer of an oxidizing gas. The oxidizing gas is provided on the substrate surface in an amount sufficient to dissipate the latent heat of condensation occurring during deposition as well as creating a favorable oxidizing environment for the material.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: February 1, 1994
    Assignee: Associated Universities, Inc.
    Inventors: Mark W. Ruckman, Myron Strongin, Yong L. Gao
  • Patent number: 5281557
    Abstract: In the manufacture of integrated circuits, a process for forming a dielectric layer such as silicon dioxide which has a high wet etch rate is disclosed. Illustratively, the process is performed with a precursor gas in a plasma reactor with a shower head and a susceptor which supports a wafer. The power density, pressure, susceptor-shower head spacing, and (optionally) temperature are respectively decreased, decreased, increased and decreased to reduce the effectiveness of dissociation of the precursor gas. The resulting film contains impurities which enhance its wet etch rate.
    Type: Grant
    Filed: April 22, 1993
    Date of Patent: January 25, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Chen-Hua D. Yu
  • Patent number: 5264394
    Abstract: A method for providing an oxide film of a material on the surface of a substrate using a reactive deposition of the material onto the substrate surface in the presence of a solid or liquid layer of an oxidizing gas. The oxidizing gas is provided on the substrate surface in an amount sufficient to dissipate the latent heat of condensation occurring during deposition as well as creating a favorable oxidizing environment for the material.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: November 23, 1993
    Assignee: Associated Universities, Inc.
    Inventors: Mark W. Ruckman, Myron Strongin, Yong L. Gao
  • Patent number: 5262358
    Abstract: A silicate layer, which is especially used as an intermediate oxide insulation layer in an integrated circuit for levelling topographic irregularities, is produced by the following method steps: photo-induced polymerization of polysiloxane by means of vapor-phase reaction taking as a basis an SiO-containing or an SiC-containing organic compound together with an O.sub.2 -containing and/or an N.sub.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: November 16, 1993
    Assignee: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Hermann Sigmund, Armin Klumpp
  • Patent number: 5246887
    Abstract: A method for forming a thin high quality interlevel dielectric is disclosed. The dielectric is produced in a plasma reactor utilizing a precursor gas such as TEOS. Pressure, power, temperature, gas flow, and showerhead spacing are controlled so that a dielectric of TEOS may be deposited at 60-5 .ANG. / sec, thus making formation of thin (800 .ANG.) high quality dielectrics feasible.
    Type: Grant
    Filed: July 10, 1991
    Date of Patent: September 21, 1993
    Assignee: AT&T Bell Laboratories
    Inventor: Chen-Hua D. Yu
  • Patent number: 5244843
    Abstract: A novel process for forming a robust, sub-100 .ANG. oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 .ANG.. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 .ANG.. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 .ANG., a composite oxide stack is used which comprises 40-90 .ANG. of pad oxide formed using the above novel process, and 60-200 .ANG. of deposited oxide.
    Type: Grant
    Filed: December 17, 1991
    Date of Patent: September 14, 1993
    Assignee: Intel Corporation
    Inventors: Robert S. K. Chau, William L. Hargrove, Leopoldo D. Yau
  • Patent number: 5238849
    Abstract: A bipolar transistor having a silicon oxide film having a stoichiometric composition ratio of silicon to oxygen controlled to 1 to 2 formed at the boundary between a monocrystalline layer and a polycrystalline layer. In fabrication, a natural oxidized film formed on the surface of an intrinsic base region of a single-crystal is removed in an ultrahigh-vacuum chamber. Subsequently, oxygen ions are supplied to the surface of the base region at room temperature to form a silicon oxide film. Further, silicon molecular beams are supplied in the same chamber to form the polycrystalline silicon layer. The current gain factor h.sub.FE of the bipolar transistor thus formed can be greatly improved.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: August 24, 1993
    Assignee: NEC Corporation
    Inventor: Fumihiko Sato
  • Patent number: 5219774
    Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: June 15, 1993
    Assignee: Xicor, Inc.
    Inventor: Gregory S. Vasche
  • Patent number: 5219797
    Abstract: A gallium arsenide surface is treated and made ready for passivation by esing the gallium arsenide surface to silicon monoxide (SiO) vapor under a vacuum at about 450.degree. C. for a short time.
    Type: Grant
    Filed: August 31, 1992
    Date of Patent: June 15, 1993
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Gary J. Gerardi, Edward H. Poindexter, Fang Rong
  • Patent number: 5214003
    Abstract: An inventive process for producing a semiconductor device has the steps of: putting a compound semiconductor substrate, an element of the substrate elements having a higher vapor pressure in a quartz ampoule, evacuating the ampoule, introducing oxygen gas into the ampoule and then sealing the ampoule; heating the ampoule to produce an oxide layer on the surface of the compound semiconductor substrate; and forming an electrode metal layer on the oxide layer to produce a MOS diode with a low interface trap density or a Schottky diode with a high barrier height and small ideal factor. Thus, the process produces a Schottky diode of a good forward current/voltage characteristic, low reverse current and superior rectification performance and a MESFET of a low dispersion at threshold voltage.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: May 25, 1993
    Assignee: Nippon Mining Co., Ltd.
    Inventors: Haruhito Shimakura, Osamu Oda, Keiji Kainosho
  • Patent number: 5212119
    Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: May 18, 1993
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyung C. Hah, Jung T. Kim, Yong K. Baek, Hee K. Cheon
  • Patent number: 5212118
    Abstract: An apparatus and method for chemical vapor deposition in which the reactants directed toward a substrate to be provided with one or more films are first subjected to an electric field. The electric field is applied between two electrodes and the reactants become polarized in the field, thus stretching their polarized chemical bonds close to the breaking point. The apparatus also applies voltage pulses between one of the electrodes and the substrate. By adjusting the pulse height, pulse width and pulse repetition rates, the chemical bonds of polarized reactants break to produce free radicals and some ions of the desired elements or compounds. The substrate is kept at a given temperature. The free radicals react to deposit the desired film of high purity on the substrate. The deposition characteristics of the deposited films in terms of isotropic, anisotropic and selective deposition are controlled by the pulse height, width, repetition rates and by other process parameters.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: May 18, 1993
    Inventor: Arjun N. Saxena
  • Patent number: 5208189
    Abstract: Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: May 4, 1993
    Assignee: Motorola, Inc.
    Inventors: Bich-Yen Nguyen, Philip J. Tobin
  • Patent number: 5194405
    Abstract: A method of manufacturing semiconductor devices wherein a silicon compound is formed on a silicon substrate, the silicon compound having a thickness less than 50.ANG.. Next, a metal film is formed on the silicon compound film, then, a two step annealing process which includes a low temperature annealing followed by a high temperature annealing is performed. A metal silicide film may be formed with high selectivity on the silicon substrate by forming a silicide layer on the silicon compound.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: March 16, 1993
    Assignee: Sony Corporation
    Inventors: Hirofumi Sumi, Toshiyuki Nishihara
  • Patent number: 5183775
    Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.
    Type: Grant
    Filed: January 23, 1990
    Date of Patent: February 2, 1993
    Assignee: Applied Materials, Inc.
    Inventor: Karl B. Levy
  • Patent number: 5182235
    Abstract: To cover a conductive interconnection (2) of a semiconductor device (1) at high speed with an insulating film (3) having good step coverage, a conductive dummy pattern (8) is provided around the interconnection (2) in spaced relationship therewith. The dummy pattern (8) and interconnection (2) are then covered with insulating film 3 using the bias sputtering method. The dummy pattern (8) and interconnection (2) are preferably applied simultaneously to the substrate using a single mask.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: January 26, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kouzi Eguchi
  • Patent number: 5182221
    Abstract: A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: January 26, 1993
    Assignee: Sony Corporation
    Inventor: Junichi Sato
  • Patent number: 5180692
    Abstract: This invention relates to a method for forming a boron-containing film of high quality on the surfaces of semiconductor wafers by CVD or epitaxial techniques using reaction gases including at least boron trifluoride.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: January 19, 1993
    Assignee: Tokyo Electron Limited
    Inventors: Shigehito Ibuka, Hideki Lee
  • Patent number: 5166101
    Abstract: A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dpoants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.
    Type: Grant
    Filed: February 1, 1991
    Date of Patent: November 24, 1992
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, David N. K. Wang, Makoto Nagashima, Kazuto Fukuma, Tetsuya Sato
  • Patent number: 5132244
    Abstract: A method is disclosed for growing relatively thin (e.g., <250 .ANG.) thermal oxides which results in lowering the defect density, mobile ion concentration, interface trapped charge density, and stress of the structure. In particular, the prior art oxidation process is modified to include in situ preoxidation silicon surface treatments to improve the silicon nucleation surface. For example, gettering operations may be performed to remove metal-ion contaminants from the silicon nucleation surface, and high temperature annealing operations may be performed to remove any local stress gradients which exist in the silicon substrate during the initial stages of oxidation. By improving the silicon nucleation surface, the subsequently grown thin oxide will be improved in terms of the qualities mentioned above.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: July 21, 1992
    Assignee: AT&T Bell Laboratories
    Inventor: Pradip K. Roy
  • Patent number: 5098865
    Abstract: A process for preparing high step coverage silicon dioxide coatings on semiconductor wafers comprising the placing of the wafer to be coated in a process chamber, introducing disilane and nitrous oxide into the process chamber and maintaining the wafer in an atmosphere consisting essentially of a gaseous mixture of disilane and nitrous oxide and initiating and maintaining plasma enhanced chemical vacuum deposition of silicon dioxide from said gaseous mixture by applying radio frequency energy to the wafer to create a plasma adjacent the surface of said wafer is disclosed.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: March 24, 1992
    Inventors: Jose R. Machado, Terry A. Francis, Hans P. W. Hey
  • Patent number: 5057463
    Abstract: A method for forming a thin oxide layer structure includes the step of first growing a dry oxide layer. A layer grown in steam and chlorine is formed next, followed by a final dry oxide layer. An anneal step in an inert gas further improves the quality of the oxide layer. The structure formed by such a process provides a layer of steam grown oxide sandwiched between two layers of oxide grown in a dry atmosphere.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: October 15, 1991
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Frank R. Bryant, Fu-Tai Liou
  • Patent number: 5051380
    Abstract: In a process for producing a semiconductor device, deposition of a CVD-SiO.sub.2 film at a given first O.sub.3 concentration according to a TEOS-SiO.sub.3 reaction is followed by further deposition of a CVD-SiO.sub.2 film at a second O.sub.3 concentration higher than the first O.sub.3 concentration according to the TEOS-O.sub.3 reaction to form a CVD-SiO.sub.2 film having a predetermined thickness and a surface little uneven.
    Type: Grant
    Filed: December 14, 1990
    Date of Patent: September 24, 1991
    Assignees: Semiconductor Process Laboratory Co., Ltd., Alcan-Tech Co., Inc.
    Inventors: Kazuo Maeda, Noboru Tokumasu, Yuko Nishimoto
  • Patent number: 5028566
    Abstract: The manufacture of semiconductor devices and, specifically, deposition of SiO.sub.2 films on semiconductor devices by oxidative decomposition of oligo siloxanes at low temperature is disclosed.
    Type: Grant
    Filed: July 27, 1990
    Date of Patent: July 2, 1991
    Assignee: Air Products and Chemicals, Inc.
    Inventor: Andre Lagendijk