Oxide Films Patents (Class 148/DIG118)
  • Patent number: 5021365
    Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: June 4, 1991
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Kirchner, Alan C. Warren, Jerry M. Woodall, Steven L. Wright
  • Patent number: 5013691
    Abstract: In a radio-frequency plasma deposition reactor (10), SiO.sub.2 is deposited from a source (16) of tetraethoxysilane (TEOS). The deposition is made to be anisotropic, that is, to be deposited preferentially on horizontal surfaces, by use in the deposition atmosphere of a constituency such as NH.sub.3 or NF.sub.3 which inhibits SiO.sub.2 deposition, along with a radio-frequency power in excess of 100 watts, which preferentially removes the inhibiting gas from horizontal surfaces through ion impact.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: May 7, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Earl R. Lory, Leonard J. Olmer
  • Patent number: 5008215
    Abstract: A process for preparing high sensitivity indium antimonide film magnetoresistance element. A silicon single crystal wafer is treated with oxidative diffusion to form a layer of silicon oxide on the surface of the silicon single crystal, a layer of indium antimonide is grown on the substrate by vapor deposition, and the indium antimonide layer is then subjected to a specific annealing treatment in which the indium antimonide layer is partially oxidized and then re-crystallized. The resultant magnetoresistance element possessing improved sensitivity, stability and suitable for large scale production is obtained.
    Type: Grant
    Filed: July 7, 1989
    Date of Patent: April 16, 1991
    Assignee: Industrial Technology Research Institute
    Inventors: Duen J. Chen, Guey F. Chi, Ying C. Yeh
  • Patent number: 4948744
    Abstract: In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.
    Type: Grant
    Filed: November 1, 1989
    Date of Patent: August 14, 1990
    Assignee: OKI Electric Industry Co., Ltd.
    Inventor: Akio Kita
  • Patent number: 4927781
    Abstract: A method for forming a semiconductor waveguide includes forming a layer of expitaxial silicon over a substrate. The impurity concentration of the layer is higher than that of the substrate. A second layer of epitaxial silicon is disposed over the upper surface of the layer with a higher resistivity than that of the substrate. A masking layer is then disposed over the substrate and then patterned, and then the layer selectively etched down to the upper surface of the layer. The layer is then porified to form an insulating layer from the layer. The porous film is then converted by oxidation to a silicon dioxide layer. The sidewalls of the resulting ridge are then oxidized to form sidewall layers and then the masking layer removed from the upper layer. The upper surface of ridge is oxidized to form an upper insulating layer to extend the sidewall layer over the entire upper surface and sidewalls of the ridge. A layer of insulating material is then disposed over the substrate.
    Type: Grant
    Filed: March 20, 1989
    Date of Patent: May 22, 1990
    Inventor: Robert O. Miller
  • Patent number: 4920067
    Abstract: Hg.sub.1-x Cd.sub.x Te, Hg.sub.1-x Zn.sub.x Te and other related II-VI ternary semiconductor compounds are important strategic materials for photovoltaic infrared detector applications. Liquid phase epitaxy employing a tellurium-rich molten nonstoichiometric solution is an accepted technology for thin film epitaxial crystal growth.This present invention describes a crystal growth process employing specially encapsulated graphite components which directly facilitate a high volume, high quality large area epitaxial layer production.
    Type: Grant
    Filed: October 5, 1988
    Date of Patent: April 24, 1990
    Inventor: Jamie Knapp
  • Patent number: 4906595
    Abstract: A method of manufacturing a semiconductor device, in which a surface (1) of a silicon wafer (2) is locally provided with an oxidation mask (3), whereupon the wafer is subjected to an oxidation treatment by heating it in an oxidizing gas mixture. According to the invention, the wafer is heated during the treatment in the oxidizing gas mixture to a temperature of 950.degree. to 1050.degree. C. Water is then added to the oxidizing gas mixture. The quantity of added water is initially less than 30% by volume and later larger. Thus, in a comparatively short time a comparatively thick layer of oxide can be formed without defects being formed in silicon lying under the oxide.
    Type: Grant
    Filed: July 21, 1989
    Date of Patent: March 6, 1990
    Assignee: U.S. Philips Corporation
    Inventors: Paulus A. van der Plas, Wilhelmina C. E. Snels
  • Patent number: 4894352
    Abstract: In a low-pressure reactor, the addition of nitrogen trifluoride to a gaseous organosilicon compound such as tetraethoxysilane (TEOS) or tetramethylcyclotetroxysilane (TMCTS) results in surprisingly enhanced silicon dioxide deposition rates. The oxide deposited using this process also has the capability of filling features having aspects ratios up to at least 1.0, and may exhibit low mobile ion concentrations. The process is also applicable for depositing other silicon-containing films such as polysilicon and silicon nitride.
    Type: Grant
    Filed: October 26, 1988
    Date of Patent: January 16, 1990
    Assignee: Texas Instruments Inc.
    Inventors: Andrew P. Lane, Douglas A. Webb, Gene R. Frederick
  • Patent number: 4882300
    Abstract: The present invention relates to a method of forming a single crystalline magnesia spinel film on a single crystalline silicon substrate by the use of the vapor-phase epitaxial method.According to the method of the present invention, at first a first single crystalline magnesia spinel layer having a compositional ratio of magnesium maintained at a nearly stoichiometric compositional ratio is epitaxially grown in a vapor-phase on the single crystalline silicon substrate, and then a second single crystalline magnesia spinel layer having a compositional ratio of magnesium which decreases upward is epitaxially grown in a vapor-phase on the first single crystalline magnesia spinel layer. In the event that a Si film is grown on the single crystalline magnesia spinel film formed by the method of the present invention, out of atoms of Mg and Al taken in the Si film in the initial growth stage of the Si film, a concentration of Mg atoms which react more actively upon Si can be reduced.
    Type: Grant
    Filed: October 6, 1988
    Date of Patent: November 21, 1989
    Assignee: Agency of Industrial Science and Technology
    Inventors: Yasunori Inoue, Hiroshi Hanafusa
  • Patent number: 4863878
    Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.
    Type: Grant
    Filed: April 6, 1987
    Date of Patent: September 5, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Larry R. Hite, Ted Houston, Mishel Matloubian
  • Patent number: 4855258
    Abstract: A process for forming a thin sealing layer of silicon nitride directly upon a silicon substrate to minimize bird's beak encroachment. The process employs in situ fabrication whereby the native oxide is removed from the silicon substrate by etching the hydrogen or hydrogen chloride and followed in direct succession, and in the absence of exposure to an oxidizing environment, with the deposition of a silicon nitride layer by LPCVD. Bird's beak encroachment is incrementally reduced by the absence of the native oxide layer as a path for oxygen species movement during the field oxide growth.
    Type: Grant
    Filed: October 22, 1987
    Date of Patent: August 8, 1989
    Assignee: NCR Corporation
    Inventors: Derryl D. J. Allman, Steven S. Lee
  • Patent number: 4845054
    Abstract: A method for low temperature chemical vapor deposition of an SiO.sub.2 based film on a semiconductor structure using selected alkoxysilanes, in particular tetramethoxysilane, trimethoxysilane and triethoxysilane which decompose pyrolytically at lower temperatures than TEOS (tetraethoxysilanes). Ozone is introduced into the reaction chamber to increase deposition rates, lower reaction temperatures and provide a better quality SiO.sub.2 film by generating a more complete oxidation. Ozone is also employed as a reactant for doping SiO.sub.2 based films with oxides of phosphorus and boron.
    Type: Grant
    Filed: June 29, 1987
    Date of Patent: July 4, 1989
    Assignee: Focus Semiconductor Systems, Inc.
    Inventor: James C. Mitchener
  • Patent number: 4843037
    Abstract: A method of passivating the surface of an indium gallium arsenide substrate by cleaning the indium gallium arsenide substrate in an etching solution and depositing a sodium hydroxide film on the substrate. The step of depositing the sodium hydroxide film is preferably performed by spin-on of a sodium hydroxide solution, followed by drying or annealing. The resulting passivated surface exhibits superior surface recombination velocity characteristics compared to prior art passivation techniques, thereby making possible superior solid state device operating characteristics.
    Type: Grant
    Filed: August 21, 1987
    Date of Patent: June 27, 1989
    Assignee: Bell Communications Research, Inc.
    Inventors: Eli Yablonovitch, Thomas J. Gmitter
  • Patent number: 4833099
    Abstract: A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS device is disclosed. After forming an insulated gate member, which has a silicon-rich tungsten silicide layer overlying a polysilicon layer, it is first oxidized and the oxide is removed to expose WSi for forming a particular source/drain doped device. Then it is annealed in a substantially pure nitrogen ambient for a given time period. A subsequent growth of the reoxidation layer over the gate member by introducing oxygen results in a substantially planarized surface. The combination between tungsten and oxygen is prevented.
    Type: Grant
    Filed: January 7, 1988
    Date of Patent: May 23, 1989
    Assignee: Intel Corporation
    Inventor: Been-Jon Woo
  • Patent number: 4829023
    Abstract: A method for producing a semiconductor laser including successively growing at least two semiconductor layers simultaneously on a substrate, the finally grown layer not containing aluminum and the layer grown immediately before the finally grown layer containing aluminum, etching a stripe groove through the finally grown layer to expose part of the semiconductor layer containing aluminum, growing a second semiconductor layer not including aluminum on the finally grown layer and the exposed surface of the semiconductor layer containing aluminum, and growing a semiconductor layer including aluminum on the second semiconductor layer not containing aluminum.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: May 9, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Nagai, Yutaka Mihashi, Tetsuya Yagi, Yoichiro Ota
  • Patent number: 4810673
    Abstract: Silicon dioxide is deposited by low pressure chemical vapor deposition (LPCVD) from dichlorosilane plus nitrous oxide, using a larger concentration of dichlorosilane than of nitrous oxide.
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: March 7, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Dean W. Freeman
  • Patent number: 4806500
    Abstract: A method of producing a large-scale integrated MOS field effect transistor circuit which includes forming p and n-doped troughs, respectively, in a silicon substrate to accommodate respective n and p-channel transistors, introducing appropriate dopant atoms into the troughs by repeated ion implantations to adjust various transistor cutoff voltages, and masking the various ion implantations with photo resist structures and/or with silicon oxide and silicon nitride structures, respectively, and which includes forming source/drain and gate areas as well as forming intermediate and insulation oxide and a strip conductor plane in accordance with conventional MOS technology methods includes the steps of: applying a total-area oxide film having a first film thickness (d1.sub.
    Type: Grant
    Filed: April 21, 1987
    Date of Patent: February 21, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Adolf Scheibe
  • Patent number: 4784973
    Abstract: A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) control layer. Titanium is thereafter deposited and in another thermal reaction the control layer retards the development of titanium silicide without retarding the development of titanium nitride so that the thickness of titanium silicide is kept small. A double titanium process can also be used.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: November 15, 1988
    Assignee: INMOS Corporation
    Inventors: E. Henry Stevens, Paul J. McClure, Christopher W. Hill
  • Patent number: 4774201
    Abstract: A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS MOSFET device. After forming an insulated gate member, which has a tungsten silicide layer overlying a polysilicon layer, a CVD oxide layer is deposited on the exposed and crystallized tungsten silicide layer to function as a cap prior to the formation of the reoxidation layer. The CVD oxide layer operates to slow the passage of oxygen atoms to combine with the tungsten atoms of the silicide layer but allows free migration of silicon atoms from the polysilicon layer to the tungsten silicide surface and combine with the oxygen atoms in forming a substantially planarized and uncontaminated reoxidation layer without the requirement of a substantially pure nitrogen ambient.
    Type: Grant
    Filed: January 7, 1988
    Date of Patent: September 27, 1988
    Assignee: Intel Corporation
    Inventors: Been-Jon Woo, Wei-Jen Lo
  • Patent number: 4758529
    Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.
    Type: Grant
    Filed: October 31, 1985
    Date of Patent: July 19, 1988
    Assignee: RCA Corporation
    Inventor: Alfred C. Ipri
  • Patent number: 4675978
    Abstract: A method for making a partially radiation hardened oxide comprises forming a first portion of an oxide layer on a semiconductor body of material at a temperature between about 950.degree. C. and 1400.degree. C., preferably between about 1000.degree. C. and 1200.degree. C. Thereafter a second portion of the oxide layer is formed between the semiconductor body and the first oxide layer at a temperature between about 850.degree. C. and 900.degree. C., preferably at about 875.degree. C.
    Type: Grant
    Filed: September 9, 1985
    Date of Patent: June 30, 1987
    Assignee: RCA Corporation
    Inventor: George A. Swartz
  • Patent number: 4665609
    Abstract: The surface of a substrate which includes a plurality of photovoltaic junctions spaced along it is prepared as follows: a first anodic oxide layer is formed to cover the whole surface of the substrate and ensures perfect control of the photovoltaic junctions, a second layer is deposited of metal which is impervious to the radiation to be detected, then through photolithography, only the zones of the second layer that it is desired to render impervious to the radiation to be detected are maintained and the remainder removed; and finally, a layer of dielectric material is deposited to cover the whole surface.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: May 19, 1987
    Assignee: Thomson - CSF
    Inventors: Yves Henry, Andre Nicollet, Michel Villard
  • Patent number: 4665608
    Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).
    Type: Grant
    Filed: December 14, 1984
    Date of Patent: May 19, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuo Okamoto, Hiroshi Harada
  • Patent number: 4661166
    Abstract: The inventive method of manufacturing a semiconductor device is carried out by slicing a silicon single crystal grown by a Czochralski method, thereby to provide a wafer (1), annealing the wafer (1) at a temperature range of 600.degree. C. to 800.degree. C. in an atmosphere including an inert gas and a small amount of oxygen for approximately 2 to 6 hours, thereby to precipitate oxygen (2) in the whole wafer (1), and then annealing the wafer (1) in the temperature range of 1000.degree. C. to 1100.degree. C. in a water vapor atmosphere including chlorine, thereby to form an oxide film (3) on the surface of the wafer (1), whereby a denuded zone (4) is formed beneath the oxide film (3) while crystal defects (5a-5d, 6) serving as a getter of impurities such as metals are formed beneath the denuded zone.
    Type: Grant
    Filed: September 20, 1984
    Date of Patent: April 28, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadashi Hirao
  • Patent number: 4597160
    Abstract: A method for making a TFT comprises forming an amorphous silicon layer having a smooth upper surface. An insulating layer is then formed on the smooth surface at or below the critical temperature for the instantaneous crystallization of amorphous. This slowly converts the amorphous silicon to polycrystalline silicon while retaining the smooth surface. TFTs incorporating the invention have a relatively high field effect (surface) mobility.
    Type: Grant
    Filed: August 9, 1985
    Date of Patent: July 1, 1986
    Assignee: RCA Corporation
    Inventor: Alfred C. Ipri
  • Patent number: 4574466
    Abstract: In a 1.2 micron CMOS process, the gate oxide is formed by growing a 1000 Angstrom thickness of sacrificial oxide, immediately performing an oxide strip and then effecting a thin gate oxidation. The gate oxidation step is characterized by a temperature ramp from 700 to 950 degrees Centigrade in a flow of 9 liters per minute nitrogen and 0.36 liters per minute oxygen. At the 950 degrees Centigrade point, the nitrogen flow ceases and the oxygen flow increases to 9 liters per minute. The temperature is then downwardly ramped to 900 degrees Centigrade.
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: March 11, 1986
    Assignee: GTE Communication Systems Corporation
    Inventors: George F. Hagner, Kothandaraman Ravindhran
  • Patent number: 4566173
    Abstract: The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Werner Gossler, Anneliese Strube, Manfred Zurheide
  • Patent number: 4566171
    Abstract: In the fabrication of buried heterostructure InP/InGaAsP lasers, mask undercutting during the mesa etching step is alleviated by a combination of steps which includes the epitaxial growth of a large bandgap InGaAsP cap layer (1.05 eV.ltorsim.E.sub.g .ltorsim.1.24 eV) and the plasma deposition of a SiO.sub.2 etch masking layer. Alternatively, the cap layer may be a bilayer: an InGaAs layer or narrow bandgap InGaAsP (E.sub.g .ltorsim.1.05 eV), which has low contact resistance, and a thin InP protective layer which reduces undercutting and which is removed after LPE regrowth is complete. In both cases, etching at a low temperature with agitation has been found advantageous.
    Type: Grant
    Filed: June 20, 1983
    Date of Patent: January 28, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Ronald J. Nelson, Randall B. Wilson
  • Patent number: 4566913
    Abstract: Silicon dioxide insulating films for integrated circuits are provided with enhanced electronic properties, including decreased water content and reduced trapping of electrons, by exposing a metal oxide semiconductor wafer including an exposed silicon dioxide layer, in an ambient of flowing inert gas, to heating radiation from a halogen lamp for a duration on the order of ten seconds to achieve annealing temperature in the range 600C.-800C.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Marc H. Brodsky, Zeev A. Weinberg
  • Patent number: 4526629
    Abstract: One or more monolayers of cerium arrayed on the surface of a niobium metal acts as a catalyst to oxidation of the niobium at ambient temperature and results in a very thin, very high quality insulating layer which may be configured by patterning of the catalyst. Significant amounts of Nb.sub.2 O.sub.5 are formed at pressures as low as 6.6.times.10.sup.-6 Pa, promoted by the presence of the cerium. This catalytic activity is related to the trivalent to tetravalent valence change of the cerium during oxidation. The kinetics of Nb.sub.2 O.sub.5 formation beneath the oxidized cerium shows two stages:the first stage is fast growth limited by ion diffusion;the second stage is slow growth limited by electron tunneling.Other catalytic rare earths usable instead of cerium are terbium and praseodymium; other substrate materials usable instead of niobium are aluminum, hafnium, silicon and tantalum, or oxidizable alloys thereof.
    Type: Grant
    Filed: May 15, 1984
    Date of Patent: July 2, 1985
    Assignee: International Business Machines Corporation
    Inventors: Ernst-Eberhard Latta, Maria Ronay