Polycrystalline Patents (Class 148/DIG122)
  • Patent number: 6111191
    Abstract: The invention relates to improved techniques for manufacturing columnar-grained polycrystalline sheets which have particular utility as substrates or wafers for solar cells. The sheet is made from silicon on a setter material which supports the silicon material. The setter material and silicon are subjected to a thermal profile all of which promote columnar growth. The thermal profile sequentially creates a melt region where a thin-film capping layer grows at the top of the silicon, a nucleation region where preferential nucleation occurs at the capping-layer/molten-silicon interface, and then a growth region where both liquid and a growing polycrystalline sheet layer coexist. An annealing region is created where the temperature of the grown polycrystalline silicon sheet layer is controllably reduced to effect stress relief.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: August 29, 2000
    Assignee: AstroPower, Inc.
    Inventors: Robert B. Hall, Allen M. Barnett, Sandra R. Collins, Joseph C. Checchi, David H. Ford, Christopher L. Kendall, James A Rand, Chad B. Moore
  • Patent number: 6074925
    Abstract: The method for fabricating a semiconductor device includes steps of forming a layered structure by sequentially depositing a silicon film containing an impurity, a metal silicide film, and an amorphous silicon film containing an impurity, forming an electrode or an interconnect in a three-layer structure by selectively etching the amorphous silicon film, the metal silicide film and the silicon film in this order, and diffusing the impurity in the amorphous silicon film into the metal silicide film by a thermal process. Thus, the impurity is supplied from the amorphous silicon film to the metal silicide film so that the ion-implantation as required in the prior art is not necessary.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventor: Fumiki Aisou
  • Patent number: 5943550
    Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: August 24, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: H. Jim Fulford, Jr., Derick Wristers
  • Patent number: 5885869
    Abstract: A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber. A doped rough silicon layer is formed in situ superjacent the silicon dioxide layer. This is accomplished by depositing the silicon layer superjacent the silicon dioxide layer and exposing the silicon layer to a source gas, a dopant gas, and energy, preferably in situ to thereby form uniformly doped silicon layer and roughened polysilicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition.Alternatively, a uniformly doped roughened polysilicon layer is formed superjacent the silicon dioxide layer in situ. This formation is achieved by depositing an amorphous silicon layer superjacent the silicon dioxide layer and roughening the amorphous silicon layer in situ.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: March 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Charles Turner, Randhir P. S. Thakur
  • Patent number: 5874129
    Abstract: A method of producing amorphous silicon layers on a substrate by chemical vapor deposition at elevated pressures of at least about 25 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain an amorphous silicon deposit of predetermined microcrystalline density, and the silicon precursor gases fed to the chamber to a preselected high pressure. Doped amorphous silicon films also can be deposited at high deposition rates.The above amorphous silicon films have a low density of nucleation sites; thus when the films are annealed, polycrystalline films having large crystal grains are produced.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: February 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mali Venkatesan
  • Patent number: 5863598
    Abstract: A method of forming a doped silicon film on a substrate. According to the present invention, a substrate is placed in a reaction chamber and heated. Next, a silicon containing gas is fed into the reaction chamber to produce a silicon containing gas partial pressure of between 4 and 20 torr.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: January 26, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Mahalingam Venkatesan, Shulin Wang, Vedapuram S. Achutharaman
  • Patent number: 5811323
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: September 22, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: 5789030
    Abstract: A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: August 4, 1998
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 5652156
    Abstract: A method of forming a multilayered polysilicon gate which inhibits penetration of ions through the polysilicon gate to the underlying gate oxide layer is described. A gate silicon oxide layer is formed over the surface of a semiconductor substrate. A layer of amorphous silicon is grown overlying the gate silicon oxide layer. A layer of polysilicon is grown over the amorphous silicon layer wherein silicon grain boundaries of the polysilicon layer are misaligned with silicon grain boundaries of the amorphous silicon layer. The amorphous silicon and the polysilicon layers are etched away where they are not covered by a mask to form the multilayered polysilicon gate. The mismatched silicon grain boundaries of the multilayered polysilicon gate inhibit ions from penetrating through the polysilicon gate to the underlying gate oxide layer.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: July 29, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Siu-han Liao, Shih Jiaw-Ren
  • Patent number: 5591668
    Abstract: A laser annealing method for a semiconductor thin film for irradiating the semiconductor thin film with a laser beam having a section whose outline includes a straight-line portion, so as to change the crystallinity of the semiconductor thin film is provided, wherein the semiconductor thin film is overlap-irradiated with the laser beam while the laser beam is shifted in a direction different from a direction along the straight-line portion. A thin film semiconductor device fabricated by use of the laser annealing method is also provided.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: January 7, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeki Maegawa, Tetsuya Kawamura, Mamoru Furuta, Yutaka Miyata
  • Patent number: 5496416
    Abstract: The invention relates to techniques for manufacturing columnar-grained polycrystalline sheets which have particular utility as substrates or wafers for solar cells. The sheet is made by applying granular silicon to a setter material which supports the granular material. The setter material and granular silicon are subjected to a thermal profile all of which promote columnar growth by melting the silicon from the top downwardly. The thermal profile sequentially creates a melt region at the top of the granular silicon and then a growth region where both liquid and a growing polycrystalline sheet layer coexist. An annealing region is created where the temperature of the grown polycrystalline silicon sheet layer is controllably reduced to effect stress relief.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: March 5, 1996
    Assignee: Astropower, Inc.
    Inventors: Robert B. Hall, Allen M. Barnett, Sandra R. Collins, Joseph C. Checchi, David H. Ford, Christopher L. Kendall, Steven M. Lampo, James A. Rand
  • Patent number: 5496744
    Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5429961
    Abstract: A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: July 4, 1995
    Assignee: Hyundai Electronics Industries Co. Ltd.
    Inventors: Sang H. Woo, Ha E. Jeon
  • Patent number: 5336335
    Abstract: The invention relates to techniques for manufacturing columnar-grained polycrystalline sheets which have particular utility as substrates or wafers for solar cells. The sheet is made by applying granular silicon to a setter material which supports the granular material. The setter material and granular silicon are subjected to a thermal profile all of which promote columnar growth by melting the silicon from the top downwardly. The thermal profile sequentially creates a melt region at the top of the granular silicon and then a growth region where both liquid and a growing polycrystalline sheet layer coexist. An annealing region is created where the temperature of the grown polycrystalline silicon sheet layer is controllably reduced to effect stress relief.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: August 9, 1994
    Assignee: AstroPower, Inc.
    Inventors: Robert B. Hall, Allen M. Barnett, Jacob E. Brown, Joseph C. Checchi, David H. Ford, Christopher L. Kendall, William P. Mulligan, James A. Rand, Todd R. Ruffins
  • Patent number: 5273911
    Abstract: A method for producing a thin-film solar cell having a thin-film active layer on a graphite sheet substrate includes the steps of adhering two sheets of graphite together, forming semi-conductor thin films serving as active layers on second main surfaces of the two sheets of graphite, and separating the two sheets of graphite from each other. In this structure, stress caused by a difference in expansion coefficients between the upper sheet and the semiconductor thin film is cancelled by stress caused by a difference in expansion coefficients between the lower sheet and the semiconductor thin film. Therefore, curvature of the substrates is prevented whereby subsequent process steps are easily carried out. In addition, the number of products per unit time is doubled, thereby increasing productivity.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: December 28, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hajime Sasaki, Hiroaki Morikawa, Kazuhiko Satoh, Mikio Deguchi
  • Patent number: 5244831
    Abstract: The present invention concerns a method for doping a polysilicon layer with phosphorous in which phosphorous oxychloride is supplied to the silicon wafer near the beginning of the oven temperature ramping of the silicon wafer. By introducing the phosphorous oxychloride earlier than in prior art methods, the present invention can reduce the poly rho and poly rho sigma of the doped polysilicon layer. Alternatively, the root DT of the diffusion of the doped material in the doped silicon region on the silicon wafer can be reduced, which helps to maintain the junction depth of the doped silicon region.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: September 14, 1993
    Assignee: Zilog, Inc.
    Inventors: Gregory Hindman, John Rule, Jack Berg
  • Patent number: 5238879
    Abstract: A method for producing polycrystalline layers having granular crystalline structure is provided. Pursuant to the method, a thin intermediate layer of amorphous is deposited before the deposition of the polycrystalline layer in order to avoid crystal structure influence proceeding from the substrate. The layer is then recrystallized applying a pattern of crystallization points or the amorphous layer. A detrimental effect of the fine-crystalline structure of the substrate is prevented by the amorphous intermediate layer. Pursuant to the present invention, the thin-film technology can also be utilized for polycrystalline silicon layers, this being especially desirable in the manufacture of solar cells.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: August 24, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventor: Rolf Plaettner
  • Patent number: 5221365
    Abstract: A thin film transistor and a photovoltaic cell wherein a polycrystalline semiconductive film, having a large grain size and high carrier mobility obtained by heat treatment of a polycrystalline semiconductive film, an amorphous semiconductive film, a microcrystalline semiconductive film or the like on a substrate with a textured surface, is used as a channel layer or a photo-activation layer, the textured surface being formed by etching one surface of the substrate or forming a textured thin film on the substrate.A method of manufacturing a polycrystalline semiconductive film, wherein a surface of a substrate is etched or a textured thin film is formed on the substrate to form a textured surface, and a polycrystalline semiconductive film, an amorphous semiconductive film, a microcrystalline semiconductive film or the like is formed on the textured surface, and the semiconductive film is polycrystallized by heat treatment.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: June 22, 1993
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeru Noguchi, Hiroshi Iwata, Keiichi Sano
  • Patent number: 5221643
    Abstract: A method for producing polycrystalline semiconductor material layers of, in particular, silicon by vapor phase deposition in a plasma reactor. Hydrogen in its activated condition is supplied to the reaction gas in the reactor through an additional gas feed. In an embodiment, the activation proceeds with a glow cathode located in the hydrogen gas feed. The method enables the deposition of uniform polycrystalline semiconductor material layers at substrate temperatures of from between approximately 100.degree. to about 450.degree. C. The deposition can be implemented onto normal glass substrates in a plasma reactor having a simple structure. The method can be used for the manufacture of transistors through thin-film technology.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: June 22, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventor: Susanne Griep
  • Patent number: 5212118
    Abstract: An apparatus and method for chemical vapor deposition in which the reactants directed toward a substrate to be provided with one or more films are first subjected to an electric field. The electric field is applied between two electrodes and the reactants become polarized in the field, thus stretching their polarized chemical bonds close to the breaking point. The apparatus also applies voltage pulses between one of the electrodes and the substrate. By adjusting the pulse height, pulse width and pulse repetition rates, the chemical bonds of polarized reactants break to produce free radicals and some ions of the desired elements or compounds. The substrate is kept at a given temperature. The free radicals react to deposit the desired film of high purity on the substrate. The deposition characteristics of the deposited films in terms of isotropic, anisotropic and selective deposition are controlled by the pulse height, width, repetition rates and by other process parameters.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: May 18, 1993
    Inventor: Arjun N. Saxena
  • Patent number: 5212119
    Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: May 18, 1993
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyung C. Hah, Jung T. Kim, Yong K. Baek, Hee K. Cheon
  • Patent number: 5202290
    Abstract: Quantum dot and quantum wire semiconductors in the nanosize range are produced by a process which utilizes a microporous aluminum oxide surface layer on an aluminum metal substrate as a template for the semiconducting material. The microporous surface layer is prepared by anodizing an aluminum substrate in an acid bath. Then a metal capable of forming a semiconductor compound is electrodeposited into the surface micropores, the oxide is partially or wholly etched away, and the deposited metal is reacted with a liquid or gaseous reagent to convert it chemically to a semiconducting compound. By the process of the invention, there are produced quantum dot or quantum wire semiconductors in the form of an array of substantially mutually parallel, substantially uniform-sized rods of semiconductor material protruding from an electrically conductive substrate, each rod having a diameter less than 100 nanometers.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: April 13, 1993
    Inventor: Martin Moskovits
  • Patent number: 5192717
    Abstract: A process for forming a high quality polycrystalline semiconductor film on an insulating substrate which comprises using a MW-PCVD apparatus comprising a plasma generation chamber provided with a microwave introducing means and a film-forming chamber connected through a grid electrode to said plasma generation chamber, said film-forming chamber containing said insulating substrate positioned on a substrate holder made of a conductive material being installed therein, producing plasma by contacting a film-forming raw material gas with a microwave energy applied through said microwave introducing means in said plasma generation chamber and introducing said plasma into said film-forming chamber while applying a high frequency voltage with a frequency in the range of from 20 to 500 MHz between said grid electrode and said substrate holder to thereby cause the formation of said polycrystalline semiconductor film on said insulating substrate maintained at a desired temperature.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: March 9, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Soichiro Kawakami, Masahiro Kanai, Takeshi Aoki
  • Patent number: 5180690
    Abstract: A method for the low temperature fabrication of doped polycrystalline semiconductor alloy material. The method includes the steps of exposing a body of semiconductor alloy material to a reaction gas containing at least a source of the dopant element, and establishing an electrical potential sufficient to sputter etch the surface of said layer, while decomposing the reaction gas. This allows for the deposition of a layer of doped amorphous semiconductor alloy material upon the body of semiconductor alloy material. Thereafter, the doped layer of amorphous semiconductor alloy material is exposed to an annealing environment sufficient to at least partially crystallize said amorphous material, and activate the dopant element.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: January 19, 1993
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Wolodymyr Czubatyj, Stanford R. Ovshinsky, Guy C. Wicker, David Beglau, Ronald Himmler, David Jablonski, Subhendu Guha
  • Patent number: 5169806
    Abstract: A resistive heating element is formed by depositing an amorphous silicon film on selected portions of a substrate and heating the deposited amorphous silicon film so that it undergoes solid phase epitaxy to form a (111) textured polycrystalline silicon film. The method is particularly useful for forming electro-thermal transducers for thermal ink jet printheads.
    Type: Grant
    Filed: September 26, 1990
    Date of Patent: December 8, 1992
    Assignee: Xerox Corporation
    Inventors: William G. Hawkins, Olaf Muller
  • Patent number: 5166091
    Abstract: In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.
    Type: Grant
    Filed: May 31, 1991
    Date of Patent: November 24, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Nadia Lifshitz, Ronald J. Schutz
  • Patent number: 5149666
    Abstract: In a semiconductor memory device having a floating gate structure, the floating gate electrode is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film, formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film is formed on the silicon substrate, portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer is formed on the silicon substrate by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film formed on the floating gate electrode can have a high breakdown voltage.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: September 22, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Toshiro Usami
  • Patent number: 5112775
    Abstract: A diamond n-type semiconductor including a substrate and a phosphorus element-doped diamond thin film disposed on the substrate. The diamond thin film is deposited by vaporizing a solution comprising a liquid organic compound as the diamond material with diphosphorus pentoxide (P.sub.2 O.sub.5) dissolved therein, and subjecting the resultant gas to a hot filament CVD method.
    Type: Grant
    Filed: November 7, 1990
    Date of Patent: May 12, 1992
    Assignee: The Tokai University Juridical Foundation
    Inventors: Masamori Iida, Tateki Kurosu, Ken Okano
  • Patent number: 5102813
    Abstract: A thin film transistor is produced by applying onto a non-silicon foundation, a thin film of silicon semiconductor material under such conditions that polycrystalline or microcrystalline material is formed. Source and/or drain regions of doped semiconductor material are then formed onto the film; following by applying insulating material onto the film, and a gate region onto the insulating material. The source and/or drain regions are applied so that such regions have a crystalline structure that depends upon the crystalline structure of the underlying thin film. The resulting source and drain regions have high lateral conductivity so that source and drain contacts can be made with reduced cross-sectional areas. The method may employ a self-alignment process to simplify device production.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: April 7, 1992
    Assignee: Interuniversitair Micro Elektronica
    Inventors: Kazuhiro Kobayashi, Kris A. E. F. Baert, Johan F. A. Nijs
  • Patent number: 5098850
    Abstract: A process for producing a substrate for selective crystal growth, which comprises subjecting a substrate having a layer comprising a first material having higher nucleation density and a layer comprising a second material having lower nucleation density than the first material laminated thereon to application of an electrical field concentrated at a desired region of the layer comprising the second material, thereby removing the region whereby the layer comprising the first material is exposed.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: March 24, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shoji Nishida, Takao Yonehara
  • Patent number: 5096856
    Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.
    Type: Grant
    Filed: October 14, 1989
    Date of Patent: March 17, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Dean W. Freeman
  • Patent number: 5087296
    Abstract: A solar battery comprises a substrate, a first semiconductor layer of a first conduction type comprising a single crystal singly grown on a nucleation surface (S.sub.NDL) formed on the surface of said substrate as the base for growing, said nucleation surface (S.sub.NDL) being comprised of a material which is sufficiently greater in nucleation density (ND) than the material constituting the surface of said substrate and having a sufficiently fine area such that only a single nucleus grows, a second semiconductor layer of a second conduction type different than the conduction type of said first semiconductor layer and means for taking out the power.
    Type: Grant
    Filed: November 8, 1990
    Date of Patent: February 11, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shigeki Kondo, Hidemasa Mizutani
  • Patent number: 5082794
    Abstract: In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
    Type: Grant
    Filed: August 17, 1990
    Date of Patent: January 21, 1992
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, Frank K. Baker, Richard D. Sivan
  • Patent number: 5064779
    Abstract: In a method of manufacturing a poly-Si film, silicon is deposited on a substrate by means of a thermal decomposition of a feed gas and plasma generation. The method comprises the step of arranging said substrate within a reaction apparatus, the step of introducing into said reaction apparatus a feed gas containing a silane-series gas for thermal decomposition of the feed gas at 500.degree. to 800.degree. C., and the step of generating plasma within the feed gas by applying power for generating the plasma simultaneously with the thermal decomposition, said power for plasma generation being controlled at a level lower than the power applied for forming a poly-Si film oriented in the <110> direction, so as to form a poly-Si film substantially oriented in the <100> direction and having a smooth surface.
    Type: Grant
    Filed: January 31, 1990
    Date of Patent: November 12, 1991
    Assignee: President of Kanazawa University
    Inventor: Seiichi Hasegawa
  • Patent number: 5024972
    Abstract: A polysilicon layer may need to have electrical characteristics which are relatively uniform from wafer to wafer. The use of polysilicon as a resistor is one such example. In order to obtain the requisite uniformity, the temperature of the wafers which are receiving the polysilicon must all be the same within a tight tolerance. The reaction takes place in a furnace which takes a long time to reach the requisite temperature tolerance. While the furnace is stabilizing the temperature, oxide, which is an insulator, is growing on the contact locations of the various substrates. To minimize the deleterious oxide formation, a thin layer of polysilicon is deposited at a time significantly prior to the time that the furnace stabilizes which ensures a good, low-resistance contact. The remainder of the polysilicon is then deposited on the thin layer of polysilicon after the temperature has stabilized to obtain the requisite wafer-to-wafer resistance uniformity.
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: June 18, 1991
    Assignee: Motorola, Inc.
    Inventors: Gary A. DePinto, Joe Steinberg, John G. Franka, Michael R. Cherniawski
  • Patent number: 5013690
    Abstract: A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.
    Type: Grant
    Filed: February 1, 1990
    Date of Patent: May 7, 1991
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Arthur K. Hochberg, David L. O'Meara, David A. Roberts
  • Patent number: 4975385
    Abstract: An improved method is disclosed for forming one or more N- LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises the steps of: forming a polysilicon gate electrode over a semiconductor wafer substrate, N- doping the substrate to form one or more N- LDD regions, selectively depositing polysilicon on the polysilicon sidewalls of the gate electrode, and then N+ doping the substrate to form N+ source and drain regions in the substrate using the selectively deposited polysilicon as a mask over the N- LDD regions previously formed in the substrate.
    Type: Grant
    Filed: April 6, 1990
    Date of Patent: December 4, 1990
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, John Borland
  • Patent number: 4968640
    Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing density VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: November 6, 1990
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4963506
    Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.
    Type: Grant
    Filed: April 24, 1989
    Date of Patent: October 16, 1990
    Assignee: Motorola Inc.
    Inventors: Hang M. Liaw, Christian A. Seelbach
  • Patent number: 4927786
    Abstract: Disclosed herein is a process for forming a silicon-containing semiconductor thin film, said process comprising the steps of causing a film-forming raw material gas containing silicon atoms as the conventional atoms in the molecule to be adsorbed in liquid form on the cooled substrate surface and subsequently causing the liquefied film-forming raw material gas to react with chemically active hydrogen atoms, thereby solidifying the silicon-containing material and forming a thin film on the substrate surface.The process of the present invention provides good step coverage and smoothens the substrate surface. It also makes it possible to increase the degree of integration of memory devices, photosensitive devices, image inputting devices, imaging devices, etc. Moreover, it makes it possible to realize the three-dimensional integrated circuits.
    Type: Grant
    Filed: October 20, 1989
    Date of Patent: May 22, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shoji Nishida
  • Patent number: 4900694
    Abstract: A process for the preparation of a multi-layers stacked junction typed thin film transister of which electric amplification factor (.beta.) at the time of the base electrode or the emitter electrode being grounded is about 10 and which has an excellent amplifying operation.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: February 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsumi Nakagawa
  • Patent number: 4897360
    Abstract: Polycrystalline silicon is deposited in a film onto the surface of a substrate which has been carefully prepared to eliminate any defects or contaminants which could nucleate crystal growth on the substrate. The deposition is carried out by low pressure decomposition of silane at substantially 580.degree. C. to cause a film of fine grained crystals of polysilicon to be formed having grain sizes averaging less than about 300 Angstroms after annealing. Such a film is very uniform and smooth, having a surface roughness less than about 100 Angstroms RMS. Annealing of the film and substrate at a low temperature results in a compressive strain in the field that decreases over the annealing time, annealing at high temperatures (e.g., over 1050.degree. C.) yields substantially zero strain in the film, and annealing at intermediate temperatures (e.g., 650.degree. C. to 950.degree. C.) yields tensile strain at varying strain levels depending on the annealing temperature and time.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: January 30, 1990
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Henry Guckel, David W. Burns
  • Patent number: 4891330
    Abstract: A method of fabricating doped microcrystalline semiconductor alloy material which includes a band gap widening element through a glow discharge deposition process by subjecting a precursor mixture which includes a diluent gas to an a.c. glow discharge in the absence of a magnetic field of sufficient strength to induce electron cyclotron resonance.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: January 2, 1990
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Subhendu Guha, Stanford R. Ovshinsky
  • Patent number: 4868140
    Abstract: In a semiconductor device, an active layer is formed on an insulating substrate. The active layer is a polycrystalline semiconductor film having large diameter crystal grain. A carrier mobility of said polycrystalline semiconductor film is not lower than 10 cm.sup.2 /V.multidot.sec.
    Type: Grant
    Filed: June 27, 1988
    Date of Patent: September 19, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 4833095
    Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N Layer. The ohmic contacts for the source and drain N layers are defined several microns away from the schottky junction, resulting in a considerable improvement in device reliability.
    Type: Grant
    Filed: December 4, 1987
    Date of Patent: May 23, 1989
    Assignee: Eaton Corporation
    Inventor: Calviello, Joseph A.
  • Patent number: 4818725
    Abstract: A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.
    Type: Grant
    Filed: July 26, 1988
    Date of Patent: April 4, 1989
    Assignee: Harris Corp.
    Inventors: Richard L. Lichtel, Jr., Lawrence G. Pearce, Dryer A. Matlock
  • Patent number: 4818235
    Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing desnity VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: April 4, 1989
    Assignee: Industry Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4772564
    Abstract: A thin-film solar cell on a substrate is fabricated by selectively introducing nucleation sites into the insulator layer which is formed on the substrate material, and activating the nucleation sites during growth of the semiconductor layers. The solar cell is made up of semiconductor layers formed on a substrate. The substrate includes an insulator containing electrically conducting nucleation sites which is interposed between the electrical contact of the substrate and the adjacent semiconductor. The insulator can also be optically transparent. Grain boundaries and voids terminate on the insulator.
    Type: Grant
    Filed: May 13, 1987
    Date of Patent: September 20, 1988
    Assignee: Astrosystems, Inc.
    Inventors: Allen M. Barnett, Robert B. Hall
  • Patent number: H1249
    Abstract: A process for minimizing or avoiding the corrosion of thermal ink jet heater components by the coating thereof with polycrystalline diamond.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: November 2, 1993
    Inventors: Mary A. Machonkin, Frank Jansen, Michael P. O'Horo
  • Patent number: RE36156
    Abstract: The invention relates to techniques for manufacturing columnar-grained polycrystalline sheets which have particular utility as substrates or wafers for solar cells. The sheet is made by applying granular silicon to a setter material which supports the granular material. The setter material and granular silicon are subjected to a thermal profile all of which promote columnar growth by melting the silicon from the top downwardly. The thermal profile sequentially creates a melt region at the top of the granular silicon and then a growth region where both liquid and a growing polycrystalline sheet layer coexist. An annealing region is created where the temperature of the grown polycrystalline silicon sheet layer is controllably reduced to effect stress relief.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: March 23, 1999
    Assignee: Astropower, Inc.
    Inventors: Robert B. Hall, Allen M. Barnett, Sandra R. Collins, Joseph C. Checchi, David H. Ford, Christopher L. Kendall, Steven M. Lampo, James A. Rand